1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * This file contains the 64-bit "server" PowerPC variant 4 * of the low level exception handling including exception 5 * vectors, exception return, part of the slb and stab 6 * handling and other fixed offset specific things. 7 * 8 * This file is meant to be #included from head_64.S due to 9 * position dependent assembly. 10 * 11 * Most of this originates from head_64.S and thus has the same 12 * copyright history. 13 * 14 */ 15 16#include <asm/hw_irq.h> 17#include <asm/exception-64s.h> 18#include <asm/ptrace.h> 19#include <asm/cpuidle.h> 20#include <asm/head-64.h> 21#include <asm/feature-fixups.h> 22#include <asm/kup.h> 23 24/* PACA save area offsets (exgen, exmc, etc) */ 25#define EX_R9 0 26#define EX_R10 8 27#define EX_R11 16 28#define EX_R12 24 29#define EX_R13 32 30#define EX_DAR 40 31#define EX_DSISR 48 32#define EX_CCR 52 33#define EX_CFAR 56 34#define EX_PPR 64 35#define EX_CTR 72 36.if EX_SIZE != 10 37 .error "EX_SIZE is wrong" 38.endif 39 40/* 41 * Following are fixed section helper macros. 42 * 43 * EXC_REAL_BEGIN/END - real, unrelocated exception vectors 44 * EXC_VIRT_BEGIN/END - virt (AIL), unrelocated exception vectors 45 * TRAMP_REAL_BEGIN - real, unrelocated helpers (virt may call these) 46 * TRAMP_VIRT_BEGIN - virt, unreloc helpers (in practice, real can use) 47 * EXC_COMMON - After switching to virtual, relocated mode. 48 */ 49 50#define EXC_REAL_BEGIN(name, start, size) \ 51 FIXED_SECTION_ENTRY_BEGIN_LOCATION(real_vectors, exc_real_##start##_##name, start, size) 52 53#define EXC_REAL_END(name, start, size) \ 54 FIXED_SECTION_ENTRY_END_LOCATION(real_vectors, exc_real_##start##_##name, start, size) 55 56#define EXC_VIRT_BEGIN(name, start, size) \ 57 FIXED_SECTION_ENTRY_BEGIN_LOCATION(virt_vectors, exc_virt_##start##_##name, start, size) 58 59#define EXC_VIRT_END(name, start, size) \ 60 FIXED_SECTION_ENTRY_END_LOCATION(virt_vectors, exc_virt_##start##_##name, start, size) 61 62#define EXC_COMMON_BEGIN(name) \ 63 USE_TEXT_SECTION(); \ 64 .balign IFETCH_ALIGN_BYTES; \ 65 .global name; \ 66 _ASM_NOKPROBE_SYMBOL(name); \ 67 DEFINE_FIXED_SYMBOL(name); \ 68name: 69 70#define TRAMP_REAL_BEGIN(name) \ 71 FIXED_SECTION_ENTRY_BEGIN(real_trampolines, name) 72 73#define TRAMP_VIRT_BEGIN(name) \ 74 FIXED_SECTION_ENTRY_BEGIN(virt_trampolines, name) 75 76#define EXC_REAL_NONE(start, size) \ 77 FIXED_SECTION_ENTRY_BEGIN_LOCATION(real_vectors, exc_real_##start##_##unused, start, size); \ 78 FIXED_SECTION_ENTRY_END_LOCATION(real_vectors, exc_real_##start##_##unused, start, size) 79 80#define EXC_VIRT_NONE(start, size) \ 81 FIXED_SECTION_ENTRY_BEGIN_LOCATION(virt_vectors, exc_virt_##start##_##unused, start, size); \ 82 FIXED_SECTION_ENTRY_END_LOCATION(virt_vectors, exc_virt_##start##_##unused, start, size) 83 84/* 85 * We're short on space and time in the exception prolog, so we can't 86 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label. 87 * Instead we get the base of the kernel from paca->kernelbase and or in the low 88 * part of label. This requires that the label be within 64KB of kernelbase, and 89 * that kernelbase be 64K aligned. 90 */ 91#define LOAD_HANDLER(reg, label) \ 92 ld reg,PACAKBASE(r13); /* get high part of &label */ \ 93 ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label) 94 95#define __LOAD_HANDLER(reg, label) \ 96 ld reg,PACAKBASE(r13); \ 97 ori reg,reg,(ABS_ADDR(label))@l 98 99/* 100 * Branches from unrelocated code (e.g., interrupts) to labels outside 101 * head-y require >64K offsets. 102 */ 103#define __LOAD_FAR_HANDLER(reg, label) \ 104 ld reg,PACAKBASE(r13); \ 105 ori reg,reg,(ABS_ADDR(label))@l; \ 106 addis reg,reg,(ABS_ADDR(label))@h 107 108/* 109 * Branch to label using its 0xC000 address. This results in instruction 110 * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned 111 * on using mtmsr rather than rfid. 112 * 113 * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than 114 * load KBASE for a slight optimisation. 115 */ 116#define BRANCH_TO_C000(reg, label) \ 117 __LOAD_FAR_HANDLER(reg, label); \ 118 mtctr reg; \ 119 bctr 120 121/* 122 * Interrupt code generation macros 123 */ 124#define IVEC .L_IVEC_\name\() /* Interrupt vector address */ 125#define IHSRR .L_IHSRR_\name\() /* Sets SRR or HSRR registers */ 126#define IHSRR_IF_HVMODE .L_IHSRR_IF_HVMODE_\name\() /* HSRR if HV else SRR */ 127#define IAREA .L_IAREA_\name\() /* PACA save area */ 128#define IVIRT .L_IVIRT_\name\() /* Has virt mode entry point */ 129#define IISIDE .L_IISIDE_\name\() /* Uses SRR0/1 not DAR/DSISR */ 130#define IDAR .L_IDAR_\name\() /* Uses DAR (or SRR0) */ 131#define IDSISR .L_IDSISR_\name\() /* Uses DSISR (or SRR1) */ 132#define ISET_RI .L_ISET_RI_\name\() /* Run common code w/ MSR[RI]=1 */ 133#define IBRANCH_TO_COMMON .L_IBRANCH_TO_COMMON_\name\() /* ENTRY branch to common */ 134#define IREALMODE_COMMON .L_IREALMODE_COMMON_\name\() /* Common runs in realmode */ 135#define IMASK .L_IMASK_\name\() /* IRQ soft-mask bit */ 136#define IKVM_SKIP .L_IKVM_SKIP_\name\() /* Generate KVM skip handler */ 137#define IKVM_REAL .L_IKVM_REAL_\name\() /* Real entry tests KVM */ 138#define __IKVM_REAL(name) .L_IKVM_REAL_ ## name 139#define IKVM_VIRT .L_IKVM_VIRT_\name\() /* Virt entry tests KVM */ 140#define ISTACK .L_ISTACK_\name\() /* Set regular kernel stack */ 141#define __ISTACK(name) .L_ISTACK_ ## name 142#define IKUAP .L_IKUAP_\name\() /* Do KUAP lock */ 143 144#define INT_DEFINE_BEGIN(n) \ 145.macro int_define_ ## n name 146 147#define INT_DEFINE_END(n) \ 148.endm ; \ 149int_define_ ## n n ; \ 150do_define_int n 151 152.macro do_define_int name 153 .ifndef IVEC 154 .error "IVEC not defined" 155 .endif 156 .ifndef IHSRR 157 IHSRR=0 158 .endif 159 .ifndef IHSRR_IF_HVMODE 160 IHSRR_IF_HVMODE=0 161 .endif 162 .ifndef IAREA 163 IAREA=PACA_EXGEN 164 .endif 165 .ifndef IVIRT 166 IVIRT=1 167 .endif 168 .ifndef IISIDE 169 IISIDE=0 170 .endif 171 .ifndef IDAR 172 IDAR=0 173 .endif 174 .ifndef IDSISR 175 IDSISR=0 176 .endif 177 .ifndef ISET_RI 178 ISET_RI=1 179 .endif 180 .ifndef IBRANCH_TO_COMMON 181 IBRANCH_TO_COMMON=1 182 .endif 183 .ifndef IREALMODE_COMMON 184 IREALMODE_COMMON=0 185 .else 186 .if ! IBRANCH_TO_COMMON 187 .error "IREALMODE_COMMON=1 but IBRANCH_TO_COMMON=0" 188 .endif 189 .endif 190 .ifndef IMASK 191 IMASK=0 192 .endif 193 .ifndef IKVM_SKIP 194 IKVM_SKIP=0 195 .endif 196 .ifndef IKVM_REAL 197 IKVM_REAL=0 198 .endif 199 .ifndef IKVM_VIRT 200 IKVM_VIRT=0 201 .endif 202 .ifndef ISTACK 203 ISTACK=1 204 .endif 205 .ifndef IKUAP 206 IKUAP=1 207 .endif 208.endm 209 210#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 211#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 212/* 213 * All interrupts which set HSRR registers, as well as SRESET and MCE and 214 * syscall when invoked with "sc 1" switch to MSR[HV]=1 (HVMODE) to be taken, 215 * so they all generally need to test whether they were taken in guest context. 216 * 217 * Note: SRESET and MCE may also be sent to the guest by the hypervisor, and be 218 * taken with MSR[HV]=0. 219 * 220 * Interrupts which set SRR registers (with the above exceptions) do not 221 * elevate to MSR[HV]=1 mode, though most can be taken when running with 222 * MSR[HV]=1 (e.g., bare metal kernel and userspace). So these interrupts do 223 * not need to test whether a guest is running because they get delivered to 224 * the guest directly, including nested HV KVM guests. 225 * 226 * The exception is PR KVM, where the guest runs with MSR[PR]=1 and the host 227 * runs with MSR[HV]=0, so the host takes all interrupts on behalf of the 228 * guest. PR KVM runs with LPCR[AIL]=0 which causes interrupts to always be 229 * delivered to the real-mode entry point, therefore such interrupts only test 230 * KVM in their real mode handlers, and only when PR KVM is possible. 231 * 232 * Interrupts that are taken in MSR[HV]=0 and escalate to MSR[HV]=1 are always 233 * delivered in real-mode when the MMU is in hash mode because the MMU 234 * registers are not set appropriately to translate host addresses. In nested 235 * radix mode these can be delivered in virt-mode as the host translations are 236 * used implicitly (see: effective LPID, effective PID). 237 */ 238 239/* 240 * If an interrupt is taken while a guest is running, it is immediately routed 241 * to KVM to handle. If both HV and PR KVM arepossible, KVM interrupts go first 242 * to kvmppc_interrupt_hv, which handles the PR guest case. 243 */ 244#define kvmppc_interrupt kvmppc_interrupt_hv 245#else 246#define kvmppc_interrupt kvmppc_interrupt_pr 247#endif 248 249.macro KVMTEST name 250 lbz r10,HSTATE_IN_GUEST(r13) 251 cmpwi r10,0 252 bne \name\()_kvm 253.endm 254 255.macro GEN_KVM name 256 .balign IFETCH_ALIGN_BYTES 257\name\()_kvm: 258 259 .if IKVM_SKIP 260 cmpwi r10,KVM_GUEST_MODE_SKIP 261 beq 89f 262 .else 263BEGIN_FTR_SECTION 264 ld r10,IAREA+EX_CFAR(r13) 265 std r10,HSTATE_CFAR(r13) 266END_FTR_SECTION_IFSET(CPU_FTR_CFAR) 267 .endif 268 269 ld r10,IAREA+EX_CTR(r13) 270 mtctr r10 271BEGIN_FTR_SECTION 272 ld r10,IAREA+EX_PPR(r13) 273 std r10,HSTATE_PPR(r13) 274END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) 275 ld r11,IAREA+EX_R11(r13) 276 ld r12,IAREA+EX_R12(r13) 277 std r12,HSTATE_SCRATCH0(r13) 278 sldi r12,r9,32 279 ld r9,IAREA+EX_R9(r13) 280 ld r10,IAREA+EX_R10(r13) 281 /* HSRR variants have the 0x2 bit added to their trap number */ 282 .if IHSRR_IF_HVMODE 283 BEGIN_FTR_SECTION 284 ori r12,r12,(IVEC + 0x2) 285 FTR_SECTION_ELSE 286 ori r12,r12,(IVEC) 287 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 288 .elseif IHSRR 289 ori r12,r12,(IVEC+ 0x2) 290 .else 291 ori r12,r12,(IVEC) 292 .endif 293 b kvmppc_interrupt 294 295 .if IKVM_SKIP 29689: mtocrf 0x80,r9 297 ld r10,IAREA+EX_CTR(r13) 298 mtctr r10 299 ld r9,IAREA+EX_R9(r13) 300 ld r10,IAREA+EX_R10(r13) 301 ld r11,IAREA+EX_R11(r13) 302 ld r12,IAREA+EX_R12(r13) 303 .if IHSRR_IF_HVMODE 304 BEGIN_FTR_SECTION 305 b kvmppc_skip_Hinterrupt 306 FTR_SECTION_ELSE 307 b kvmppc_skip_interrupt 308 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 309 .elseif IHSRR 310 b kvmppc_skip_Hinterrupt 311 .else 312 b kvmppc_skip_interrupt 313 .endif 314 .endif 315.endm 316 317#else 318.macro KVMTEST name 319.endm 320.macro GEN_KVM name 321.endm 322#endif 323 324/* 325 * This is the BOOK3S interrupt entry code macro. 326 * 327 * This can result in one of several things happening: 328 * - Branch to the _common handler, relocated, in virtual mode. 329 * These are normal interrupts (synchronous and asynchronous) handled by 330 * the kernel. 331 * - Branch to KVM, relocated but real mode interrupts remain in real mode. 332 * These occur when HSTATE_IN_GUEST is set. The interrupt may be caused by 333 * / intended for host or guest kernel, but KVM must always be involved 334 * because the machine state is set for guest execution. 335 * - Branch to the masked handler, unrelocated. 336 * These occur when maskable asynchronous interrupts are taken with the 337 * irq_soft_mask set. 338 * - Branch to an "early" handler in real mode but relocated. 339 * This is done if early=1. MCE and HMI use these to handle errors in real 340 * mode. 341 * - Fall through and continue executing in real, unrelocated mode. 342 * This is done if early=2. 343 */ 344 345.macro GEN_BRANCH_TO_COMMON name, virt 346 .if IREALMODE_COMMON 347 LOAD_HANDLER(r10, \name\()_common) 348 mtctr r10 349 bctr 350 .else 351 .if \virt 352#ifndef CONFIG_RELOCATABLE 353 b \name\()_common_virt 354#else 355 LOAD_HANDLER(r10, \name\()_common_virt) 356 mtctr r10 357 bctr 358#endif 359 .else 360 LOAD_HANDLER(r10, \name\()_common_real) 361 mtctr r10 362 bctr 363 .endif 364 .endif 365.endm 366 367.macro GEN_INT_ENTRY name, virt, ool=0 368 SET_SCRATCH0(r13) /* save r13 */ 369 GET_PACA(r13) 370 std r9,IAREA+EX_R9(r13) /* save r9 */ 371BEGIN_FTR_SECTION 372 mfspr r9,SPRN_PPR 373END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) 374 HMT_MEDIUM 375 std r10,IAREA+EX_R10(r13) /* save r10 - r12 */ 376BEGIN_FTR_SECTION 377 mfspr r10,SPRN_CFAR 378END_FTR_SECTION_IFSET(CPU_FTR_CFAR) 379 .if \ool 380 .if !\virt 381 b tramp_real_\name 382 .pushsection .text 383 TRAMP_REAL_BEGIN(tramp_real_\name) 384 .else 385 b tramp_virt_\name 386 .pushsection .text 387 TRAMP_VIRT_BEGIN(tramp_virt_\name) 388 .endif 389 .endif 390 391BEGIN_FTR_SECTION 392 std r9,IAREA+EX_PPR(r13) 393END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) 394BEGIN_FTR_SECTION 395 std r10,IAREA+EX_CFAR(r13) 396END_FTR_SECTION_IFSET(CPU_FTR_CFAR) 397 INTERRUPT_TO_KERNEL 398 mfctr r10 399 std r10,IAREA+EX_CTR(r13) 400 mfcr r9 401 std r11,IAREA+EX_R11(r13) 402 std r12,IAREA+EX_R12(r13) 403 404 /* 405 * DAR/DSISR, SCRATCH0 must be read before setting MSR[RI], 406 * because a d-side MCE will clobber those registers so is 407 * not recoverable if they are live. 408 */ 409 GET_SCRATCH0(r10) 410 std r10,IAREA+EX_R13(r13) 411 .if IDAR && !IISIDE 412 .if IHSRR 413 mfspr r10,SPRN_HDAR 414 .else 415 mfspr r10,SPRN_DAR 416 .endif 417 std r10,IAREA+EX_DAR(r13) 418 .endif 419 .if IDSISR && !IISIDE 420 .if IHSRR 421 mfspr r10,SPRN_HDSISR 422 .else 423 mfspr r10,SPRN_DSISR 424 .endif 425 stw r10,IAREA+EX_DSISR(r13) 426 .endif 427 428 .if IHSRR_IF_HVMODE 429 BEGIN_FTR_SECTION 430 mfspr r11,SPRN_HSRR0 /* save HSRR0 */ 431 mfspr r12,SPRN_HSRR1 /* and HSRR1 */ 432 FTR_SECTION_ELSE 433 mfspr r11,SPRN_SRR0 /* save SRR0 */ 434 mfspr r12,SPRN_SRR1 /* and SRR1 */ 435 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 436 .elseif IHSRR 437 mfspr r11,SPRN_HSRR0 /* save HSRR0 */ 438 mfspr r12,SPRN_HSRR1 /* and HSRR1 */ 439 .else 440 mfspr r11,SPRN_SRR0 /* save SRR0 */ 441 mfspr r12,SPRN_SRR1 /* and SRR1 */ 442 .endif 443 444 .if IBRANCH_TO_COMMON 445 GEN_BRANCH_TO_COMMON \name \virt 446 .endif 447 448 .if \ool 449 .popsection 450 .endif 451.endm 452 453/* 454 * __GEN_COMMON_ENTRY is required to receive the branch from interrupt 455 * entry, except in the case of the real-mode handlers which require 456 * __GEN_REALMODE_COMMON_ENTRY. 457 * 458 * This switches to virtual mode and sets MSR[RI]. 459 */ 460.macro __GEN_COMMON_ENTRY name 461DEFINE_FIXED_SYMBOL(\name\()_common_real) 462\name\()_common_real: 463 .if IKVM_REAL 464 KVMTEST \name 465 .endif 466 467 ld r10,PACAKMSR(r13) /* get MSR value for kernel */ 468 /* MSR[RI] is clear iff using SRR regs */ 469 .if IHSRR_IF_HVMODE 470 BEGIN_FTR_SECTION 471 xori r10,r10,MSR_RI 472 END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE) 473 .elseif ! IHSRR 474 xori r10,r10,MSR_RI 475 .endif 476 mtmsrd r10 477 478 .if IVIRT 479 .if IKVM_VIRT 480 b 1f /* skip the virt test coming from real */ 481 .endif 482 483 .balign IFETCH_ALIGN_BYTES 484DEFINE_FIXED_SYMBOL(\name\()_common_virt) 485\name\()_common_virt: 486 .if IKVM_VIRT 487 KVMTEST \name 4881: 489 .endif 490 .endif /* IVIRT */ 491.endm 492 493/* 494 * Don't switch to virt mode. Used for early MCE and HMI handlers that 495 * want to run in real mode. 496 */ 497.macro __GEN_REALMODE_COMMON_ENTRY name 498DEFINE_FIXED_SYMBOL(\name\()_common_real) 499\name\()_common_real: 500 .if IKVM_REAL 501 KVMTEST \name 502 .endif 503.endm 504 505.macro __GEN_COMMON_BODY name 506 .if IMASK 507 .if ! ISTACK 508 .error "No support for masked interrupt to use custom stack" 509 .endif 510 511 /* If coming from user, skip soft-mask tests. */ 512 andi. r10,r12,MSR_PR 513 bne 2f 514 515 /* Kernel code running below __end_interrupts is implicitly 516 * soft-masked */ 517 LOAD_HANDLER(r10, __end_interrupts) 518 cmpld r11,r10 519 li r10,IMASK 520 blt- 1f 521 522 /* Test the soft mask state against our interrupt's bit */ 523 lbz r10,PACAIRQSOFTMASK(r13) 5241: andi. r10,r10,IMASK 525 /* Associate vector numbers with bits in paca->irq_happened */ 526 .if IVEC == 0x500 || IVEC == 0xea0 527 li r10,PACA_IRQ_EE 528 .elseif IVEC == 0x900 529 li r10,PACA_IRQ_DEC 530 .elseif IVEC == 0xa00 || IVEC == 0xe80 531 li r10,PACA_IRQ_DBELL 532 .elseif IVEC == 0xe60 533 li r10,PACA_IRQ_HMI 534 .elseif IVEC == 0xf00 535 li r10,PACA_IRQ_PMI 536 .else 537 .abort "Bad maskable vector" 538 .endif 539 540 .if IHSRR_IF_HVMODE 541 BEGIN_FTR_SECTION 542 bne masked_Hinterrupt 543 FTR_SECTION_ELSE 544 bne masked_interrupt 545 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 546 .elseif IHSRR 547 bne masked_Hinterrupt 548 .else 549 bne masked_interrupt 550 .endif 551 .endif 552 553 .if ISTACK 554 andi. r10,r12,MSR_PR /* See if coming from user */ 5552: mr r10,r1 /* Save r1 */ 556 subi r1,r1,INT_FRAME_SIZE /* alloc frame on kernel stack */ 557 beq- 100f 558 ld r1,PACAKSAVE(r13) /* kernel stack to use */ 559100: tdgei r1,-INT_FRAME_SIZE /* trap if r1 is in userspace */ 560 EMIT_BUG_ENTRY 100b,__FILE__,__LINE__,0 561 .endif 562 563 std r9,_CCR(r1) /* save CR in stackframe */ 564 std r11,_NIP(r1) /* save SRR0 in stackframe */ 565 std r12,_MSR(r1) /* save SRR1 in stackframe */ 566 std r10,0(r1) /* make stack chain pointer */ 567 std r0,GPR0(r1) /* save r0 in stackframe */ 568 std r10,GPR1(r1) /* save r1 in stackframe */ 569 570 .if ISET_RI 571 li r10,MSR_RI 572 mtmsrd r10,1 /* Set MSR_RI */ 573 .endif 574 575 .if ISTACK 576 .if IKUAP 577 kuap_save_amr_and_lock r9, r10, cr1, cr0 578 .endif 579 beq 101f /* if from kernel mode */ 580BEGIN_FTR_SECTION 581 ld r9,IAREA+EX_PPR(r13) /* Read PPR from paca */ 582 std r9,_PPR(r1) 583END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) 584101: 585 .else 586 .if IKUAP 587 kuap_save_amr_and_lock r9, r10, cr1 588 .endif 589 .endif 590 591 /* Save original regs values from save area to stack frame. */ 592 ld r9,IAREA+EX_R9(r13) /* move r9, r10 to stackframe */ 593 ld r10,IAREA+EX_R10(r13) 594 std r9,GPR9(r1) 595 std r10,GPR10(r1) 596 ld r9,IAREA+EX_R11(r13) /* move r11 - r13 to stackframe */ 597 ld r10,IAREA+EX_R12(r13) 598 ld r11,IAREA+EX_R13(r13) 599 std r9,GPR11(r1) 600 std r10,GPR12(r1) 601 std r11,GPR13(r1) 602 603 SAVE_NVGPRS(r1) 604 605 .if IDAR 606 .if IISIDE 607 ld r10,_NIP(r1) 608 .else 609 ld r10,IAREA+EX_DAR(r13) 610 .endif 611 std r10,_DAR(r1) 612 .endif 613 614 .if IDSISR 615 .if IISIDE 616 ld r10,_MSR(r1) 617 lis r11,DSISR_SRR1_MATCH_64S@h 618 and r10,r10,r11 619 .else 620 lwz r10,IAREA+EX_DSISR(r13) 621 .endif 622 std r10,_DSISR(r1) 623 .endif 624 625BEGIN_FTR_SECTION 626 ld r10,IAREA+EX_CFAR(r13) 627 std r10,ORIG_GPR3(r1) 628END_FTR_SECTION_IFSET(CPU_FTR_CFAR) 629 ld r10,IAREA+EX_CTR(r13) 630 std r10,_CTR(r1) 631 std r2,GPR2(r1) /* save r2 in stackframe */ 632 SAVE_4GPRS(3, r1) /* save r3 - r6 in stackframe */ 633 SAVE_2GPRS(7, r1) /* save r7, r8 in stackframe */ 634 mflr r9 /* Get LR, later save to stack */ 635 ld r2,PACATOC(r13) /* get kernel TOC into r2 */ 636 std r9,_LINK(r1) 637 lbz r10,PACAIRQSOFTMASK(r13) 638 mfspr r11,SPRN_XER /* save XER in stackframe */ 639 std r10,SOFTE(r1) 640 std r11,_XER(r1) 641 li r9,IVEC 642 std r9,_TRAP(r1) /* set trap number */ 643 li r10,0 644 ld r11,exception_marker@toc(r2) 645 std r10,RESULT(r1) /* clear regs->result */ 646 std r11,STACK_FRAME_OVERHEAD-16(r1) /* mark the frame */ 647.endm 648 649/* 650 * On entry r13 points to the paca, r9-r13 are saved in the paca, 651 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and 652 * SRR1, and relocation is on. 653 * 654 * If stack=0, then the stack is already set in r1, and r1 is saved in r10. 655 * PPR save and CPU accounting is not done for the !stack case (XXX why not?) 656 */ 657.macro GEN_COMMON name 658 __GEN_COMMON_ENTRY \name 659 __GEN_COMMON_BODY \name 660.endm 661 662/* 663 * Restore all registers including H/SRR0/1 saved in a stack frame of a 664 * standard exception. 665 */ 666.macro EXCEPTION_RESTORE_REGS hsrr=0 667 /* Move original SRR0 and SRR1 into the respective regs */ 668 ld r9,_MSR(r1) 669 .if \hsrr 670 mtspr SPRN_HSRR1,r9 671 .else 672 mtspr SPRN_SRR1,r9 673 .endif 674 ld r9,_NIP(r1) 675 .if \hsrr 676 mtspr SPRN_HSRR0,r9 677 .else 678 mtspr SPRN_SRR0,r9 679 .endif 680 ld r9,_CTR(r1) 681 mtctr r9 682 ld r9,_XER(r1) 683 mtxer r9 684 ld r9,_LINK(r1) 685 mtlr r9 686 ld r9,_CCR(r1) 687 mtcr r9 688 REST_8GPRS(2, r1) 689 REST_4GPRS(10, r1) 690 REST_GPR(0, r1) 691 /* restore original r1. */ 692 ld r1,GPR1(r1) 693.endm 694 695/* 696 * There are a few constraints to be concerned with. 697 * - Real mode exceptions code/data must be located at their physical location. 698 * - Virtual mode exceptions must be mapped at their 0xc000... location. 699 * - Fixed location code must not call directly beyond the __end_interrupts 700 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence 701 * must be used. 702 * - LOAD_HANDLER targets must be within first 64K of physical 0 / 703 * virtual 0xc00... 704 * - Conditional branch targets must be within +/-32K of caller. 705 * 706 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and 707 * therefore don't have to run in physically located code or rfid to 708 * virtual mode kernel code. However on relocatable kernels they do have 709 * to branch to KERNELBASE offset because the rest of the kernel (outside 710 * the exception vectors) may be located elsewhere. 711 * 712 * Virtual exceptions correspond with physical, except their entry points 713 * are offset by 0xc000000000000000 and also tend to get an added 0x4000 714 * offset applied. Virtual exceptions are enabled with the Alternate 715 * Interrupt Location (AIL) bit set in the LPCR. However this does not 716 * guarantee they will be delivered virtually. Some conditions (see the ISA) 717 * cause exceptions to be delivered in real mode. 718 * 719 * The scv instructions are a special case. They get a 0x3000 offset applied. 720 * scv exceptions have unique reentrancy properties, see below. 721 * 722 * It's impossible to receive interrupts below 0x300 via AIL. 723 * 724 * KVM: None of the virtual exceptions are from the guest. Anything that 725 * escalated to HV=1 from HV=0 is delivered via real mode handlers. 726 * 727 * 728 * We layout physical memory as follows: 729 * 0x0000 - 0x00ff : Secondary processor spin code 730 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors 731 * 0x1900 - 0x2fff : Real mode trampolines 732 * 0x3000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors 733 * 0x5900 - 0x6fff : Relon mode trampolines 734 * 0x7000 - 0x7fff : FWNMI data area 735 * 0x8000 - .... : Common interrupt handlers, remaining early 736 * setup code, rest of kernel. 737 * 738 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space 739 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE 740 * vectors there. 741 */ 742OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) 743OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x3000) 744OPEN_FIXED_SECTION(virt_vectors, 0x3000, 0x5900) 745OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) 746 747#ifdef CONFIG_PPC_POWERNV 748 .globl start_real_trampolines 749 .globl end_real_trampolines 750 .globl start_virt_trampolines 751 .globl end_virt_trampolines 752#endif 753 754#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) 755/* 756 * Data area reserved for FWNMI option. 757 * This address (0x7000) is fixed by the RPA. 758 * pseries and powernv need to keep the whole page from 759 * 0x7000 to 0x8000 free for use by the firmware 760 */ 761ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) 762OPEN_TEXT_SECTION(0x8000) 763#else 764OPEN_TEXT_SECTION(0x7000) 765#endif 766 767USE_FIXED_SECTION(real_vectors) 768 769/* 770 * This is the start of the interrupt handlers for pSeries 771 * This code runs with relocation off. 772 * Code from here to __end_interrupts gets copied down to real 773 * address 0x100 when we are running a relocatable kernel. 774 * Therefore any relative branches in this section must only 775 * branch to labels in this section. 776 */ 777 .globl __start_interrupts 778__start_interrupts: 779 780/** 781 * Interrupt 0x3000 - System Call Vectored Interrupt (syscall). 782 * This is a synchronous interrupt invoked with the "scv" instruction. The 783 * system call does not alter the HV bit, so it is directed to the OS. 784 * 785 * Handling: 786 * scv instructions enter the kernel without changing EE, RI, ME, or HV. 787 * In particular, this means we can take a maskable interrupt at any point 788 * in the scv handler, which is unlike any other interrupt. This is solved 789 * by treating the instruction addresses below __end_interrupts as being 790 * soft-masked. 791 * 792 * AIL-0 mode scv exceptions go to 0x17000-0x17fff, but we set AIL-3 and 793 * ensure scv is never executed with relocation off, which means AIL-0 794 * should never happen. 795 * 796 * Before leaving the below __end_interrupts text, at least of the following 797 * must be true: 798 * - MSR[PR]=1 (i.e., return to userspace) 799 * - MSR_EE|MSR_RI is set (no reentrant exceptions) 800 * - Standard kernel environment is set up (stack, paca, etc) 801 * 802 * Call convention: 803 * 804 * syscall register convention is in Documentation/powerpc/syscall64-abi.rst 805 */ 806EXC_VIRT_BEGIN(system_call_vectored, 0x3000, 0x1000) 807 /* SCV 0 */ 808 mr r9,r13 809 GET_PACA(r13) 810 mflr r11 811 mfctr r12 812 li r10,IRQS_ALL_DISABLED 813 stb r10,PACAIRQSOFTMASK(r13) 814#ifdef CONFIG_RELOCATABLE 815 b system_call_vectored_tramp 816#else 817 b system_call_vectored_common 818#endif 819 nop 820 821 /* SCV 1 - 127 */ 822 .rept 127 823 mr r9,r13 824 GET_PACA(r13) 825 mflr r11 826 mfctr r12 827 li r10,IRQS_ALL_DISABLED 828 stb r10,PACAIRQSOFTMASK(r13) 829 li r0,-1 /* cause failure */ 830#ifdef CONFIG_RELOCATABLE 831 b system_call_vectored_sigill_tramp 832#else 833 b system_call_vectored_sigill 834#endif 835 .endr 836EXC_VIRT_END(system_call_vectored, 0x3000, 0x1000) 837 838#ifdef CONFIG_RELOCATABLE 839TRAMP_VIRT_BEGIN(system_call_vectored_tramp) 840 __LOAD_HANDLER(r10, system_call_vectored_common) 841 mtctr r10 842 bctr 843 844TRAMP_VIRT_BEGIN(system_call_vectored_sigill_tramp) 845 __LOAD_HANDLER(r10, system_call_vectored_sigill) 846 mtctr r10 847 bctr 848#endif 849 850 851/* No virt vectors corresponding with 0x0..0x100 */ 852EXC_VIRT_NONE(0x4000, 0x100) 853 854 855/** 856 * Interrupt 0x100 - System Reset Interrupt (SRESET aka NMI). 857 * This is a non-maskable, asynchronous interrupt always taken in real-mode. 858 * It is caused by: 859 * - Wake from power-saving state, on powernv. 860 * - An NMI from another CPU, triggered by firmware or hypercall. 861 * - As crash/debug signal injected from BMC, firmware or hypervisor. 862 * 863 * Handling: 864 * Power-save wakeup is the only performance critical path, so this is 865 * determined quickly as possible first. In this case volatile registers 866 * can be discarded and SPRs like CFAR don't need to be read. 867 * 868 * If not a powersave wakeup, then it's run as a regular interrupt, however 869 * it uses its own stack and PACA save area to preserve the regular kernel 870 * environment for debugging. 871 * 872 * This interrupt is not maskable, so triggering it when MSR[RI] is clear, 873 * or SCRATCH0 is in use, etc. may cause a crash. It's also not entirely 874 * correct to switch to virtual mode to run the regular interrupt handler 875 * because it might be interrupted when the MMU is in a bad state (e.g., SLB 876 * is clear). 877 * 878 * FWNMI: 879 * PAPR specifies a "fwnmi" facility which sends the sreset to a different 880 * entry point with a different register set up. Some hypervisors will 881 * send the sreset to 0x100 in the guest if it is not fwnmi capable. 882 * 883 * KVM: 884 * Unlike most SRR interrupts, this may be taken by the host while executing 885 * in a guest, so a KVM test is required. KVM will pull the CPU out of guest 886 * mode and then raise the sreset. 887 */ 888INT_DEFINE_BEGIN(system_reset) 889 IVEC=0x100 890 IAREA=PACA_EXNMI 891 IVIRT=0 /* no virt entry point */ 892 /* 893 * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is 894 * being used, so a nested NMI exception would corrupt it. 895 */ 896 ISET_RI=0 897 ISTACK=0 898 IKVM_REAL=1 899INT_DEFINE_END(system_reset) 900 901EXC_REAL_BEGIN(system_reset, 0x100, 0x100) 902#ifdef CONFIG_PPC_P7_NAP 903 /* 904 * If running native on arch 2.06 or later, check if we are waking up 905 * from nap/sleep/winkle, and branch to idle handler. This tests SRR1 906 * bits 46:47. A non-0 value indicates that we are coming from a power 907 * saving state. The idle wakeup handler initially runs in real mode, 908 * but we branch to the 0xc000... address so we can turn on relocation 909 * with mtmsrd later, after SPRs are restored. 910 * 911 * Careful to minimise cost for the fast path (idle wakeup) while 912 * also avoiding clobbering CFAR for the debug path (non-idle). 913 * 914 * For the idle wake case volatile registers can be clobbered, which 915 * is why we use those initially. If it turns out to not be an idle 916 * wake, carefully put everything back the way it was, so we can use 917 * common exception macros to handle it. 918 */ 919BEGIN_FTR_SECTION 920 SET_SCRATCH0(r13) 921 GET_PACA(r13) 922 std r3,PACA_EXNMI+0*8(r13) 923 std r4,PACA_EXNMI+1*8(r13) 924 std r5,PACA_EXNMI+2*8(r13) 925 mfspr r3,SPRN_SRR1 926 mfocrf r4,0x80 927 rlwinm. r5,r3,47-31,30,31 928 bne+ system_reset_idle_wake 929 /* Not powersave wakeup. Restore regs for regular interrupt handler. */ 930 mtocrf 0x80,r4 931 ld r3,PACA_EXNMI+0*8(r13) 932 ld r4,PACA_EXNMI+1*8(r13) 933 ld r5,PACA_EXNMI+2*8(r13) 934 GET_SCRATCH0(r13) 935END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 936#endif 937 938 GEN_INT_ENTRY system_reset, virt=0 939 /* 940 * In theory, we should not enable relocation here if it was disabled 941 * in SRR1, because the MMU may not be configured to support it (e.g., 942 * SLB may have been cleared). In practice, there should only be a few 943 * small windows where that's the case, and sreset is considered to 944 * be dangerous anyway. 945 */ 946EXC_REAL_END(system_reset, 0x100, 0x100) 947EXC_VIRT_NONE(0x4100, 0x100) 948 949#ifdef CONFIG_PPC_P7_NAP 950TRAMP_REAL_BEGIN(system_reset_idle_wake) 951 /* We are waking up from idle, so may clobber any volatile register */ 952 cmpwi cr1,r5,2 953 bltlr cr1 /* no state loss, return to idle caller with r3=SRR1 */ 954 BRANCH_TO_C000(r12, DOTSYM(idle_return_gpr_loss)) 955#endif 956 957#ifdef CONFIG_PPC_PSERIES 958/* 959 * Vectors for the FWNMI option. Share common code. 960 */ 961TRAMP_REAL_BEGIN(system_reset_fwnmi) 962 GEN_INT_ENTRY system_reset, virt=0 963 964#endif /* CONFIG_PPC_PSERIES */ 965 966EXC_COMMON_BEGIN(system_reset_common) 967 __GEN_COMMON_ENTRY system_reset 968 /* 969 * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able 970 * to recover, but nested NMI will notice in_nmi and not recover 971 * because of the use of the NMI stack. in_nmi reentrancy is tested in 972 * system_reset_exception. 973 */ 974 lhz r10,PACA_IN_NMI(r13) 975 addi r10,r10,1 976 sth r10,PACA_IN_NMI(r13) 977 li r10,MSR_RI 978 mtmsrd r10,1 979 980 mr r10,r1 981 ld r1,PACA_NMI_EMERG_SP(r13) 982 subi r1,r1,INT_FRAME_SIZE 983 __GEN_COMMON_BODY system_reset 984 985 addi r3,r1,STACK_FRAME_OVERHEAD 986 bl system_reset_exception 987 988 /* Clear MSR_RI before setting SRR0 and SRR1. */ 989 li r9,0 990 mtmsrd r9,1 991 992 /* 993 * MSR_RI is clear, now we can decrement paca->in_nmi. 994 */ 995 lhz r10,PACA_IN_NMI(r13) 996 subi r10,r10,1 997 sth r10,PACA_IN_NMI(r13) 998 999 kuap_kernel_restore r9, r10 1000 EXCEPTION_RESTORE_REGS 1001 RFI_TO_USER_OR_KERNEL 1002 1003 GEN_KVM system_reset 1004 1005 1006/** 1007 * Interrupt 0x200 - Machine Check Interrupt (MCE). 1008 * This is a non-maskable interrupt always taken in real-mode. It can be 1009 * synchronous or asynchronous, caused by hardware or software, and it may be 1010 * taken in a power-saving state. 1011 * 1012 * Handling: 1013 * Similarly to system reset, this uses its own stack and PACA save area, 1014 * the difference is re-entrancy is allowed on the machine check stack. 1015 * 1016 * machine_check_early is run in real mode, and carefully decodes the 1017 * machine check and tries to handle it (e.g., flush the SLB if there was an 1018 * error detected there), determines if it was recoverable and logs the 1019 * event. 1020 * 1021 * This early code does not "reconcile" irq soft-mask state like SRESET or 1022 * regular interrupts do, so irqs_disabled() among other things may not work 1023 * properly (irq disable/enable already doesn't work because irq tracing can 1024 * not work in real mode). 1025 * 1026 * Then, depending on the execution context when the interrupt is taken, there 1027 * are 3 main actions: 1028 * - Executing in kernel mode. The event is queued with irq_work, which means 1029 * it is handled when it is next safe to do so (i.e., the kernel has enabled 1030 * interrupts), which could be immediately when the interrupt returns. This 1031 * avoids nasty issues like switching to virtual mode when the MMU is in a 1032 * bad state, or when executing OPAL code. (SRESET is exposed to such issues, 1033 * but it has different priorities). Check to see if the CPU was in power 1034 * save, and return via the wake up code if it was. 1035 * 1036 * - Executing in user mode. machine_check_exception is run like a normal 1037 * interrupt handler, which processes the data generated by the early handler. 1038 * 1039 * - Executing in guest mode. The interrupt is run with its KVM test, and 1040 * branches to KVM to deal with. KVM may queue the event for the host 1041 * to report later. 1042 * 1043 * This interrupt is not maskable, so if it triggers when MSR[RI] is clear, 1044 * or SCRATCH0 is in use, it may cause a crash. 1045 * 1046 * KVM: 1047 * See SRESET. 1048 */ 1049INT_DEFINE_BEGIN(machine_check_early) 1050 IVEC=0x200 1051 IAREA=PACA_EXMC 1052 IVIRT=0 /* no virt entry point */ 1053 IREALMODE_COMMON=1 1054 /* 1055 * MSR_RI is not enabled, because PACA_EXMC is being used, so a 1056 * nested machine check corrupts it. machine_check_common enables 1057 * MSR_RI. 1058 */ 1059 ISET_RI=0 1060 ISTACK=0 1061 IDAR=1 1062 IDSISR=1 1063 IKUAP=0 /* We don't touch AMR here, we never go to virtual mode */ 1064INT_DEFINE_END(machine_check_early) 1065 1066INT_DEFINE_BEGIN(machine_check) 1067 IVEC=0x200 1068 IAREA=PACA_EXMC 1069 IVIRT=0 /* no virt entry point */ 1070 ISET_RI=0 1071 IDAR=1 1072 IDSISR=1 1073 IKVM_SKIP=1 1074 IKVM_REAL=1 1075INT_DEFINE_END(machine_check) 1076 1077EXC_REAL_BEGIN(machine_check, 0x200, 0x100) 1078 GEN_INT_ENTRY machine_check_early, virt=0 1079EXC_REAL_END(machine_check, 0x200, 0x100) 1080EXC_VIRT_NONE(0x4200, 0x100) 1081 1082#ifdef CONFIG_PPC_PSERIES 1083TRAMP_REAL_BEGIN(machine_check_fwnmi) 1084 /* See comment at machine_check exception, don't turn on RI */ 1085 GEN_INT_ENTRY machine_check_early, virt=0 1086#endif 1087 1088#define MACHINE_CHECK_HANDLER_WINDUP \ 1089 /* Clear MSR_RI before setting SRR0 and SRR1. */\ 1090 li r9,0; \ 1091 mtmsrd r9,1; /* Clear MSR_RI */ \ 1092 /* Decrement paca->in_mce now RI is clear. */ \ 1093 lhz r12,PACA_IN_MCE(r13); \ 1094 subi r12,r12,1; \ 1095 sth r12,PACA_IN_MCE(r13); \ 1096 EXCEPTION_RESTORE_REGS 1097 1098EXC_COMMON_BEGIN(machine_check_early_common) 1099 __GEN_REALMODE_COMMON_ENTRY machine_check_early 1100 1101 /* 1102 * Switch to mc_emergency stack and handle re-entrancy (we limit 1103 * the nested MCE upto level 4 to avoid stack overflow). 1104 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 1105 * 1106 * We use paca->in_mce to check whether this is the first entry or 1107 * nested machine check. We increment paca->in_mce to track nested 1108 * machine checks. 1109 * 1110 * If this is the first entry then set stack pointer to 1111 * paca->mc_emergency_sp, otherwise r1 is already pointing to 1112 * stack frame on mc_emergency stack. 1113 * 1114 * NOTE: We are here with MSR_ME=0 (off), which means we risk a 1115 * checkstop if we get another machine check exception before we do 1116 * rfid with MSR_ME=1. 1117 * 1118 * This interrupt can wake directly from idle. If that is the case, 1119 * the machine check is handled then the idle wakeup code is called 1120 * to restore state. 1121 */ 1122 lhz r10,PACA_IN_MCE(r13) 1123 cmpwi r10,0 /* Are we in nested machine check */ 1124 cmpwi cr1,r10,MAX_MCE_DEPTH /* Are we at maximum nesting */ 1125 addi r10,r10,1 /* increment paca->in_mce */ 1126 sth r10,PACA_IN_MCE(r13) 1127 1128 mr r10,r1 /* Save r1 */ 1129 bne 1f 1130 /* First machine check entry */ 1131 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ 11321: /* Limit nested MCE to level 4 to avoid stack overflow */ 1133 bgt cr1,unrecoverable_mce /* Check if we hit limit of 4 */ 1134 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 1135 1136 __GEN_COMMON_BODY machine_check_early 1137 1138BEGIN_FTR_SECTION 1139 bl enable_machine_check 1140END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 1141 li r10,MSR_RI 1142 mtmsrd r10,1 1143 1144 addi r3,r1,STACK_FRAME_OVERHEAD 1145 bl machine_check_early 1146 std r3,RESULT(r1) /* Save result */ 1147 ld r12,_MSR(r1) 1148 1149#ifdef CONFIG_PPC_P7_NAP 1150 /* 1151 * Check if thread was in power saving mode. We come here when any 1152 * of the following is true: 1153 * a. thread wasn't in power saving mode 1154 * b. thread was in power saving mode with no state loss, 1155 * supervisor state loss or hypervisor state loss. 1156 * 1157 * Go back to nap/sleep/winkle mode again if (b) is true. 1158 */ 1159BEGIN_FTR_SECTION 1160 rlwinm. r11,r12,47-31,30,31 1161 bne machine_check_idle_common 1162END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 1163#endif 1164 1165#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 1166 /* 1167 * Check if we are coming from guest. If yes, then run the normal 1168 * exception handler which will take the 1169 * machine_check_kvm->kvmppc_interrupt branch to deliver the MC event 1170 * to guest. 1171 */ 1172 lbz r11,HSTATE_IN_GUEST(r13) 1173 cmpwi r11,0 /* Check if coming from guest */ 1174 bne mce_deliver /* continue if we are. */ 1175#endif 1176 1177 /* 1178 * Check if we are coming from userspace. If yes, then run the normal 1179 * exception handler which will deliver the MC event to this kernel. 1180 */ 1181 andi. r11,r12,MSR_PR /* See if coming from user. */ 1182 bne mce_deliver /* continue in V mode if we are. */ 1183 1184 /* 1185 * At this point we are coming from kernel context. 1186 * Queue up the MCE event and return from the interrupt. 1187 * But before that, check if this is an un-recoverable exception. 1188 * If yes, then stay on emergency stack and panic. 1189 */ 1190 andi. r11,r12,MSR_RI 1191 beq unrecoverable_mce 1192 1193 /* 1194 * Check if we have successfully handled/recovered from error, if not 1195 * then stay on emergency stack and panic. 1196 */ 1197 ld r3,RESULT(r1) /* Load result */ 1198 cmpdi r3,0 /* see if we handled MCE successfully */ 1199 beq unrecoverable_mce /* if !handled then panic */ 1200 1201 /* 1202 * Return from MC interrupt. 1203 * Queue up the MCE event so that we can log it later, while 1204 * returning from kernel or opal call. 1205 */ 1206 bl machine_check_queue_event 1207 MACHINE_CHECK_HANDLER_WINDUP 1208 RFI_TO_KERNEL 1209 1210mce_deliver: 1211 /* 1212 * This is a host user or guest MCE. Restore all registers, then 1213 * run the "late" handler. For host user, this will run the 1214 * machine_check_exception handler in virtual mode like a normal 1215 * interrupt handler. For guest, this will trigger the KVM test 1216 * and branch to the KVM interrupt similarly to other interrupts. 1217 */ 1218BEGIN_FTR_SECTION 1219 ld r10,ORIG_GPR3(r1) 1220 mtspr SPRN_CFAR,r10 1221END_FTR_SECTION_IFSET(CPU_FTR_CFAR) 1222 MACHINE_CHECK_HANDLER_WINDUP 1223 GEN_INT_ENTRY machine_check, virt=0 1224 1225EXC_COMMON_BEGIN(machine_check_common) 1226 /* 1227 * Machine check is different because we use a different 1228 * save area: PACA_EXMC instead of PACA_EXGEN. 1229 */ 1230 GEN_COMMON machine_check 1231 1232 /* Enable MSR_RI when finished with PACA_EXMC */ 1233 li r10,MSR_RI 1234 mtmsrd r10,1 1235 addi r3,r1,STACK_FRAME_OVERHEAD 1236 bl machine_check_exception 1237 b interrupt_return 1238 1239 GEN_KVM machine_check 1240 1241 1242#ifdef CONFIG_PPC_P7_NAP 1243/* 1244 * This is an idle wakeup. Low level machine check has already been 1245 * done. Queue the event then call the idle code to do the wake up. 1246 */ 1247EXC_COMMON_BEGIN(machine_check_idle_common) 1248 bl machine_check_queue_event 1249 1250 /* 1251 * GPR-loss wakeups are relatively straightforward, because the 1252 * idle sleep code has saved all non-volatile registers on its 1253 * own stack, and r1 in PACAR1. 1254 * 1255 * For no-loss wakeups the r1 and lr registers used by the 1256 * early machine check handler have to be restored first. r2 is 1257 * the kernel TOC, so no need to restore it. 1258 * 1259 * Then decrement MCE nesting after finishing with the stack. 1260 */ 1261 ld r3,_MSR(r1) 1262 ld r4,_LINK(r1) 1263 ld r1,GPR1(r1) 1264 1265 lhz r11,PACA_IN_MCE(r13) 1266 subi r11,r11,1 1267 sth r11,PACA_IN_MCE(r13) 1268 1269 mtlr r4 1270 rlwinm r10,r3,47-31,30,31 1271 cmpwi cr1,r10,2 1272 bltlr cr1 /* no state loss, return to idle caller with r3=SRR1 */ 1273 b idle_return_gpr_loss 1274#endif 1275 1276EXC_COMMON_BEGIN(unrecoverable_mce) 1277 /* 1278 * We are going down. But there are chances that we might get hit by 1279 * another MCE during panic path and we may run into unstable state 1280 * with no way out. Hence, turn ME bit off while going down, so that 1281 * when another MCE is hit during panic path, system will checkstop 1282 * and hypervisor will get restarted cleanly by SP. 1283 */ 1284BEGIN_FTR_SECTION 1285 li r10,0 /* clear MSR_RI */ 1286 mtmsrd r10,1 1287 bl disable_machine_check 1288END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 1289 ld r10,PACAKMSR(r13) 1290 li r3,MSR_ME 1291 andc r10,r10,r3 1292 mtmsrd r10 1293 1294 lhz r12,PACA_IN_MCE(r13) 1295 subi r12,r12,1 1296 sth r12,PACA_IN_MCE(r13) 1297 1298 /* Invoke machine_check_exception to print MCE event and panic. */ 1299 addi r3,r1,STACK_FRAME_OVERHEAD 1300 bl machine_check_exception 1301 1302 /* 1303 * We will not reach here. Even if we did, there is no way out. 1304 * Call unrecoverable_exception and die. 1305 */ 1306 addi r3,r1,STACK_FRAME_OVERHEAD 1307 bl unrecoverable_exception 1308 b . 1309 1310 1311/** 1312 * Interrupt 0x300 - Data Storage Interrupt (DSI). 1313 * This is a synchronous interrupt generated due to a data access exception, 1314 * e.g., a load orstore which does not have a valid page table entry with 1315 * permissions. DAWR matches also fault here, as do RC updates, and minor misc 1316 * errors e.g., copy/paste, AMO, certain invalid CI accesses, etc. 1317 * 1318 * Handling: 1319 * - Hash MMU 1320 * Go to do_hash_fault, which attempts to fill the HPT from an entry in the 1321 * Linux page table. Hash faults can hit in kernel mode in a fairly 1322 * arbitrary state (e.g., interrupts disabled, locks held) when accessing 1323 * "non-bolted" regions, e.g., vmalloc space. However these should always be 1324 * backed by Linux page table entries. 1325 * 1326 * If no entry is found the Linux page fault handler is invoked (by 1327 * do_hash_fault). Linux page faults can happen in kernel mode due to user 1328 * copy operations of course. 1329 * 1330 * KVM: The KVM HDSI handler may perform a load with MSR[DR]=1 in guest 1331 * MMU context, which may cause a DSI in the host, which must go to the 1332 * KVM handler. MSR[IR] is not enabled, so the real-mode handler will 1333 * always be used regardless of AIL setting. 1334 * 1335 * - Radix MMU 1336 * The hardware loads from the Linux page table directly, so a fault goes 1337 * immediately to Linux page fault. 1338 * 1339 * Conditions like DAWR match are handled on the way in to Linux page fault. 1340 */ 1341INT_DEFINE_BEGIN(data_access) 1342 IVEC=0x300 1343 IDAR=1 1344 IDSISR=1 1345 IKVM_SKIP=1 1346 IKVM_REAL=1 1347INT_DEFINE_END(data_access) 1348 1349EXC_REAL_BEGIN(data_access, 0x300, 0x80) 1350 GEN_INT_ENTRY data_access, virt=0 1351EXC_REAL_END(data_access, 0x300, 0x80) 1352EXC_VIRT_BEGIN(data_access, 0x4300, 0x80) 1353 GEN_INT_ENTRY data_access, virt=1 1354EXC_VIRT_END(data_access, 0x4300, 0x80) 1355EXC_COMMON_BEGIN(data_access_common) 1356 GEN_COMMON data_access 1357 ld r4,_DSISR(r1) 1358 addi r3,r1,STACK_FRAME_OVERHEAD 1359 andis. r0,r4,DSISR_DABRMATCH@h 1360 bne- 1f 1361BEGIN_MMU_FTR_SECTION 1362 bl do_hash_fault 1363MMU_FTR_SECTION_ELSE 1364 bl do_page_fault 1365ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 1366 b interrupt_return 1367 13681: bl do_break 1369 /* 1370 * do_break() may have changed the NV GPRS while handling a breakpoint. 1371 * If so, we need to restore them with their updated values. 1372 */ 1373 REST_NVGPRS(r1) 1374 b interrupt_return 1375 1376 GEN_KVM data_access 1377 1378 1379/** 1380 * Interrupt 0x380 - Data Segment Interrupt (DSLB). 1381 * This is a synchronous interrupt in response to an MMU fault missing SLB 1382 * entry for HPT, or an address outside RPT translation range. 1383 * 1384 * Handling: 1385 * - HPT: 1386 * This refills the SLB, or reports an access fault similarly to a bad page 1387 * fault. When coming from user-mode, the SLB handler may access any kernel 1388 * data, though it may itself take a DSLB. When coming from kernel mode, 1389 * recursive faults must be avoided so access is restricted to the kernel 1390 * image text/data, kernel stack, and any data allocated below 1391 * ppc64_bolted_size (first segment). The kernel handler must avoid stomping 1392 * on user-handler data structures. 1393 * 1394 * KVM: Same as 0x300, DSLB must test for KVM guest. 1395 */ 1396INT_DEFINE_BEGIN(data_access_slb) 1397 IVEC=0x380 1398 IDAR=1 1399 IKVM_SKIP=1 1400 IKVM_REAL=1 1401INT_DEFINE_END(data_access_slb) 1402 1403EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80) 1404 GEN_INT_ENTRY data_access_slb, virt=0 1405EXC_REAL_END(data_access_slb, 0x380, 0x80) 1406EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80) 1407 GEN_INT_ENTRY data_access_slb, virt=1 1408EXC_VIRT_END(data_access_slb, 0x4380, 0x80) 1409EXC_COMMON_BEGIN(data_access_slb_common) 1410 GEN_COMMON data_access_slb 1411BEGIN_MMU_FTR_SECTION 1412 /* HPT case, do SLB fault */ 1413 addi r3,r1,STACK_FRAME_OVERHEAD 1414 bl do_slb_fault 1415 cmpdi r3,0 1416 bne- 1f 1417 b fast_interrupt_return 14181: /* Error case */ 1419MMU_FTR_SECTION_ELSE 1420 /* Radix case, access is outside page table range */ 1421 li r3,-EFAULT 1422ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 1423 std r3,RESULT(r1) 1424 addi r3,r1,STACK_FRAME_OVERHEAD 1425 bl do_bad_slb_fault 1426 b interrupt_return 1427 1428 GEN_KVM data_access_slb 1429 1430 1431/** 1432 * Interrupt 0x400 - Instruction Storage Interrupt (ISI). 1433 * This is a synchronous interrupt in response to an MMU fault due to an 1434 * instruction fetch. 1435 * 1436 * Handling: 1437 * Similar to DSI, though in response to fetch. The faulting address is found 1438 * in SRR0 (rather than DAR), and status in SRR1 (rather than DSISR). 1439 */ 1440INT_DEFINE_BEGIN(instruction_access) 1441 IVEC=0x400 1442 IISIDE=1 1443 IDAR=1 1444 IDSISR=1 1445#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 1446 IKVM_REAL=1 1447#endif 1448INT_DEFINE_END(instruction_access) 1449 1450EXC_REAL_BEGIN(instruction_access, 0x400, 0x80) 1451 GEN_INT_ENTRY instruction_access, virt=0 1452EXC_REAL_END(instruction_access, 0x400, 0x80) 1453EXC_VIRT_BEGIN(instruction_access, 0x4400, 0x80) 1454 GEN_INT_ENTRY instruction_access, virt=1 1455EXC_VIRT_END(instruction_access, 0x4400, 0x80) 1456EXC_COMMON_BEGIN(instruction_access_common) 1457 GEN_COMMON instruction_access 1458 addi r3,r1,STACK_FRAME_OVERHEAD 1459BEGIN_MMU_FTR_SECTION 1460 bl do_hash_fault 1461MMU_FTR_SECTION_ELSE 1462 bl do_page_fault 1463ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 1464 b interrupt_return 1465 1466 GEN_KVM instruction_access 1467 1468 1469/** 1470 * Interrupt 0x480 - Instruction Segment Interrupt (ISLB). 1471 * This is a synchronous interrupt in response to an MMU fault due to an 1472 * instruction fetch. 1473 * 1474 * Handling: 1475 * Similar to DSLB, though in response to fetch. The faulting address is found 1476 * in SRR0 (rather than DAR). 1477 */ 1478INT_DEFINE_BEGIN(instruction_access_slb) 1479 IVEC=0x480 1480 IISIDE=1 1481 IDAR=1 1482#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 1483 IKVM_REAL=1 1484#endif 1485INT_DEFINE_END(instruction_access_slb) 1486 1487EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80) 1488 GEN_INT_ENTRY instruction_access_slb, virt=0 1489EXC_REAL_END(instruction_access_slb, 0x480, 0x80) 1490EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80) 1491 GEN_INT_ENTRY instruction_access_slb, virt=1 1492EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80) 1493EXC_COMMON_BEGIN(instruction_access_slb_common) 1494 GEN_COMMON instruction_access_slb 1495BEGIN_MMU_FTR_SECTION 1496 /* HPT case, do SLB fault */ 1497 addi r3,r1,STACK_FRAME_OVERHEAD 1498 bl do_slb_fault 1499 cmpdi r3,0 1500 bne- 1f 1501 b fast_interrupt_return 15021: /* Error case */ 1503MMU_FTR_SECTION_ELSE 1504 /* Radix case, access is outside page table range */ 1505 li r3,-EFAULT 1506ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 1507 std r3,RESULT(r1) 1508 addi r3,r1,STACK_FRAME_OVERHEAD 1509 bl do_bad_slb_fault 1510 b interrupt_return 1511 1512 GEN_KVM instruction_access_slb 1513 1514 1515/** 1516 * Interrupt 0x500 - External Interrupt. 1517 * This is an asynchronous maskable interrupt in response to an "external 1518 * exception" from the interrupt controller or hypervisor (e.g., device 1519 * interrupt). It is maskable in hardware by clearing MSR[EE], and 1520 * soft-maskable with IRQS_DISABLED mask (i.e., local_irq_disable()). 1521 * 1522 * When running in HV mode, Linux sets up the LPCR[LPES] bit such that 1523 * interrupts are delivered with HSRR registers, guests use SRRs, which 1524 * reqiures IHSRR_IF_HVMODE. 1525 * 1526 * On bare metal POWER9 and later, Linux sets the LPCR[HVICE] bit such that 1527 * external interrupts are delivered as Hypervisor Virtualization Interrupts 1528 * rather than External Interrupts. 1529 * 1530 * Handling: 1531 * This calls into Linux IRQ handler. NVGPRs are not saved to reduce overhead, 1532 * because registers at the time of the interrupt are not so important as it is 1533 * asynchronous. 1534 * 1535 * If soft masked, the masked handler will note the pending interrupt for 1536 * replay, and clear MSR[EE] in the interrupted context. 1537 */ 1538INT_DEFINE_BEGIN(hardware_interrupt) 1539 IVEC=0x500 1540 IHSRR_IF_HVMODE=1 1541 IMASK=IRQS_DISABLED 1542 IKVM_REAL=1 1543 IKVM_VIRT=1 1544INT_DEFINE_END(hardware_interrupt) 1545 1546EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100) 1547 GEN_INT_ENTRY hardware_interrupt, virt=0 1548EXC_REAL_END(hardware_interrupt, 0x500, 0x100) 1549EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100) 1550 GEN_INT_ENTRY hardware_interrupt, virt=1 1551EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100) 1552EXC_COMMON_BEGIN(hardware_interrupt_common) 1553 GEN_COMMON hardware_interrupt 1554 addi r3,r1,STACK_FRAME_OVERHEAD 1555 bl do_IRQ 1556 b interrupt_return 1557 1558 GEN_KVM hardware_interrupt 1559 1560 1561/** 1562 * Interrupt 0x600 - Alignment Interrupt 1563 * This is a synchronous interrupt in response to data alignment fault. 1564 */ 1565INT_DEFINE_BEGIN(alignment) 1566 IVEC=0x600 1567 IDAR=1 1568 IDSISR=1 1569#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 1570 IKVM_REAL=1 1571#endif 1572INT_DEFINE_END(alignment) 1573 1574EXC_REAL_BEGIN(alignment, 0x600, 0x100) 1575 GEN_INT_ENTRY alignment, virt=0 1576EXC_REAL_END(alignment, 0x600, 0x100) 1577EXC_VIRT_BEGIN(alignment, 0x4600, 0x100) 1578 GEN_INT_ENTRY alignment, virt=1 1579EXC_VIRT_END(alignment, 0x4600, 0x100) 1580EXC_COMMON_BEGIN(alignment_common) 1581 GEN_COMMON alignment 1582 addi r3,r1,STACK_FRAME_OVERHEAD 1583 bl alignment_exception 1584 REST_NVGPRS(r1) /* instruction emulation may change GPRs */ 1585 b interrupt_return 1586 1587 GEN_KVM alignment 1588 1589 1590/** 1591 * Interrupt 0x700 - Program Interrupt (program check). 1592 * This is a synchronous interrupt in response to various instruction faults: 1593 * traps, privilege errors, TM errors, floating point exceptions. 1594 * 1595 * Handling: 1596 * This interrupt may use the "emergency stack" in some cases when being taken 1597 * from kernel context, which complicates handling. 1598 */ 1599INT_DEFINE_BEGIN(program_check) 1600 IVEC=0x700 1601#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 1602 IKVM_REAL=1 1603#endif 1604INT_DEFINE_END(program_check) 1605 1606EXC_REAL_BEGIN(program_check, 0x700, 0x100) 1607 1608#ifdef CONFIG_CPU_LITTLE_ENDIAN 1609 /* 1610 * There's a short window during boot where although the kernel is 1611 * running little endian, any exceptions will cause the CPU to switch 1612 * back to big endian. For example a WARN() boils down to a trap 1613 * instruction, which will cause a program check, and we end up here but 1614 * with the CPU in big endian mode. The first instruction of the program 1615 * check handler (in GEN_INT_ENTRY below) is an mtsprg, which when 1616 * executed in the wrong endian is an lhzu with a ~3GB displacement from 1617 * r3. The content of r3 is random, so that is a load from some random 1618 * location, and depending on the system can easily lead to a checkstop, 1619 * or an infinitely recursive page fault. 1620 * 1621 * So to handle that case we have a trampoline here that can detect we 1622 * are in the wrong endian and flip us back to the correct endian. We 1623 * can't flip MSR[LE] using mtmsr, so we have to use rfid. That requires 1624 * backing up SRR0/1 as well as a GPR. To do that we use SPRG0/2/3, as 1625 * SPRG1 is already used for the paca. SPRG3 is user readable, but this 1626 * trampoline is only active very early in boot, and SPRG3 will be 1627 * reinitialised in vdso_getcpu_init() before userspace starts. 1628 */ 1629BEGIN_FTR_SECTION 1630 tdi 0,0,0x48 // Trap never, or in reverse endian: b . + 8 1631 b 1f // Skip trampoline if endian is correct 1632 .long 0xa643707d // mtsprg 0, r11 Backup r11 1633 .long 0xa6027a7d // mfsrr0 r11 1634 .long 0xa643727d // mtsprg 2, r11 Backup SRR0 in SPRG2 1635 .long 0xa6027b7d // mfsrr1 r11 1636 .long 0xa643737d // mtsprg 3, r11 Backup SRR1 in SPRG3 1637 .long 0xa600607d // mfmsr r11 1638 .long 0x01006b69 // xori r11, r11, 1 Invert MSR[LE] 1639 .long 0xa6037b7d // mtsrr1 r11 1640 .long 0x34076039 // li r11, 0x734 1641 .long 0xa6037a7d // mtsrr0 r11 1642 .long 0x2400004c // rfid 1643 mfsprg r11, 3 1644 mtsrr1 r11 // Restore SRR1 1645 mfsprg r11, 2 1646 mtsrr0 r11 // Restore SRR0 1647 mfsprg r11, 0 // Restore r11 16481: 1649END_FTR_SECTION(0, 1) // nop out after boot 1650#endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1651 1652 GEN_INT_ENTRY program_check, virt=0 1653EXC_REAL_END(program_check, 0x700, 0x100) 1654EXC_VIRT_BEGIN(program_check, 0x4700, 0x100) 1655 GEN_INT_ENTRY program_check, virt=1 1656EXC_VIRT_END(program_check, 0x4700, 0x100) 1657EXC_COMMON_BEGIN(program_check_common) 1658 __GEN_COMMON_ENTRY program_check 1659 1660 /* 1661 * It's possible to receive a TM Bad Thing type program check with 1662 * userspace register values (in particular r1), but with SRR1 reporting 1663 * that we came from the kernel. Normally that would confuse the bad 1664 * stack logic, and we would report a bad kernel stack pointer. Instead 1665 * we switch to the emergency stack if we're taking a TM Bad Thing from 1666 * the kernel. 1667 */ 1668 1669 andi. r10,r12,MSR_PR 1670 bne 2f /* If userspace, go normal path */ 1671 1672 andis. r10,r12,(SRR1_PROGTM)@h 1673 bne 1f /* If TM, emergency */ 1674 1675 cmpdi r1,-INT_FRAME_SIZE /* check if r1 is in userspace */ 1676 blt 2f /* normal path if not */ 1677 1678 /* Use the emergency stack */ 16791: andi. r10,r12,MSR_PR /* Set CR0 correctly for label */ 1680 /* 3 in EXCEPTION_PROLOG_COMMON */ 1681 mr r10,r1 /* Save r1 */ 1682 ld r1,PACAEMERGSP(r13) /* Use emergency stack */ 1683 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 1684 __ISTACK(program_check)=0 1685 __GEN_COMMON_BODY program_check 1686 b 3f 16872: 1688 __ISTACK(program_check)=1 1689 __GEN_COMMON_BODY program_check 16903: 1691 addi r3,r1,STACK_FRAME_OVERHEAD 1692 bl program_check_exception 1693 REST_NVGPRS(r1) /* instruction emulation may change GPRs */ 1694 b interrupt_return 1695 1696 GEN_KVM program_check 1697 1698 1699/* 1700 * Interrupt 0x800 - Floating-Point Unavailable Interrupt. 1701 * This is a synchronous interrupt in response to executing an fp instruction 1702 * with MSR[FP]=0. 1703 * 1704 * Handling: 1705 * This will load FP registers and enable the FP bit if coming from userspace, 1706 * otherwise report a bad kernel use of FP. 1707 */ 1708INT_DEFINE_BEGIN(fp_unavailable) 1709 IVEC=0x800 1710#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 1711 IKVM_REAL=1 1712#endif 1713INT_DEFINE_END(fp_unavailable) 1714 1715EXC_REAL_BEGIN(fp_unavailable, 0x800, 0x100) 1716 GEN_INT_ENTRY fp_unavailable, virt=0 1717EXC_REAL_END(fp_unavailable, 0x800, 0x100) 1718EXC_VIRT_BEGIN(fp_unavailable, 0x4800, 0x100) 1719 GEN_INT_ENTRY fp_unavailable, virt=1 1720EXC_VIRT_END(fp_unavailable, 0x4800, 0x100) 1721EXC_COMMON_BEGIN(fp_unavailable_common) 1722 GEN_COMMON fp_unavailable 1723 bne 1f /* if from user, just load it up */ 1724 addi r3,r1,STACK_FRAME_OVERHEAD 1725 bl kernel_fp_unavailable_exception 17260: trap 1727 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0 17281: 1729#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1730BEGIN_FTR_SECTION 1731 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1732 * transaction), go do TM stuff 1733 */ 1734 rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1735 bne- 2f 1736END_FTR_SECTION_IFSET(CPU_FTR_TM) 1737#endif 1738 bl load_up_fpu 1739 b fast_interrupt_return 1740#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 17412: /* User process was in a transaction */ 1742 addi r3,r1,STACK_FRAME_OVERHEAD 1743 bl fp_unavailable_tm 1744 b interrupt_return 1745#endif 1746 1747 GEN_KVM fp_unavailable 1748 1749 1750/** 1751 * Interrupt 0x900 - Decrementer Interrupt. 1752 * This is an asynchronous interrupt in response to a decrementer exception 1753 * (e.g., DEC has wrapped below zero). It is maskable in hardware by clearing 1754 * MSR[EE], and soft-maskable with IRQS_DISABLED mask (i.e., 1755 * local_irq_disable()). 1756 * 1757 * Handling: 1758 * This calls into Linux timer handler. NVGPRs are not saved (see 0x500). 1759 * 1760 * If soft masked, the masked handler will note the pending interrupt for 1761 * replay, and bump the decrementer to a high value, leaving MSR[EE] enabled 1762 * in the interrupted context. 1763 * If PPC_WATCHDOG is configured, the soft masked handler will actually set 1764 * things back up to run soft_nmi_interrupt as a regular interrupt handler 1765 * on the emergency stack. 1766 */ 1767INT_DEFINE_BEGIN(decrementer) 1768 IVEC=0x900 1769 IMASK=IRQS_DISABLED 1770#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 1771 IKVM_REAL=1 1772#endif 1773INT_DEFINE_END(decrementer) 1774 1775EXC_REAL_BEGIN(decrementer, 0x900, 0x80) 1776 GEN_INT_ENTRY decrementer, virt=0 1777EXC_REAL_END(decrementer, 0x900, 0x80) 1778EXC_VIRT_BEGIN(decrementer, 0x4900, 0x80) 1779 GEN_INT_ENTRY decrementer, virt=1 1780EXC_VIRT_END(decrementer, 0x4900, 0x80) 1781EXC_COMMON_BEGIN(decrementer_common) 1782 GEN_COMMON decrementer 1783 addi r3,r1,STACK_FRAME_OVERHEAD 1784 bl timer_interrupt 1785 b interrupt_return 1786 1787 GEN_KVM decrementer 1788 1789 1790/** 1791 * Interrupt 0x980 - Hypervisor Decrementer Interrupt. 1792 * This is an asynchronous interrupt, similar to 0x900 but for the HDEC 1793 * register. 1794 * 1795 * Handling: 1796 * Linux does not use this outside KVM where it's used to keep a host timer 1797 * while the guest is given control of DEC. It should normally be caught by 1798 * the KVM test and routed there. 1799 */ 1800INT_DEFINE_BEGIN(hdecrementer) 1801 IVEC=0x980 1802 IHSRR=1 1803 ISTACK=0 1804 IKVM_REAL=1 1805 IKVM_VIRT=1 1806INT_DEFINE_END(hdecrementer) 1807 1808EXC_REAL_BEGIN(hdecrementer, 0x980, 0x80) 1809 GEN_INT_ENTRY hdecrementer, virt=0 1810EXC_REAL_END(hdecrementer, 0x980, 0x80) 1811EXC_VIRT_BEGIN(hdecrementer, 0x4980, 0x80) 1812 GEN_INT_ENTRY hdecrementer, virt=1 1813EXC_VIRT_END(hdecrementer, 0x4980, 0x80) 1814EXC_COMMON_BEGIN(hdecrementer_common) 1815 __GEN_COMMON_ENTRY hdecrementer 1816 /* 1817 * Hypervisor decrementer interrupts not caught by the KVM test 1818 * shouldn't occur but are sometimes left pending on exit from a KVM 1819 * guest. We don't need to do anything to clear them, as they are 1820 * edge-triggered. 1821 * 1822 * Be careful to avoid touching the kernel stack. 1823 */ 1824 ld r10,PACA_EXGEN+EX_CTR(r13) 1825 mtctr r10 1826 mtcrf 0x80,r9 1827 ld r9,PACA_EXGEN+EX_R9(r13) 1828 ld r10,PACA_EXGEN+EX_R10(r13) 1829 ld r11,PACA_EXGEN+EX_R11(r13) 1830 ld r12,PACA_EXGEN+EX_R12(r13) 1831 ld r13,PACA_EXGEN+EX_R13(r13) 1832 HRFI_TO_KERNEL 1833 1834 GEN_KVM hdecrementer 1835 1836 1837/** 1838 * Interrupt 0xa00 - Directed Privileged Doorbell Interrupt. 1839 * This is an asynchronous interrupt in response to a msgsndp doorbell. 1840 * It is maskable in hardware by clearing MSR[EE], and soft-maskable with 1841 * IRQS_DISABLED mask (i.e., local_irq_disable()). 1842 * 1843 * Handling: 1844 * Guests may use this for IPIs between threads in a core if the 1845 * hypervisor supports it. NVGPRS are not saved (see 0x500). 1846 * 1847 * If soft masked, the masked handler will note the pending interrupt for 1848 * replay, leaving MSR[EE] enabled in the interrupted context because the 1849 * doorbells are edge triggered. 1850 */ 1851INT_DEFINE_BEGIN(doorbell_super) 1852 IVEC=0xa00 1853 IMASK=IRQS_DISABLED 1854#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 1855 IKVM_REAL=1 1856#endif 1857INT_DEFINE_END(doorbell_super) 1858 1859EXC_REAL_BEGIN(doorbell_super, 0xa00, 0x100) 1860 GEN_INT_ENTRY doorbell_super, virt=0 1861EXC_REAL_END(doorbell_super, 0xa00, 0x100) 1862EXC_VIRT_BEGIN(doorbell_super, 0x4a00, 0x100) 1863 GEN_INT_ENTRY doorbell_super, virt=1 1864EXC_VIRT_END(doorbell_super, 0x4a00, 0x100) 1865EXC_COMMON_BEGIN(doorbell_super_common) 1866 GEN_COMMON doorbell_super 1867 addi r3,r1,STACK_FRAME_OVERHEAD 1868#ifdef CONFIG_PPC_DOORBELL 1869 bl doorbell_exception 1870#else 1871 bl unknown_async_exception 1872#endif 1873 b interrupt_return 1874 1875 GEN_KVM doorbell_super 1876 1877 1878EXC_REAL_NONE(0xb00, 0x100) 1879EXC_VIRT_NONE(0x4b00, 0x100) 1880 1881/** 1882 * Interrupt 0xc00 - System Call Interrupt (syscall, hcall). 1883 * This is a synchronous interrupt invoked with the "sc" instruction. The 1884 * system call is invoked with "sc 0" and does not alter the HV bit, so it 1885 * is directed to the currently running OS. The hypercall is invoked with 1886 * "sc 1" and it sets HV=1, so it elevates to hypervisor. 1887 * 1888 * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to 1889 * 0x4c00 virtual mode. 1890 * 1891 * Handling: 1892 * If the KVM test fires then it was due to a hypercall and is accordingly 1893 * routed to KVM. Otherwise this executes a normal Linux system call. 1894 * 1895 * Call convention: 1896 * 1897 * syscall and hypercalls register conventions are documented in 1898 * Documentation/powerpc/syscall64-abi.rst and 1899 * Documentation/powerpc/papr_hcalls.rst respectively. 1900 * 1901 * The intersection of volatile registers that don't contain possible 1902 * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry 1903 * without saving, though xer is not a good idea to use, as hardware may 1904 * interpret some bits so it may be costly to change them. 1905 */ 1906INT_DEFINE_BEGIN(system_call) 1907 IVEC=0xc00 1908 IKVM_REAL=1 1909 IKVM_VIRT=1 1910INT_DEFINE_END(system_call) 1911 1912.macro SYSTEM_CALL virt 1913#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 1914 /* 1915 * There is a little bit of juggling to get syscall and hcall 1916 * working well. Save r13 in ctr to avoid using SPRG scratch 1917 * register. 1918 * 1919 * Userspace syscalls have already saved the PPR, hcalls must save 1920 * it before setting HMT_MEDIUM. 1921 */ 1922 mtctr r13 1923 GET_PACA(r13) 1924 std r10,PACA_EXGEN+EX_R10(r13) 1925 INTERRUPT_TO_KERNEL 1926 KVMTEST system_call /* uses r10, branch to system_call_kvm */ 1927 mfctr r9 1928#else 1929 mr r9,r13 1930 GET_PACA(r13) 1931 INTERRUPT_TO_KERNEL 1932#endif 1933 1934#ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH 1935BEGIN_FTR_SECTION 1936 cmpdi r0,0x1ebe 1937 beq- 1f 1938END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) 1939#endif 1940 1941 /* We reach here with PACA in r13, r13 in r9. */ 1942 mfspr r11,SPRN_SRR0 1943 mfspr r12,SPRN_SRR1 1944 1945 HMT_MEDIUM 1946 1947 .if ! \virt 1948 __LOAD_HANDLER(r10, system_call_common_real) 1949 mtctr r10 1950 bctr 1951 .else 1952 li r10,MSR_RI 1953 mtmsrd r10,1 /* Set RI (EE=0) */ 1954#ifdef CONFIG_RELOCATABLE 1955 __LOAD_HANDLER(r10, system_call_common) 1956 mtctr r10 1957 bctr 1958#else 1959 b system_call_common 1960#endif 1961 .endif 1962 1963#ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH 1964 /* Fast LE/BE switch system call */ 19651: mfspr r12,SPRN_SRR1 1966 xori r12,r12,MSR_LE 1967 mtspr SPRN_SRR1,r12 1968 mr r13,r9 1969 RFI_TO_USER /* return to userspace */ 1970 b . /* prevent speculative execution */ 1971#endif 1972.endm 1973 1974EXC_REAL_BEGIN(system_call, 0xc00, 0x100) 1975 SYSTEM_CALL 0 1976EXC_REAL_END(system_call, 0xc00, 0x100) 1977EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100) 1978 SYSTEM_CALL 1 1979EXC_VIRT_END(system_call, 0x4c00, 0x100) 1980 1981#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 1982TRAMP_REAL_BEGIN(system_call_kvm) 1983 /* 1984 * This is a hcall, so register convention is as above, with these 1985 * differences: 1986 * r13 = PACA 1987 * ctr = orig r13 1988 * orig r10 saved in PACA 1989 */ 1990 /* 1991 * Save the PPR (on systems that support it) before changing to 1992 * HMT_MEDIUM. That allows the KVM code to save that value into the 1993 * guest state (it is the guest's PPR value). 1994 */ 1995BEGIN_FTR_SECTION 1996 mfspr r10,SPRN_PPR 1997 std r10,HSTATE_PPR(r13) 1998END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) 1999 HMT_MEDIUM 2000 mfctr r10 2001 SET_SCRATCH0(r10) 2002 mfcr r10 2003 std r12,HSTATE_SCRATCH0(r13) 2004 sldi r12,r10,32 2005 ori r12,r12,0xc00 2006#ifdef CONFIG_RELOCATABLE 2007 /* 2008 * Requires __LOAD_FAR_HANDLER beause kvmppc_interrupt lives 2009 * outside the head section. 2010 */ 2011 __LOAD_FAR_HANDLER(r10, kvmppc_interrupt) 2012 mtctr r10 2013 ld r10,PACA_EXGEN+EX_R10(r13) 2014 bctr 2015#else 2016 ld r10,PACA_EXGEN+EX_R10(r13) 2017 b kvmppc_interrupt 2018#endif 2019#endif 2020 2021 2022/** 2023 * Interrupt 0xd00 - Trace Interrupt. 2024 * This is a synchronous interrupt in response to instruction step or 2025 * breakpoint faults. 2026 */ 2027INT_DEFINE_BEGIN(single_step) 2028 IVEC=0xd00 2029#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 2030 IKVM_REAL=1 2031#endif 2032INT_DEFINE_END(single_step) 2033 2034EXC_REAL_BEGIN(single_step, 0xd00, 0x100) 2035 GEN_INT_ENTRY single_step, virt=0 2036EXC_REAL_END(single_step, 0xd00, 0x100) 2037EXC_VIRT_BEGIN(single_step, 0x4d00, 0x100) 2038 GEN_INT_ENTRY single_step, virt=1 2039EXC_VIRT_END(single_step, 0x4d00, 0x100) 2040EXC_COMMON_BEGIN(single_step_common) 2041 GEN_COMMON single_step 2042 addi r3,r1,STACK_FRAME_OVERHEAD 2043 bl single_step_exception 2044 b interrupt_return 2045 2046 GEN_KVM single_step 2047 2048 2049/** 2050 * Interrupt 0xe00 - Hypervisor Data Storage Interrupt (HDSI). 2051 * This is a synchronous interrupt in response to an MMU fault caused by a 2052 * guest data access. 2053 * 2054 * Handling: 2055 * This should always get routed to KVM. In radix MMU mode, this is caused 2056 * by a guest nested radix access that can't be performed due to the 2057 * partition scope page table. In hash mode, this can be caused by guests 2058 * running with translation disabled (virtual real mode) or with VPM enabled. 2059 * KVM will update the page table structures or disallow the access. 2060 */ 2061INT_DEFINE_BEGIN(h_data_storage) 2062 IVEC=0xe00 2063 IHSRR=1 2064 IDAR=1 2065 IDSISR=1 2066 IKVM_SKIP=1 2067 IKVM_REAL=1 2068 IKVM_VIRT=1 2069INT_DEFINE_END(h_data_storage) 2070 2071EXC_REAL_BEGIN(h_data_storage, 0xe00, 0x20) 2072 GEN_INT_ENTRY h_data_storage, virt=0, ool=1 2073EXC_REAL_END(h_data_storage, 0xe00, 0x20) 2074EXC_VIRT_BEGIN(h_data_storage, 0x4e00, 0x20) 2075 GEN_INT_ENTRY h_data_storage, virt=1, ool=1 2076EXC_VIRT_END(h_data_storage, 0x4e00, 0x20) 2077EXC_COMMON_BEGIN(h_data_storage_common) 2078 GEN_COMMON h_data_storage 2079 addi r3,r1,STACK_FRAME_OVERHEAD 2080BEGIN_MMU_FTR_SECTION 2081 bl do_bad_page_fault_segv 2082MMU_FTR_SECTION_ELSE 2083 bl unknown_exception 2084ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_TYPE_RADIX) 2085 b interrupt_return 2086 2087 GEN_KVM h_data_storage 2088 2089 2090/** 2091 * Interrupt 0xe20 - Hypervisor Instruction Storage Interrupt (HISI). 2092 * This is a synchronous interrupt in response to an MMU fault caused by a 2093 * guest instruction fetch, similar to HDSI. 2094 */ 2095INT_DEFINE_BEGIN(h_instr_storage) 2096 IVEC=0xe20 2097 IHSRR=1 2098 IKVM_REAL=1 2099 IKVM_VIRT=1 2100INT_DEFINE_END(h_instr_storage) 2101 2102EXC_REAL_BEGIN(h_instr_storage, 0xe20, 0x20) 2103 GEN_INT_ENTRY h_instr_storage, virt=0, ool=1 2104EXC_REAL_END(h_instr_storage, 0xe20, 0x20) 2105EXC_VIRT_BEGIN(h_instr_storage, 0x4e20, 0x20) 2106 GEN_INT_ENTRY h_instr_storage, virt=1, ool=1 2107EXC_VIRT_END(h_instr_storage, 0x4e20, 0x20) 2108EXC_COMMON_BEGIN(h_instr_storage_common) 2109 GEN_COMMON h_instr_storage 2110 addi r3,r1,STACK_FRAME_OVERHEAD 2111 bl unknown_exception 2112 b interrupt_return 2113 2114 GEN_KVM h_instr_storage 2115 2116 2117/** 2118 * Interrupt 0xe40 - Hypervisor Emulation Assistance Interrupt. 2119 */ 2120INT_DEFINE_BEGIN(emulation_assist) 2121 IVEC=0xe40 2122 IHSRR=1 2123 IKVM_REAL=1 2124 IKVM_VIRT=1 2125INT_DEFINE_END(emulation_assist) 2126 2127EXC_REAL_BEGIN(emulation_assist, 0xe40, 0x20) 2128 GEN_INT_ENTRY emulation_assist, virt=0, ool=1 2129EXC_REAL_END(emulation_assist, 0xe40, 0x20) 2130EXC_VIRT_BEGIN(emulation_assist, 0x4e40, 0x20) 2131 GEN_INT_ENTRY emulation_assist, virt=1, ool=1 2132EXC_VIRT_END(emulation_assist, 0x4e40, 0x20) 2133EXC_COMMON_BEGIN(emulation_assist_common) 2134 GEN_COMMON emulation_assist 2135 addi r3,r1,STACK_FRAME_OVERHEAD 2136 bl emulation_assist_interrupt 2137 REST_NVGPRS(r1) /* instruction emulation may change GPRs */ 2138 b interrupt_return 2139 2140 GEN_KVM emulation_assist 2141 2142 2143/** 2144 * Interrupt 0xe60 - Hypervisor Maintenance Interrupt (HMI). 2145 * This is an asynchronous interrupt caused by a Hypervisor Maintenance 2146 * Exception. It is always taken in real mode but uses HSRR registers 2147 * unlike SRESET and MCE. 2148 * 2149 * It is maskable in hardware by clearing MSR[EE], and partially soft-maskable 2150 * with IRQS_DISABLED mask (i.e., local_irq_disable()). 2151 * 2152 * Handling: 2153 * This is a special case, this is handled similarly to machine checks, with an 2154 * initial real mode handler that is not soft-masked, which attempts to fix the 2155 * problem. Then a regular handler which is soft-maskable and reports the 2156 * problem. 2157 * 2158 * The emergency stack is used for the early real mode handler. 2159 * 2160 * XXX: unclear why MCE and HMI schemes could not be made common, e.g., 2161 * either use soft-masking for the MCE, or use irq_work for the HMI. 2162 * 2163 * KVM: 2164 * Unlike MCE, this calls into KVM without calling the real mode handler 2165 * first. 2166 */ 2167INT_DEFINE_BEGIN(hmi_exception_early) 2168 IVEC=0xe60 2169 IHSRR=1 2170 IREALMODE_COMMON=1 2171 ISTACK=0 2172 IKUAP=0 /* We don't touch AMR here, we never go to virtual mode */ 2173 IKVM_REAL=1 2174INT_DEFINE_END(hmi_exception_early) 2175 2176INT_DEFINE_BEGIN(hmi_exception) 2177 IVEC=0xe60 2178 IHSRR=1 2179 IMASK=IRQS_DISABLED 2180 IKVM_REAL=1 2181INT_DEFINE_END(hmi_exception) 2182 2183EXC_REAL_BEGIN(hmi_exception, 0xe60, 0x20) 2184 GEN_INT_ENTRY hmi_exception_early, virt=0, ool=1 2185EXC_REAL_END(hmi_exception, 0xe60, 0x20) 2186EXC_VIRT_NONE(0x4e60, 0x20) 2187 2188EXC_COMMON_BEGIN(hmi_exception_early_common) 2189 __GEN_REALMODE_COMMON_ENTRY hmi_exception_early 2190 2191 mr r10,r1 /* Save r1 */ 2192 ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */ 2193 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 2194 2195 __GEN_COMMON_BODY hmi_exception_early 2196 2197 addi r3,r1,STACK_FRAME_OVERHEAD 2198 bl hmi_exception_realmode 2199 cmpdi cr0,r3,0 2200 bne 1f 2201 2202 EXCEPTION_RESTORE_REGS hsrr=1 2203 HRFI_TO_USER_OR_KERNEL 2204 22051: 2206 /* 2207 * Go to virtual mode and pull the HMI event information from 2208 * firmware. 2209 */ 2210 EXCEPTION_RESTORE_REGS hsrr=1 2211 GEN_INT_ENTRY hmi_exception, virt=0 2212 2213 GEN_KVM hmi_exception_early 2214 2215EXC_COMMON_BEGIN(hmi_exception_common) 2216 GEN_COMMON hmi_exception 2217 addi r3,r1,STACK_FRAME_OVERHEAD 2218 bl handle_hmi_exception 2219 b interrupt_return 2220 2221 GEN_KVM hmi_exception 2222 2223 2224/** 2225 * Interrupt 0xe80 - Directed Hypervisor Doorbell Interrupt. 2226 * This is an asynchronous interrupt in response to a msgsnd doorbell. 2227 * Similar to the 0xa00 doorbell but for host rather than guest. 2228 */ 2229INT_DEFINE_BEGIN(h_doorbell) 2230 IVEC=0xe80 2231 IHSRR=1 2232 IMASK=IRQS_DISABLED 2233 IKVM_REAL=1 2234 IKVM_VIRT=1 2235INT_DEFINE_END(h_doorbell) 2236 2237EXC_REAL_BEGIN(h_doorbell, 0xe80, 0x20) 2238 GEN_INT_ENTRY h_doorbell, virt=0, ool=1 2239EXC_REAL_END(h_doorbell, 0xe80, 0x20) 2240EXC_VIRT_BEGIN(h_doorbell, 0x4e80, 0x20) 2241 GEN_INT_ENTRY h_doorbell, virt=1, ool=1 2242EXC_VIRT_END(h_doorbell, 0x4e80, 0x20) 2243EXC_COMMON_BEGIN(h_doorbell_common) 2244 GEN_COMMON h_doorbell 2245 addi r3,r1,STACK_FRAME_OVERHEAD 2246#ifdef CONFIG_PPC_DOORBELL 2247 bl doorbell_exception 2248#else 2249 bl unknown_async_exception 2250#endif 2251 b interrupt_return 2252 2253 GEN_KVM h_doorbell 2254 2255 2256/** 2257 * Interrupt 0xea0 - Hypervisor Virtualization Interrupt. 2258 * This is an asynchronous interrupt in response to an "external exception". 2259 * Similar to 0x500 but for host only. 2260 */ 2261INT_DEFINE_BEGIN(h_virt_irq) 2262 IVEC=0xea0 2263 IHSRR=1 2264 IMASK=IRQS_DISABLED 2265 IKVM_REAL=1 2266 IKVM_VIRT=1 2267INT_DEFINE_END(h_virt_irq) 2268 2269EXC_REAL_BEGIN(h_virt_irq, 0xea0, 0x20) 2270 GEN_INT_ENTRY h_virt_irq, virt=0, ool=1 2271EXC_REAL_END(h_virt_irq, 0xea0, 0x20) 2272EXC_VIRT_BEGIN(h_virt_irq, 0x4ea0, 0x20) 2273 GEN_INT_ENTRY h_virt_irq, virt=1, ool=1 2274EXC_VIRT_END(h_virt_irq, 0x4ea0, 0x20) 2275EXC_COMMON_BEGIN(h_virt_irq_common) 2276 GEN_COMMON h_virt_irq 2277 addi r3,r1,STACK_FRAME_OVERHEAD 2278 bl do_IRQ 2279 b interrupt_return 2280 2281 GEN_KVM h_virt_irq 2282 2283 2284EXC_REAL_NONE(0xec0, 0x20) 2285EXC_VIRT_NONE(0x4ec0, 0x20) 2286EXC_REAL_NONE(0xee0, 0x20) 2287EXC_VIRT_NONE(0x4ee0, 0x20) 2288 2289 2290/* 2291 * Interrupt 0xf00 - Performance Monitor Interrupt (PMI, PMU). 2292 * This is an asynchronous interrupt in response to a PMU exception. 2293 * It is maskable in hardware by clearing MSR[EE], and soft-maskable with 2294 * IRQS_PMI_DISABLED mask (NOTE: NOT local_irq_disable()). 2295 * 2296 * Handling: 2297 * This calls into the perf subsystem. 2298 * 2299 * Like the watchdog soft-nmi, it appears an NMI interrupt to Linux, in that it 2300 * runs under local_irq_disable. However it may be soft-masked in 2301 * powerpc-specific code. 2302 * 2303 * If soft masked, the masked handler will note the pending interrupt for 2304 * replay, and clear MSR[EE] in the interrupted context. 2305 */ 2306INT_DEFINE_BEGIN(performance_monitor) 2307 IVEC=0xf00 2308 IMASK=IRQS_PMI_DISABLED 2309#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 2310 IKVM_REAL=1 2311#endif 2312INT_DEFINE_END(performance_monitor) 2313 2314EXC_REAL_BEGIN(performance_monitor, 0xf00, 0x20) 2315 GEN_INT_ENTRY performance_monitor, virt=0, ool=1 2316EXC_REAL_END(performance_monitor, 0xf00, 0x20) 2317EXC_VIRT_BEGIN(performance_monitor, 0x4f00, 0x20) 2318 GEN_INT_ENTRY performance_monitor, virt=1, ool=1 2319EXC_VIRT_END(performance_monitor, 0x4f00, 0x20) 2320EXC_COMMON_BEGIN(performance_monitor_common) 2321 GEN_COMMON performance_monitor 2322 addi r3,r1,STACK_FRAME_OVERHEAD 2323 bl performance_monitor_exception 2324 b interrupt_return 2325 2326 GEN_KVM performance_monitor 2327 2328 2329/** 2330 * Interrupt 0xf20 - Vector Unavailable Interrupt. 2331 * This is a synchronous interrupt in response to 2332 * executing a vector (or altivec) instruction with MSR[VEC]=0. 2333 * Similar to FP unavailable. 2334 */ 2335INT_DEFINE_BEGIN(altivec_unavailable) 2336 IVEC=0xf20 2337#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 2338 IKVM_REAL=1 2339#endif 2340INT_DEFINE_END(altivec_unavailable) 2341 2342EXC_REAL_BEGIN(altivec_unavailable, 0xf20, 0x20) 2343 GEN_INT_ENTRY altivec_unavailable, virt=0, ool=1 2344EXC_REAL_END(altivec_unavailable, 0xf20, 0x20) 2345EXC_VIRT_BEGIN(altivec_unavailable, 0x4f20, 0x20) 2346 GEN_INT_ENTRY altivec_unavailable, virt=1, ool=1 2347EXC_VIRT_END(altivec_unavailable, 0x4f20, 0x20) 2348EXC_COMMON_BEGIN(altivec_unavailable_common) 2349 GEN_COMMON altivec_unavailable 2350#ifdef CONFIG_ALTIVEC 2351BEGIN_FTR_SECTION 2352 beq 1f 2353#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 2354 BEGIN_FTR_SECTION_NESTED(69) 2355 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 2356 * transaction), go do TM stuff 2357 */ 2358 rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 2359 bne- 2f 2360 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) 2361#endif 2362 bl load_up_altivec 2363 b fast_interrupt_return 2364#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 23652: /* User process was in a transaction */ 2366 addi r3,r1,STACK_FRAME_OVERHEAD 2367 bl altivec_unavailable_tm 2368 b interrupt_return 2369#endif 23701: 2371END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 2372#endif 2373 addi r3,r1,STACK_FRAME_OVERHEAD 2374 bl altivec_unavailable_exception 2375 b interrupt_return 2376 2377 GEN_KVM altivec_unavailable 2378 2379 2380/** 2381 * Interrupt 0xf40 - VSX Unavailable Interrupt. 2382 * This is a synchronous interrupt in response to 2383 * executing a VSX instruction with MSR[VSX]=0. 2384 * Similar to FP unavailable. 2385 */ 2386INT_DEFINE_BEGIN(vsx_unavailable) 2387 IVEC=0xf40 2388#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 2389 IKVM_REAL=1 2390#endif 2391INT_DEFINE_END(vsx_unavailable) 2392 2393EXC_REAL_BEGIN(vsx_unavailable, 0xf40, 0x20) 2394 GEN_INT_ENTRY vsx_unavailable, virt=0, ool=1 2395EXC_REAL_END(vsx_unavailable, 0xf40, 0x20) 2396EXC_VIRT_BEGIN(vsx_unavailable, 0x4f40, 0x20) 2397 GEN_INT_ENTRY vsx_unavailable, virt=1, ool=1 2398EXC_VIRT_END(vsx_unavailable, 0x4f40, 0x20) 2399EXC_COMMON_BEGIN(vsx_unavailable_common) 2400 GEN_COMMON vsx_unavailable 2401#ifdef CONFIG_VSX 2402BEGIN_FTR_SECTION 2403 beq 1f 2404#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 2405 BEGIN_FTR_SECTION_NESTED(69) 2406 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 2407 * transaction), go do TM stuff 2408 */ 2409 rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 2410 bne- 2f 2411 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) 2412#endif 2413 b load_up_vsx 2414#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 24152: /* User process was in a transaction */ 2416 addi r3,r1,STACK_FRAME_OVERHEAD 2417 bl vsx_unavailable_tm 2418 b interrupt_return 2419#endif 24201: 2421END_FTR_SECTION_IFSET(CPU_FTR_VSX) 2422#endif 2423 addi r3,r1,STACK_FRAME_OVERHEAD 2424 bl vsx_unavailable_exception 2425 b interrupt_return 2426 2427 GEN_KVM vsx_unavailable 2428 2429 2430/** 2431 * Interrupt 0xf60 - Facility Unavailable Interrupt. 2432 * This is a synchronous interrupt in response to 2433 * executing an instruction without access to the facility that can be 2434 * resolved by the OS (e.g., FSCR, MSR). 2435 * Similar to FP unavailable. 2436 */ 2437INT_DEFINE_BEGIN(facility_unavailable) 2438 IVEC=0xf60 2439#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 2440 IKVM_REAL=1 2441#endif 2442INT_DEFINE_END(facility_unavailable) 2443 2444EXC_REAL_BEGIN(facility_unavailable, 0xf60, 0x20) 2445 GEN_INT_ENTRY facility_unavailable, virt=0, ool=1 2446EXC_REAL_END(facility_unavailable, 0xf60, 0x20) 2447EXC_VIRT_BEGIN(facility_unavailable, 0x4f60, 0x20) 2448 GEN_INT_ENTRY facility_unavailable, virt=1, ool=1 2449EXC_VIRT_END(facility_unavailable, 0x4f60, 0x20) 2450EXC_COMMON_BEGIN(facility_unavailable_common) 2451 GEN_COMMON facility_unavailable 2452 addi r3,r1,STACK_FRAME_OVERHEAD 2453 bl facility_unavailable_exception 2454 REST_NVGPRS(r1) /* instruction emulation may change GPRs */ 2455 b interrupt_return 2456 2457 GEN_KVM facility_unavailable 2458 2459 2460/** 2461 * Interrupt 0xf60 - Hypervisor Facility Unavailable Interrupt. 2462 * This is a synchronous interrupt in response to 2463 * executing an instruction without access to the facility that can only 2464 * be resolved in HV mode (e.g., HFSCR). 2465 * Similar to FP unavailable. 2466 */ 2467INT_DEFINE_BEGIN(h_facility_unavailable) 2468 IVEC=0xf80 2469 IHSRR=1 2470 IKVM_REAL=1 2471 IKVM_VIRT=1 2472INT_DEFINE_END(h_facility_unavailable) 2473 2474EXC_REAL_BEGIN(h_facility_unavailable, 0xf80, 0x20) 2475 GEN_INT_ENTRY h_facility_unavailable, virt=0, ool=1 2476EXC_REAL_END(h_facility_unavailable, 0xf80, 0x20) 2477EXC_VIRT_BEGIN(h_facility_unavailable, 0x4f80, 0x20) 2478 GEN_INT_ENTRY h_facility_unavailable, virt=1, ool=1 2479EXC_VIRT_END(h_facility_unavailable, 0x4f80, 0x20) 2480EXC_COMMON_BEGIN(h_facility_unavailable_common) 2481 GEN_COMMON h_facility_unavailable 2482 addi r3,r1,STACK_FRAME_OVERHEAD 2483 bl facility_unavailable_exception 2484 REST_NVGPRS(r1) /* XXX Shouldn't be necessary in practice */ 2485 b interrupt_return 2486 2487 GEN_KVM h_facility_unavailable 2488 2489 2490EXC_REAL_NONE(0xfa0, 0x20) 2491EXC_VIRT_NONE(0x4fa0, 0x20) 2492EXC_REAL_NONE(0xfc0, 0x20) 2493EXC_VIRT_NONE(0x4fc0, 0x20) 2494EXC_REAL_NONE(0xfe0, 0x20) 2495EXC_VIRT_NONE(0x4fe0, 0x20) 2496 2497EXC_REAL_NONE(0x1000, 0x100) 2498EXC_VIRT_NONE(0x5000, 0x100) 2499EXC_REAL_NONE(0x1100, 0x100) 2500EXC_VIRT_NONE(0x5100, 0x100) 2501 2502#ifdef CONFIG_CBE_RAS 2503INT_DEFINE_BEGIN(cbe_system_error) 2504 IVEC=0x1200 2505 IHSRR=1 2506INT_DEFINE_END(cbe_system_error) 2507 2508EXC_REAL_BEGIN(cbe_system_error, 0x1200, 0x100) 2509 GEN_INT_ENTRY cbe_system_error, virt=0 2510EXC_REAL_END(cbe_system_error, 0x1200, 0x100) 2511EXC_VIRT_NONE(0x5200, 0x100) 2512EXC_COMMON_BEGIN(cbe_system_error_common) 2513 GEN_COMMON cbe_system_error 2514 addi r3,r1,STACK_FRAME_OVERHEAD 2515 bl cbe_system_error_exception 2516 b interrupt_return 2517 2518 GEN_KVM cbe_system_error 2519 2520#else /* CONFIG_CBE_RAS */ 2521EXC_REAL_NONE(0x1200, 0x100) 2522EXC_VIRT_NONE(0x5200, 0x100) 2523#endif 2524 2525/** 2526 * Interrupt 0x1300 - Instruction Address Breakpoint Interrupt. 2527 * This has been removed from the ISA before 2.01, which is the earliest 2528 * 64-bit BookS ISA supported, however the G5 / 970 implements this 2529 * interrupt with a non-architected feature available through the support 2530 * processor interface. 2531 */ 2532INT_DEFINE_BEGIN(instruction_breakpoint) 2533 IVEC=0x1300 2534#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 2535 IKVM_REAL=1 2536#endif 2537INT_DEFINE_END(instruction_breakpoint) 2538 2539EXC_REAL_BEGIN(instruction_breakpoint, 0x1300, 0x100) 2540 GEN_INT_ENTRY instruction_breakpoint, virt=0 2541EXC_REAL_END(instruction_breakpoint, 0x1300, 0x100) 2542EXC_VIRT_BEGIN(instruction_breakpoint, 0x5300, 0x100) 2543 GEN_INT_ENTRY instruction_breakpoint, virt=1 2544EXC_VIRT_END(instruction_breakpoint, 0x5300, 0x100) 2545EXC_COMMON_BEGIN(instruction_breakpoint_common) 2546 GEN_COMMON instruction_breakpoint 2547 addi r3,r1,STACK_FRAME_OVERHEAD 2548 bl instruction_breakpoint_exception 2549 b interrupt_return 2550 2551 GEN_KVM instruction_breakpoint 2552 2553 2554EXC_REAL_NONE(0x1400, 0x100) 2555EXC_VIRT_NONE(0x5400, 0x100) 2556 2557/** 2558 * Interrupt 0x1500 - Soft Patch Interrupt 2559 * 2560 * Handling: 2561 * This is an implementation specific interrupt which can be used for a 2562 * range of exceptions. 2563 * 2564 * This interrupt handler is unique in that it runs the denormal assist 2565 * code even for guests (and even in guest context) without going to KVM, 2566 * for speed. POWER9 does not raise denorm exceptions, so this special case 2567 * could be phased out in future to reduce special cases. 2568 */ 2569INT_DEFINE_BEGIN(denorm_exception) 2570 IVEC=0x1500 2571 IHSRR=1 2572 IBRANCH_TO_COMMON=0 2573 IKVM_REAL=1 2574INT_DEFINE_END(denorm_exception) 2575 2576EXC_REAL_BEGIN(denorm_exception, 0x1500, 0x100) 2577 GEN_INT_ENTRY denorm_exception, virt=0 2578#ifdef CONFIG_PPC_DENORMALISATION 2579 andis. r10,r12,(HSRR1_DENORM)@h /* denorm? */ 2580 bne+ denorm_assist 2581#endif 2582 GEN_BRANCH_TO_COMMON denorm_exception, virt=0 2583EXC_REAL_END(denorm_exception, 0x1500, 0x100) 2584#ifdef CONFIG_PPC_DENORMALISATION 2585EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100) 2586 GEN_INT_ENTRY denorm_exception, virt=1 2587 andis. r10,r12,(HSRR1_DENORM)@h /* denorm? */ 2588 bne+ denorm_assist 2589 GEN_BRANCH_TO_COMMON denorm_exception, virt=1 2590EXC_VIRT_END(denorm_exception, 0x5500, 0x100) 2591#else 2592EXC_VIRT_NONE(0x5500, 0x100) 2593#endif 2594 2595#ifdef CONFIG_PPC_DENORMALISATION 2596TRAMP_REAL_BEGIN(denorm_assist) 2597BEGIN_FTR_SECTION 2598/* 2599 * To denormalise we need to move a copy of the register to itself. 2600 * For POWER6 do that here for all FP regs. 2601 */ 2602 mfmsr r10 2603 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) 2604 xori r10,r10,(MSR_FE0|MSR_FE1) 2605 mtmsrd r10 2606 sync 2607 2608 .Lreg=0 2609 .rept 32 2610 fmr .Lreg,.Lreg 2611 .Lreg=.Lreg+1 2612 .endr 2613 2614FTR_SECTION_ELSE 2615/* 2616 * To denormalise we need to move a copy of the register to itself. 2617 * For POWER7 do that here for the first 32 VSX registers only. 2618 */ 2619 mfmsr r10 2620 oris r10,r10,MSR_VSX@h 2621 mtmsrd r10 2622 sync 2623 2624 .Lreg=0 2625 .rept 32 2626 XVCPSGNDP(.Lreg,.Lreg,.Lreg) 2627 .Lreg=.Lreg+1 2628 .endr 2629 2630ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) 2631 2632BEGIN_FTR_SECTION 2633 b denorm_done 2634END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) 2635/* 2636 * To denormalise we need to move a copy of the register to itself. 2637 * For POWER8 we need to do that for all 64 VSX registers 2638 */ 2639 .Lreg=32 2640 .rept 32 2641 XVCPSGNDP(.Lreg,.Lreg,.Lreg) 2642 .Lreg=.Lreg+1 2643 .endr 2644 2645denorm_done: 2646 mfspr r11,SPRN_HSRR0 2647 subi r11,r11,4 2648 mtspr SPRN_HSRR0,r11 2649 mtcrf 0x80,r9 2650 ld r9,PACA_EXGEN+EX_R9(r13) 2651BEGIN_FTR_SECTION 2652 ld r10,PACA_EXGEN+EX_PPR(r13) 2653 mtspr SPRN_PPR,r10 2654END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) 2655BEGIN_FTR_SECTION 2656 ld r10,PACA_EXGEN+EX_CFAR(r13) 2657 mtspr SPRN_CFAR,r10 2658END_FTR_SECTION_IFSET(CPU_FTR_CFAR) 2659 ld r10,PACA_EXGEN+EX_R10(r13) 2660 ld r11,PACA_EXGEN+EX_R11(r13) 2661 ld r12,PACA_EXGEN+EX_R12(r13) 2662 ld r13,PACA_EXGEN+EX_R13(r13) 2663 HRFI_TO_UNKNOWN 2664 b . 2665#endif 2666 2667EXC_COMMON_BEGIN(denorm_exception_common) 2668 GEN_COMMON denorm_exception 2669 addi r3,r1,STACK_FRAME_OVERHEAD 2670 bl unknown_exception 2671 b interrupt_return 2672 2673 GEN_KVM denorm_exception 2674 2675 2676#ifdef CONFIG_CBE_RAS 2677INT_DEFINE_BEGIN(cbe_maintenance) 2678 IVEC=0x1600 2679 IHSRR=1 2680INT_DEFINE_END(cbe_maintenance) 2681 2682EXC_REAL_BEGIN(cbe_maintenance, 0x1600, 0x100) 2683 GEN_INT_ENTRY cbe_maintenance, virt=0 2684EXC_REAL_END(cbe_maintenance, 0x1600, 0x100) 2685EXC_VIRT_NONE(0x5600, 0x100) 2686EXC_COMMON_BEGIN(cbe_maintenance_common) 2687 GEN_COMMON cbe_maintenance 2688 addi r3,r1,STACK_FRAME_OVERHEAD 2689 bl cbe_maintenance_exception 2690 b interrupt_return 2691 2692 GEN_KVM cbe_maintenance 2693 2694#else /* CONFIG_CBE_RAS */ 2695EXC_REAL_NONE(0x1600, 0x100) 2696EXC_VIRT_NONE(0x5600, 0x100) 2697#endif 2698 2699 2700INT_DEFINE_BEGIN(altivec_assist) 2701 IVEC=0x1700 2702#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 2703 IKVM_REAL=1 2704#endif 2705INT_DEFINE_END(altivec_assist) 2706 2707EXC_REAL_BEGIN(altivec_assist, 0x1700, 0x100) 2708 GEN_INT_ENTRY altivec_assist, virt=0 2709EXC_REAL_END(altivec_assist, 0x1700, 0x100) 2710EXC_VIRT_BEGIN(altivec_assist, 0x5700, 0x100) 2711 GEN_INT_ENTRY altivec_assist, virt=1 2712EXC_VIRT_END(altivec_assist, 0x5700, 0x100) 2713EXC_COMMON_BEGIN(altivec_assist_common) 2714 GEN_COMMON altivec_assist 2715 addi r3,r1,STACK_FRAME_OVERHEAD 2716#ifdef CONFIG_ALTIVEC 2717 bl altivec_assist_exception 2718 REST_NVGPRS(r1) /* instruction emulation may change GPRs */ 2719#else 2720 bl unknown_exception 2721#endif 2722 b interrupt_return 2723 2724 GEN_KVM altivec_assist 2725 2726 2727#ifdef CONFIG_CBE_RAS 2728INT_DEFINE_BEGIN(cbe_thermal) 2729 IVEC=0x1800 2730 IHSRR=1 2731INT_DEFINE_END(cbe_thermal) 2732 2733EXC_REAL_BEGIN(cbe_thermal, 0x1800, 0x100) 2734 GEN_INT_ENTRY cbe_thermal, virt=0 2735EXC_REAL_END(cbe_thermal, 0x1800, 0x100) 2736EXC_VIRT_NONE(0x5800, 0x100) 2737EXC_COMMON_BEGIN(cbe_thermal_common) 2738 GEN_COMMON cbe_thermal 2739 addi r3,r1,STACK_FRAME_OVERHEAD 2740 bl cbe_thermal_exception 2741 b interrupt_return 2742 2743 GEN_KVM cbe_thermal 2744 2745#else /* CONFIG_CBE_RAS */ 2746EXC_REAL_NONE(0x1800, 0x100) 2747EXC_VIRT_NONE(0x5800, 0x100) 2748#endif 2749 2750 2751#ifdef CONFIG_PPC_WATCHDOG 2752 2753INT_DEFINE_BEGIN(soft_nmi) 2754 IVEC=0x900 2755 ISTACK=0 2756INT_DEFINE_END(soft_nmi) 2757 2758/* 2759 * Branch to soft_nmi_interrupt using the emergency stack. The emergency 2760 * stack is one that is usable by maskable interrupts so long as MSR_EE 2761 * remains off. It is used for recovery when something has corrupted the 2762 * normal kernel stack, for example. The "soft NMI" must not use the process 2763 * stack because we want irq disabled sections to avoid touching the stack 2764 * at all (other than PMU interrupts), so use the emergency stack for this, 2765 * and run it entirely with interrupts hard disabled. 2766 */ 2767EXC_COMMON_BEGIN(soft_nmi_common) 2768 mfspr r11,SPRN_SRR0 2769 mr r10,r1 2770 ld r1,PACAEMERGSP(r13) 2771 subi r1,r1,INT_FRAME_SIZE 2772 __GEN_COMMON_BODY soft_nmi 2773 2774 addi r3,r1,STACK_FRAME_OVERHEAD 2775 bl soft_nmi_interrupt 2776 2777 /* Clear MSR_RI before setting SRR0 and SRR1. */ 2778 li r9,0 2779 mtmsrd r9,1 2780 2781 kuap_kernel_restore r9, r10 2782 EXCEPTION_RESTORE_REGS hsrr=0 2783 RFI_TO_KERNEL 2784 2785#endif /* CONFIG_PPC_WATCHDOG */ 2786 2787/* 2788 * An interrupt came in while soft-disabled. We set paca->irq_happened, then: 2789 * - If it was a decrementer interrupt, we bump the dec to max and and return. 2790 * - If it was a doorbell we return immediately since doorbells are edge 2791 * triggered and won't automatically refire. 2792 * - If it was a HMI we return immediately since we handled it in realmode 2793 * and it won't refire. 2794 * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return. 2795 * This is called with r10 containing the value to OR to the paca field. 2796 */ 2797.macro MASKED_INTERRUPT hsrr=0 2798 .if \hsrr 2799masked_Hinterrupt: 2800 .else 2801masked_interrupt: 2802 .endif 2803 lbz r11,PACAIRQHAPPENED(r13) 2804 or r11,r11,r10 2805 stb r11,PACAIRQHAPPENED(r13) 2806 cmpwi r10,PACA_IRQ_DEC 2807 bne 1f 2808 lis r10,0x7fff 2809 ori r10,r10,0xffff 2810 mtspr SPRN_DEC,r10 2811#ifdef CONFIG_PPC_WATCHDOG 2812 b soft_nmi_common 2813#else 2814 b 2f 2815#endif 28161: andi. r10,r10,PACA_IRQ_MUST_HARD_MASK 2817 beq 2f 2818 xori r12,r12,MSR_EE /* clear MSR_EE */ 2819 .if \hsrr 2820 mtspr SPRN_HSRR1,r12 2821 .else 2822 mtspr SPRN_SRR1,r12 2823 .endif 2824 ori r11,r11,PACA_IRQ_HARD_DIS 2825 stb r11,PACAIRQHAPPENED(r13) 28262: /* done */ 2827 ld r10,PACA_EXGEN+EX_CTR(r13) 2828 mtctr r10 2829 mtcrf 0x80,r9 2830 std r1,PACAR1(r13) 2831 ld r9,PACA_EXGEN+EX_R9(r13) 2832 ld r10,PACA_EXGEN+EX_R10(r13) 2833 ld r11,PACA_EXGEN+EX_R11(r13) 2834 ld r12,PACA_EXGEN+EX_R12(r13) 2835 ld r13,PACA_EXGEN+EX_R13(r13) 2836 /* May return to masked low address where r13 is not set up */ 2837 .if \hsrr 2838 HRFI_TO_KERNEL 2839 .else 2840 RFI_TO_KERNEL 2841 .endif 2842 b . 2843.endm 2844 2845TRAMP_REAL_BEGIN(stf_barrier_fallback) 2846 std r9,PACA_EXRFI+EX_R9(r13) 2847 std r10,PACA_EXRFI+EX_R10(r13) 2848 sync 2849 ld r9,PACA_EXRFI+EX_R9(r13) 2850 ld r10,PACA_EXRFI+EX_R10(r13) 2851 ori 31,31,0 2852 .rept 14 2853 b 1f 28541: 2855 .endr 2856 blr 2857 2858/* Clobbers r10, r11, ctr */ 2859.macro L1D_DISPLACEMENT_FLUSH 2860 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) 2861 ld r11,PACA_L1D_FLUSH_SIZE(r13) 2862 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ 2863 mtctr r11 2864 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ 2865 2866 /* order ld/st prior to dcbt stop all streams with flushing */ 2867 sync 2868 2869 /* 2870 * The load addresses are at staggered offsets within cachelines, 2871 * which suits some pipelines better (on others it should not 2872 * hurt). 2873 */ 28741: 2875 ld r11,(0x80 + 8)*0(r10) 2876 ld r11,(0x80 + 8)*1(r10) 2877 ld r11,(0x80 + 8)*2(r10) 2878 ld r11,(0x80 + 8)*3(r10) 2879 ld r11,(0x80 + 8)*4(r10) 2880 ld r11,(0x80 + 8)*5(r10) 2881 ld r11,(0x80 + 8)*6(r10) 2882 ld r11,(0x80 + 8)*7(r10) 2883 addi r10,r10,0x80*8 2884 bdnz 1b 2885.endm 2886 2887TRAMP_REAL_BEGIN(entry_flush_fallback) 2888 std r9,PACA_EXRFI+EX_R9(r13) 2889 std r10,PACA_EXRFI+EX_R10(r13) 2890 std r11,PACA_EXRFI+EX_R11(r13) 2891 mfctr r9 2892 L1D_DISPLACEMENT_FLUSH 2893 mtctr r9 2894 ld r9,PACA_EXRFI+EX_R9(r13) 2895 ld r10,PACA_EXRFI+EX_R10(r13) 2896 ld r11,PACA_EXRFI+EX_R11(r13) 2897 blr 2898 2899/* 2900 * The SCV entry flush happens with interrupts enabled, so it must disable 2901 * to prevent EXRFI being clobbered by NMIs (e.g., soft_nmi_common). r10 2902 * (containing LR) does not need to be preserved here because scv entry 2903 * puts 0 in the pt_regs, CTR can be clobbered for the same reason. 2904 */ 2905TRAMP_REAL_BEGIN(scv_entry_flush_fallback) 2906 li r10,0 2907 mtmsrd r10,1 2908 lbz r10,PACAIRQHAPPENED(r13) 2909 ori r10,r10,PACA_IRQ_HARD_DIS 2910 stb r10,PACAIRQHAPPENED(r13) 2911 std r11,PACA_EXRFI+EX_R11(r13) 2912 L1D_DISPLACEMENT_FLUSH 2913 ld r11,PACA_EXRFI+EX_R11(r13) 2914 li r10,MSR_RI 2915 mtmsrd r10,1 2916 blr 2917 2918TRAMP_REAL_BEGIN(rfi_flush_fallback) 2919 SET_SCRATCH0(r13); 2920 GET_PACA(r13); 2921 std r1,PACA_EXRFI+EX_R12(r13) 2922 ld r1,PACAKSAVE(r13) 2923 std r9,PACA_EXRFI+EX_R9(r13) 2924 std r10,PACA_EXRFI+EX_R10(r13) 2925 std r11,PACA_EXRFI+EX_R11(r13) 2926 mfctr r9 2927 L1D_DISPLACEMENT_FLUSH 2928 mtctr r9 2929 ld r9,PACA_EXRFI+EX_R9(r13) 2930 ld r10,PACA_EXRFI+EX_R10(r13) 2931 ld r11,PACA_EXRFI+EX_R11(r13) 2932 ld r1,PACA_EXRFI+EX_R12(r13) 2933 GET_SCRATCH0(r13); 2934 rfid 2935 2936TRAMP_REAL_BEGIN(hrfi_flush_fallback) 2937 SET_SCRATCH0(r13); 2938 GET_PACA(r13); 2939 std r1,PACA_EXRFI+EX_R12(r13) 2940 ld r1,PACAKSAVE(r13) 2941 std r9,PACA_EXRFI+EX_R9(r13) 2942 std r10,PACA_EXRFI+EX_R10(r13) 2943 std r11,PACA_EXRFI+EX_R11(r13) 2944 mfctr r9 2945 L1D_DISPLACEMENT_FLUSH 2946 mtctr r9 2947 ld r9,PACA_EXRFI+EX_R9(r13) 2948 ld r10,PACA_EXRFI+EX_R10(r13) 2949 ld r11,PACA_EXRFI+EX_R11(r13) 2950 ld r1,PACA_EXRFI+EX_R12(r13) 2951 GET_SCRATCH0(r13); 2952 hrfid 2953 2954TRAMP_REAL_BEGIN(rfscv_flush_fallback) 2955 /* system call volatile */ 2956 mr r7,r13 2957 GET_PACA(r13); 2958 mr r8,r1 2959 ld r1,PACAKSAVE(r13) 2960 mfctr r9 2961 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) 2962 ld r11,PACA_L1D_FLUSH_SIZE(r13) 2963 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ 2964 mtctr r11 2965 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ 2966 2967 /* order ld/st prior to dcbt stop all streams with flushing */ 2968 sync 2969 2970 /* 2971 * The load adresses are at staggered offsets within cachelines, 2972 * which suits some pipelines better (on others it should not 2973 * hurt). 2974 */ 29751: 2976 ld r11,(0x80 + 8)*0(r10) 2977 ld r11,(0x80 + 8)*1(r10) 2978 ld r11,(0x80 + 8)*2(r10) 2979 ld r11,(0x80 + 8)*3(r10) 2980 ld r11,(0x80 + 8)*4(r10) 2981 ld r11,(0x80 + 8)*5(r10) 2982 ld r11,(0x80 + 8)*6(r10) 2983 ld r11,(0x80 + 8)*7(r10) 2984 addi r10,r10,0x80*8 2985 bdnz 1b 2986 2987 mtctr r9 2988 li r9,0 2989 li r10,0 2990 li r11,0 2991 mr r1,r8 2992 mr r13,r7 2993 RFSCV 2994 2995USE_TEXT_SECTION() 2996 2997_GLOBAL(do_uaccess_flush) 2998 UACCESS_FLUSH_FIXUP_SECTION 2999 nop 3000 nop 3001 nop 3002 blr 3003 L1D_DISPLACEMENT_FLUSH 3004 blr 3005_ASM_NOKPROBE_SYMBOL(do_uaccess_flush) 3006EXPORT_SYMBOL(do_uaccess_flush) 3007 3008 3009MASKED_INTERRUPT 3010MASKED_INTERRUPT hsrr=1 3011 3012#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 3013kvmppc_skip_interrupt: 3014 /* 3015 * Here all GPRs are unchanged from when the interrupt happened 3016 * except for r13, which is saved in SPRG_SCRATCH0. 3017 */ 3018 mfspr r13, SPRN_SRR0 3019 addi r13, r13, 4 3020 mtspr SPRN_SRR0, r13 3021 GET_SCRATCH0(r13) 3022 RFI_TO_KERNEL 3023 b . 3024 3025kvmppc_skip_Hinterrupt: 3026 /* 3027 * Here all GPRs are unchanged from when the interrupt happened 3028 * except for r13, which is saved in SPRG_SCRATCH0. 3029 */ 3030 mfspr r13, SPRN_HSRR0 3031 addi r13, r13, 4 3032 mtspr SPRN_HSRR0, r13 3033 GET_SCRATCH0(r13) 3034 HRFI_TO_KERNEL 3035 b . 3036#endif 3037 3038 /* 3039 * Relocation-on interrupts: A subset of the interrupts can be delivered 3040 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering 3041 * it. Addresses are the same as the original interrupt addresses, but 3042 * offset by 0xc000000000004000. 3043 * It's impossible to receive interrupts below 0x300 via this mechanism. 3044 * KVM: None of these traps are from the guest ; anything that escalated 3045 * to HV=1 from HV=0 is delivered via real mode handlers. 3046 */ 3047 3048 /* 3049 * This uses the standard macro, since the original 0x300 vector 3050 * only has extra guff for STAB-based processors -- which never 3051 * come here. 3052 */ 3053 3054USE_FIXED_SECTION(virt_trampolines) 3055 /* 3056 * All code below __end_interrupts is treated as soft-masked. If 3057 * any code runs here with MSR[EE]=1, it must then cope with pending 3058 * soft interrupt being raised (i.e., by ensuring it is replayed). 3059 * 3060 * The __end_interrupts marker must be past the out-of-line (OOL) 3061 * handlers, so that they are copied to real address 0x100 when running 3062 * a relocatable kernel. This ensures they can be reached from the short 3063 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch 3064 * directly, without using LOAD_HANDLER(). 3065 */ 3066 .align 7 3067 .globl __end_interrupts 3068__end_interrupts: 3069DEFINE_FIXED_SYMBOL(__end_interrupts) 3070 3071CLOSE_FIXED_SECTION(real_vectors); 3072CLOSE_FIXED_SECTION(real_trampolines); 3073CLOSE_FIXED_SECTION(virt_vectors); 3074CLOSE_FIXED_SECTION(virt_trampolines); 3075 3076USE_TEXT_SECTION() 3077 3078/* MSR[RI] should be clear because this uses SRR[01] */ 3079enable_machine_check: 3080 mflr r0 3081 bcl 20,31,$+4 30820: mflr r3 3083 addi r3,r3,(1f - 0b) 3084 mtspr SPRN_SRR0,r3 3085 mfmsr r3 3086 ori r3,r3,MSR_ME 3087 mtspr SPRN_SRR1,r3 3088 RFI_TO_KERNEL 30891: mtlr r0 3090 blr 3091 3092/* MSR[RI] should be clear because this uses SRR[01] */ 3093disable_machine_check: 3094 mflr r0 3095 bcl 20,31,$+4 30960: mflr r3 3097 addi r3,r3,(1f - 0b) 3098 mtspr SPRN_SRR0,r3 3099 mfmsr r3 3100 li r4,MSR_ME 3101 andc r3,r3,r4 3102 mtspr SPRN_SRR1,r3 3103 RFI_TO_KERNEL 31041: mtlr r0 3105 blr 3106