1/* 2 * Boot code and exception vectors for Book3E processors 3 * 4 * Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12#include <linux/threads.h> 13#include <asm/reg.h> 14#include <asm/page.h> 15#include <asm/ppc_asm.h> 16#include <asm/asm-offsets.h> 17#include <asm/cputable.h> 18#include <asm/setup.h> 19#include <asm/thread_info.h> 20#include <asm/reg_a2.h> 21#include <asm/exception-64e.h> 22#include <asm/bug.h> 23#include <asm/irqflags.h> 24#include <asm/ptrace.h> 25#include <asm/ppc-opcode.h> 26#include <asm/mmu.h> 27#include <asm/hw_irq.h> 28#include <asm/kvm_asm.h> 29#include <asm/kvm_booke_hv_asm.h> 30#include <asm/feature-fixups.h> 31 32/* XXX This will ultimately add space for a special exception save 33 * structure used to save things like SRR0/SRR1, SPRGs, MAS, etc... 34 * when taking special interrupts. For now we don't support that, 35 * special interrupts from within a non-standard level will probably 36 * blow you up 37 */ 38#define SPECIAL_EXC_SRR0 0 39#define SPECIAL_EXC_SRR1 1 40#define SPECIAL_EXC_SPRG_GEN 2 41#define SPECIAL_EXC_SPRG_TLB 3 42#define SPECIAL_EXC_MAS0 4 43#define SPECIAL_EXC_MAS1 5 44#define SPECIAL_EXC_MAS2 6 45#define SPECIAL_EXC_MAS3 7 46#define SPECIAL_EXC_MAS6 8 47#define SPECIAL_EXC_MAS7 9 48#define SPECIAL_EXC_MAS5 10 /* E.HV only */ 49#define SPECIAL_EXC_MAS8 11 /* E.HV only */ 50#define SPECIAL_EXC_IRQHAPPENED 12 51#define SPECIAL_EXC_DEAR 13 52#define SPECIAL_EXC_ESR 14 53#define SPECIAL_EXC_SOFTE 15 54#define SPECIAL_EXC_CSRR0 16 55#define SPECIAL_EXC_CSRR1 17 56/* must be even to keep 16-byte stack alignment */ 57#define SPECIAL_EXC_END 18 58 59#define SPECIAL_EXC_FRAME_SIZE (INT_FRAME_SIZE + SPECIAL_EXC_END * 8) 60#define SPECIAL_EXC_FRAME_OFFS (INT_FRAME_SIZE - 288) 61 62#define SPECIAL_EXC_STORE(reg, name) \ 63 std reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1) 64 65#define SPECIAL_EXC_LOAD(reg, name) \ 66 ld reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1) 67 68special_reg_save: 69 lbz r9,PACAIRQHAPPENED(r13) 70 RECONCILE_IRQ_STATE(r3,r4) 71 72 /* 73 * We only need (or have stack space) to save this stuff if 74 * we interrupted the kernel. 75 */ 76 ld r3,_MSR(r1) 77 andi. r3,r3,MSR_PR 78 bnelr 79 80 /* Copy info into temporary exception thread info */ 81 ld r11,PACAKSAVE(r13) 82 CURRENT_THREAD_INFO(r11, r11) 83 CURRENT_THREAD_INFO(r12, r1) 84 ld r10,TI_FLAGS(r11) 85 std r10,TI_FLAGS(r12) 86 ld r10,TI_PREEMPT(r11) 87 std r10,TI_PREEMPT(r12) 88 ld r10,TI_TASK(r11) 89 std r10,TI_TASK(r12) 90 91 /* 92 * Advance to the next TLB exception frame for handler 93 * types that don't do it automatically. 94 */ 95 LOAD_REG_ADDR(r11,extlb_level_exc) 96 lwz r12,0(r11) 97 mfspr r10,SPRN_SPRG_TLB_EXFRAME 98 add r10,r10,r12 99 mtspr SPRN_SPRG_TLB_EXFRAME,r10 100 101 /* 102 * Save registers needed to allow nesting of certain exceptions 103 * (such as TLB misses) inside special exception levels 104 */ 105 mfspr r10,SPRN_SRR0 106 SPECIAL_EXC_STORE(r10,SRR0) 107 mfspr r10,SPRN_SRR1 108 SPECIAL_EXC_STORE(r10,SRR1) 109 mfspr r10,SPRN_SPRG_GEN_SCRATCH 110 SPECIAL_EXC_STORE(r10,SPRG_GEN) 111 mfspr r10,SPRN_SPRG_TLB_SCRATCH 112 SPECIAL_EXC_STORE(r10,SPRG_TLB) 113 mfspr r10,SPRN_MAS0 114 SPECIAL_EXC_STORE(r10,MAS0) 115 mfspr r10,SPRN_MAS1 116 SPECIAL_EXC_STORE(r10,MAS1) 117 mfspr r10,SPRN_MAS2 118 SPECIAL_EXC_STORE(r10,MAS2) 119 mfspr r10,SPRN_MAS3 120 SPECIAL_EXC_STORE(r10,MAS3) 121 mfspr r10,SPRN_MAS6 122 SPECIAL_EXC_STORE(r10,MAS6) 123 mfspr r10,SPRN_MAS7 124 SPECIAL_EXC_STORE(r10,MAS7) 125BEGIN_FTR_SECTION 126 mfspr r10,SPRN_MAS5 127 SPECIAL_EXC_STORE(r10,MAS5) 128 mfspr r10,SPRN_MAS8 129 SPECIAL_EXC_STORE(r10,MAS8) 130 131 /* MAS5/8 could have inappropriate values if we interrupted KVM code */ 132 li r10,0 133 mtspr SPRN_MAS5,r10 134 mtspr SPRN_MAS8,r10 135END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) 136 SPECIAL_EXC_STORE(r9,IRQHAPPENED) 137 138 mfspr r10,SPRN_DEAR 139 SPECIAL_EXC_STORE(r10,DEAR) 140 mfspr r10,SPRN_ESR 141 SPECIAL_EXC_STORE(r10,ESR) 142 143 lbz r10,PACAIRQSOFTMASK(r13) 144 SPECIAL_EXC_STORE(r10,SOFTE) 145 ld r10,_NIP(r1) 146 SPECIAL_EXC_STORE(r10,CSRR0) 147 ld r10,_MSR(r1) 148 SPECIAL_EXC_STORE(r10,CSRR1) 149 150 blr 151 152ret_from_level_except: 153 ld r3,_MSR(r1) 154 andi. r3,r3,MSR_PR 155 beq 1f 156 b ret_from_except 1571: 158 159 LOAD_REG_ADDR(r11,extlb_level_exc) 160 lwz r12,0(r11) 161 mfspr r10,SPRN_SPRG_TLB_EXFRAME 162 sub r10,r10,r12 163 mtspr SPRN_SPRG_TLB_EXFRAME,r10 164 165 /* 166 * It's possible that the special level exception interrupted a 167 * TLB miss handler, and inserted the same entry that the 168 * interrupted handler was about to insert. On CPUs without TLB 169 * write conditional, this can result in a duplicate TLB entry. 170 * Wipe all non-bolted entries to be safe. 171 * 172 * Note that this doesn't protect against any TLB misses 173 * we may take accessing the stack from here to the end of 174 * the special level exception. It's not clear how we can 175 * reasonably protect against that, but only CPUs with 176 * neither TLB write conditional nor bolted kernel memory 177 * are affected. Do any such CPUs even exist? 178 */ 179 PPC_TLBILX_ALL(0,R0) 180 181 REST_NVGPRS(r1) 182 183 SPECIAL_EXC_LOAD(r10,SRR0) 184 mtspr SPRN_SRR0,r10 185 SPECIAL_EXC_LOAD(r10,SRR1) 186 mtspr SPRN_SRR1,r10 187 SPECIAL_EXC_LOAD(r10,SPRG_GEN) 188 mtspr SPRN_SPRG_GEN_SCRATCH,r10 189 SPECIAL_EXC_LOAD(r10,SPRG_TLB) 190 mtspr SPRN_SPRG_TLB_SCRATCH,r10 191 SPECIAL_EXC_LOAD(r10,MAS0) 192 mtspr SPRN_MAS0,r10 193 SPECIAL_EXC_LOAD(r10,MAS1) 194 mtspr SPRN_MAS1,r10 195 SPECIAL_EXC_LOAD(r10,MAS2) 196 mtspr SPRN_MAS2,r10 197 SPECIAL_EXC_LOAD(r10,MAS3) 198 mtspr SPRN_MAS3,r10 199 SPECIAL_EXC_LOAD(r10,MAS6) 200 mtspr SPRN_MAS6,r10 201 SPECIAL_EXC_LOAD(r10,MAS7) 202 mtspr SPRN_MAS7,r10 203BEGIN_FTR_SECTION 204 SPECIAL_EXC_LOAD(r10,MAS5) 205 mtspr SPRN_MAS5,r10 206 SPECIAL_EXC_LOAD(r10,MAS8) 207 mtspr SPRN_MAS8,r10 208END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) 209 210 lbz r6,PACAIRQSOFTMASK(r13) 211 ld r5,SOFTE(r1) 212 213 /* Interrupts had better not already be enabled... */ 214 tweqi r6,IRQS_ENABLED 215 216 andi. r6,r5,IRQS_DISABLED 217 bne 1f 218 219 TRACE_ENABLE_INTS 220 stb r5,PACAIRQSOFTMASK(r13) 2211: 222 /* 223 * Restore PACAIRQHAPPENED rather than setting it based on 224 * the return MSR[EE], since we could have interrupted 225 * __check_irq_replay() or other inconsistent transitory 226 * states that must remain that way. 227 */ 228 SPECIAL_EXC_LOAD(r10,IRQHAPPENED) 229 stb r10,PACAIRQHAPPENED(r13) 230 231 SPECIAL_EXC_LOAD(r10,DEAR) 232 mtspr SPRN_DEAR,r10 233 SPECIAL_EXC_LOAD(r10,ESR) 234 mtspr SPRN_ESR,r10 235 236 stdcx. r0,0,r1 /* to clear the reservation */ 237 238 REST_4GPRS(2, r1) 239 REST_4GPRS(6, r1) 240 241 ld r10,_CTR(r1) 242 ld r11,_XER(r1) 243 mtctr r10 244 mtxer r11 245 246 blr 247 248.macro ret_from_level srr0 srr1 paca_ex scratch 249 bl ret_from_level_except 250 251 ld r10,_LINK(r1) 252 ld r11,_CCR(r1) 253 ld r0,GPR13(r1) 254 mtlr r10 255 mtcr r11 256 257 ld r10,GPR10(r1) 258 ld r11,GPR11(r1) 259 ld r12,GPR12(r1) 260 mtspr \scratch,r0 261 262 std r10,\paca_ex+EX_R10(r13); 263 std r11,\paca_ex+EX_R11(r13); 264 ld r10,_NIP(r1) 265 ld r11,_MSR(r1) 266 ld r0,GPR0(r1) 267 ld r1,GPR1(r1) 268 mtspr \srr0,r10 269 mtspr \srr1,r11 270 ld r10,\paca_ex+EX_R10(r13) 271 ld r11,\paca_ex+EX_R11(r13) 272 mfspr r13,\scratch 273.endm 274 275ret_from_crit_except: 276 ret_from_level SPRN_CSRR0 SPRN_CSRR1 PACA_EXCRIT SPRN_SPRG_CRIT_SCRATCH 277 rfci 278 279ret_from_mc_except: 280 ret_from_level SPRN_MCSRR0 SPRN_MCSRR1 PACA_EXMC SPRN_SPRG_MC_SCRATCH 281 rfmci 282 283/* Exception prolog code for all exceptions */ 284#define EXCEPTION_PROLOG(n, intnum, type, addition) \ 285 mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \ 286 mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \ 287 std r10,PACA_EX##type+EX_R10(r13); \ 288 std r11,PACA_EX##type+EX_R11(r13); \ 289 mfcr r10; /* save CR */ \ 290 mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \ 291 DO_KVM intnum,SPRN_##type##_SRR1; /* KVM hook */ \ 292 stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \ 293 addition; /* additional code for that exc. */ \ 294 std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \ 295 type##_SET_KSTACK; /* get special stack if necessary */\ 296 andi. r10,r11,MSR_PR; /* save stack pointer */ \ 297 beq 1f; /* branch around if supervisor */ \ 298 ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\ 2991: cmpdi cr1,r1,0; /* check if SP makes sense */ \ 300 bge- cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \ 301 mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */ 302 303/* Exception type-specific macros */ 304#define GEN_SET_KSTACK \ 305 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ 306#define SPRN_GEN_SRR0 SPRN_SRR0 307#define SPRN_GEN_SRR1 SPRN_SRR1 308 309#define GDBELL_SET_KSTACK GEN_SET_KSTACK 310#define SPRN_GDBELL_SRR0 SPRN_GSRR0 311#define SPRN_GDBELL_SRR1 SPRN_GSRR1 312 313#define CRIT_SET_KSTACK \ 314 ld r1,PACA_CRIT_STACK(r13); \ 315 subi r1,r1,SPECIAL_EXC_FRAME_SIZE 316#define SPRN_CRIT_SRR0 SPRN_CSRR0 317#define SPRN_CRIT_SRR1 SPRN_CSRR1 318 319#define DBG_SET_KSTACK \ 320 ld r1,PACA_DBG_STACK(r13); \ 321 subi r1,r1,SPECIAL_EXC_FRAME_SIZE 322#define SPRN_DBG_SRR0 SPRN_DSRR0 323#define SPRN_DBG_SRR1 SPRN_DSRR1 324 325#define MC_SET_KSTACK \ 326 ld r1,PACA_MC_STACK(r13); \ 327 subi r1,r1,SPECIAL_EXC_FRAME_SIZE 328#define SPRN_MC_SRR0 SPRN_MCSRR0 329#define SPRN_MC_SRR1 SPRN_MCSRR1 330 331#define NORMAL_EXCEPTION_PROLOG(n, intnum, addition) \ 332 EXCEPTION_PROLOG(n, intnum, GEN, addition##_GEN(n)) 333 334#define CRIT_EXCEPTION_PROLOG(n, intnum, addition) \ 335 EXCEPTION_PROLOG(n, intnum, CRIT, addition##_CRIT(n)) 336 337#define DBG_EXCEPTION_PROLOG(n, intnum, addition) \ 338 EXCEPTION_PROLOG(n, intnum, DBG, addition##_DBG(n)) 339 340#define MC_EXCEPTION_PROLOG(n, intnum, addition) \ 341 EXCEPTION_PROLOG(n, intnum, MC, addition##_MC(n)) 342 343#define GDBELL_EXCEPTION_PROLOG(n, intnum, addition) \ 344 EXCEPTION_PROLOG(n, intnum, GDBELL, addition##_GDBELL(n)) 345 346/* Variants of the "addition" argument for the prolog 347 */ 348#define PROLOG_ADDITION_NONE_GEN(n) 349#define PROLOG_ADDITION_NONE_GDBELL(n) 350#define PROLOG_ADDITION_NONE_CRIT(n) 351#define PROLOG_ADDITION_NONE_DBG(n) 352#define PROLOG_ADDITION_NONE_MC(n) 353 354#define PROLOG_ADDITION_MASKABLE_GEN(n) \ 355 lbz r10,PACAIRQSOFTMASK(r13); /* are irqs soft-masked? */ \ 356 andi. r10,r10,IRQS_DISABLED; /* yes -> go out of line */ \ 357 bne masked_interrupt_book3e_##n 358 359#define PROLOG_ADDITION_2REGS_GEN(n) \ 360 std r14,PACA_EXGEN+EX_R14(r13); \ 361 std r15,PACA_EXGEN+EX_R15(r13) 362 363#define PROLOG_ADDITION_1REG_GEN(n) \ 364 std r14,PACA_EXGEN+EX_R14(r13); 365 366#define PROLOG_ADDITION_2REGS_CRIT(n) \ 367 std r14,PACA_EXCRIT+EX_R14(r13); \ 368 std r15,PACA_EXCRIT+EX_R15(r13) 369 370#define PROLOG_ADDITION_2REGS_DBG(n) \ 371 std r14,PACA_EXDBG+EX_R14(r13); \ 372 std r15,PACA_EXDBG+EX_R15(r13) 373 374#define PROLOG_ADDITION_2REGS_MC(n) \ 375 std r14,PACA_EXMC+EX_R14(r13); \ 376 std r15,PACA_EXMC+EX_R15(r13) 377 378 379/* Core exception code for all exceptions except TLB misses. */ 380#define EXCEPTION_COMMON_LVL(n, scratch, excf) \ 381exc_##n##_common: \ 382 std r0,GPR0(r1); /* save r0 in stackframe */ \ 383 std r2,GPR2(r1); /* save r2 in stackframe */ \ 384 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 385 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 386 std r9,GPR9(r1); /* save r9 in stackframe */ \ 387 std r10,_NIP(r1); /* save SRR0 to stackframe */ \ 388 std r11,_MSR(r1); /* save SRR1 to stackframe */ \ 389 beq 2f; /* if from kernel mode */ \ 390 ACCOUNT_CPU_USER_ENTRY(r13,r10,r11);/* accounting (uses cr0+eq) */ \ 3912: ld r3,excf+EX_R10(r13); /* get back r10 */ \ 392 ld r4,excf+EX_R11(r13); /* get back r11 */ \ 393 mfspr r5,scratch; /* get back r13 */ \ 394 std r12,GPR12(r1); /* save r12 in stackframe */ \ 395 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 396 mflr r6; /* save LR in stackframe */ \ 397 mfctr r7; /* save CTR in stackframe */ \ 398 mfspr r8,SPRN_XER; /* save XER in stackframe */ \ 399 ld r9,excf+EX_R1(r13); /* load orig r1 back from PACA */ \ 400 lwz r10,excf+EX_CR(r13); /* load orig CR back from PACA */ \ 401 lbz r11,PACAIRQSOFTMASK(r13); /* get current IRQ softe */ \ 402 ld r12,exception_marker@toc(r2); \ 403 li r0,0; \ 404 std r3,GPR10(r1); /* save r10 to stackframe */ \ 405 std r4,GPR11(r1); /* save r11 to stackframe */ \ 406 std r5,GPR13(r1); /* save it to stackframe */ \ 407 std r6,_LINK(r1); \ 408 std r7,_CTR(r1); \ 409 std r8,_XER(r1); \ 410 li r3,(n)+1; /* indicate partial regs in trap */ \ 411 std r9,0(r1); /* store stack frame back link */ \ 412 std r10,_CCR(r1); /* store orig CR in stackframe */ \ 413 std r9,GPR1(r1); /* store stack frame back link */ \ 414 std r11,SOFTE(r1); /* and save it to stackframe */ \ 415 std r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \ 416 std r3,_TRAP(r1); /* set trap number */ \ 417 std r0,RESULT(r1); /* clear regs->result */ 418 419#define EXCEPTION_COMMON(n) \ 420 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_GEN_SCRATCH, PACA_EXGEN) 421#define EXCEPTION_COMMON_CRIT(n) \ 422 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_CRIT_SCRATCH, PACA_EXCRIT) 423#define EXCEPTION_COMMON_MC(n) \ 424 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_MC_SCRATCH, PACA_EXMC) 425#define EXCEPTION_COMMON_DBG(n) \ 426 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_DBG_SCRATCH, PACA_EXDBG) 427 428/* 429 * This is meant for exceptions that don't immediately hard-enable. We 430 * set a bit in paca->irq_happened to ensure that a subsequent call to 431 * arch_local_irq_restore() will properly hard-enable and avoid the 432 * fast-path, and then reconcile irq state. 433 */ 434#define INTS_DISABLE RECONCILE_IRQ_STATE(r3,r4) 435 436/* 437 * This is called by exceptions that don't use INTS_DISABLE (that did not 438 * touch irq indicators in the PACA). This will restore MSR:EE to it's 439 * previous value 440 * 441 * XXX In the long run, we may want to open-code it in order to separate the 442 * load from the wrtee, thus limiting the latency caused by the dependency 443 * but at this point, I'll favor code clarity until we have a near to final 444 * implementation 445 */ 446#define INTS_RESTORE_HARD \ 447 ld r11,_MSR(r1); \ 448 wrtee r11; 449 450/* XXX FIXME: Restore r14/r15 when necessary */ 451#define BAD_STACK_TRAMPOLINE(n) \ 452exc_##n##_bad_stack: \ 453 li r1,(n); /* get exception number */ \ 454 sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \ 455 b bad_stack_book3e; /* bad stack error */ 456 457/* WARNING: If you change the layout of this stub, make sure you check 458 * the debug exception handler which handles single stepping 459 * into exceptions from userspace, and the MM code in 460 * arch/powerpc/mm/tlb_nohash.c which patches the branch here 461 * and would need to be updated if that branch is moved 462 */ 463#define EXCEPTION_STUB(loc, label) \ 464 . = interrupt_base_book3e + loc; \ 465 nop; /* To make debug interrupts happy */ \ 466 b exc_##label##_book3e; 467 468#define ACK_NONE(r) 469#define ACK_DEC(r) \ 470 lis r,TSR_DIS@h; \ 471 mtspr SPRN_TSR,r 472#define ACK_FIT(r) \ 473 lis r,TSR_FIS@h; \ 474 mtspr SPRN_TSR,r 475 476/* Used by asynchronous interrupt that may happen in the idle loop. 477 * 478 * This check if the thread was in the idle loop, and if yes, returns 479 * to the caller rather than the PC. This is to avoid a race if 480 * interrupts happen before the wait instruction. 481 */ 482#define CHECK_NAPPING() \ 483 CURRENT_THREAD_INFO(r11, r1); \ 484 ld r10,TI_LOCAL_FLAGS(r11); \ 485 andi. r9,r10,_TLF_NAPPING; \ 486 beq+ 1f; \ 487 ld r8,_LINK(r1); \ 488 rlwinm r7,r10,0,~_TLF_NAPPING; \ 489 std r8,_NIP(r1); \ 490 std r7,TI_LOCAL_FLAGS(r11); \ 4911: 492 493 494#define MASKABLE_EXCEPTION(trapnum, intnum, label, hdlr, ack) \ 495 START_EXCEPTION(label); \ 496 NORMAL_EXCEPTION_PROLOG(trapnum, intnum, PROLOG_ADDITION_MASKABLE)\ 497 EXCEPTION_COMMON(trapnum) \ 498 INTS_DISABLE; \ 499 ack(r8); \ 500 CHECK_NAPPING(); \ 501 addi r3,r1,STACK_FRAME_OVERHEAD; \ 502 bl hdlr; \ 503 b ret_from_except_lite; 504 505/* This value is used to mark exception frames on the stack. */ 506 .section ".toc","aw" 507exception_marker: 508 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER 509 510 511/* 512 * And here we have the exception vectors ! 513 */ 514 515 .text 516 .balign 0x1000 517 .globl interrupt_base_book3e 518interrupt_base_book3e: /* fake trap */ 519 EXCEPTION_STUB(0x000, machine_check) 520 EXCEPTION_STUB(0x020, critical_input) /* 0x0100 */ 521 EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */ 522 EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */ 523 EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */ 524 EXCEPTION_STUB(0x0a0, external_input) /* 0x0500 */ 525 EXCEPTION_STUB(0x0c0, alignment) /* 0x0600 */ 526 EXCEPTION_STUB(0x0e0, program) /* 0x0700 */ 527 EXCEPTION_STUB(0x100, fp_unavailable) /* 0x0800 */ 528 EXCEPTION_STUB(0x120, system_call) /* 0x0c00 */ 529 EXCEPTION_STUB(0x140, ap_unavailable) /* 0x0f20 */ 530 EXCEPTION_STUB(0x160, decrementer) /* 0x0900 */ 531 EXCEPTION_STUB(0x180, fixed_interval) /* 0x0980 */ 532 EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */ 533 EXCEPTION_STUB(0x1c0, data_tlb_miss) 534 EXCEPTION_STUB(0x1e0, instruction_tlb_miss) 535 EXCEPTION_STUB(0x200, altivec_unavailable) 536 EXCEPTION_STUB(0x220, altivec_assist) 537 EXCEPTION_STUB(0x260, perfmon) 538 EXCEPTION_STUB(0x280, doorbell) 539 EXCEPTION_STUB(0x2a0, doorbell_crit) 540 EXCEPTION_STUB(0x2c0, guest_doorbell) 541 EXCEPTION_STUB(0x2e0, guest_doorbell_crit) 542 EXCEPTION_STUB(0x300, hypercall) 543 EXCEPTION_STUB(0x320, ehpriv) 544 EXCEPTION_STUB(0x340, lrat_error) 545 546 .globl __end_interrupts 547__end_interrupts: 548 549/* Critical Input Interrupt */ 550 START_EXCEPTION(critical_input); 551 CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL, 552 PROLOG_ADDITION_NONE) 553 EXCEPTION_COMMON_CRIT(0x100) 554 bl save_nvgprs 555 bl special_reg_save 556 CHECK_NAPPING(); 557 addi r3,r1,STACK_FRAME_OVERHEAD 558 bl unknown_exception 559 b ret_from_crit_except 560 561/* Machine Check Interrupt */ 562 START_EXCEPTION(machine_check); 563 MC_EXCEPTION_PROLOG(0x000, BOOKE_INTERRUPT_MACHINE_CHECK, 564 PROLOG_ADDITION_NONE) 565 EXCEPTION_COMMON_MC(0x000) 566 bl save_nvgprs 567 bl special_reg_save 568 CHECK_NAPPING(); 569 addi r3,r1,STACK_FRAME_OVERHEAD 570 bl machine_check_exception 571 b ret_from_mc_except 572 573/* Data Storage Interrupt */ 574 START_EXCEPTION(data_storage) 575 NORMAL_EXCEPTION_PROLOG(0x300, BOOKE_INTERRUPT_DATA_STORAGE, 576 PROLOG_ADDITION_2REGS) 577 mfspr r14,SPRN_DEAR 578 mfspr r15,SPRN_ESR 579 EXCEPTION_COMMON(0x300) 580 INTS_DISABLE 581 b storage_fault_common 582 583/* Instruction Storage Interrupt */ 584 START_EXCEPTION(instruction_storage); 585 NORMAL_EXCEPTION_PROLOG(0x400, BOOKE_INTERRUPT_INST_STORAGE, 586 PROLOG_ADDITION_2REGS) 587 li r15,0 588 mr r14,r10 589 EXCEPTION_COMMON(0x400) 590 INTS_DISABLE 591 b storage_fault_common 592 593/* External Input Interrupt */ 594 MASKABLE_EXCEPTION(0x500, BOOKE_INTERRUPT_EXTERNAL, 595 external_input, do_IRQ, ACK_NONE) 596 597/* Alignment */ 598 START_EXCEPTION(alignment); 599 NORMAL_EXCEPTION_PROLOG(0x600, BOOKE_INTERRUPT_ALIGNMENT, 600 PROLOG_ADDITION_2REGS) 601 mfspr r14,SPRN_DEAR 602 mfspr r15,SPRN_ESR 603 EXCEPTION_COMMON(0x600) 604 b alignment_more /* no room, go out of line */ 605 606/* Program Interrupt */ 607 START_EXCEPTION(program); 608 NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM, 609 PROLOG_ADDITION_1REG) 610 mfspr r14,SPRN_ESR 611 EXCEPTION_COMMON(0x700) 612 INTS_DISABLE 613 std r14,_DSISR(r1) 614 addi r3,r1,STACK_FRAME_OVERHEAD 615 ld r14,PACA_EXGEN+EX_R14(r13) 616 bl save_nvgprs 617 bl program_check_exception 618 b ret_from_except 619 620/* Floating Point Unavailable Interrupt */ 621 START_EXCEPTION(fp_unavailable); 622 NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL, 623 PROLOG_ADDITION_NONE) 624 /* we can probably do a shorter exception entry for that one... */ 625 EXCEPTION_COMMON(0x800) 626 ld r12,_MSR(r1) 627 andi. r0,r12,MSR_PR; 628 beq- 1f 629 bl load_up_fpu 630 b fast_exception_return 6311: INTS_DISABLE 632 bl save_nvgprs 633 addi r3,r1,STACK_FRAME_OVERHEAD 634 bl kernel_fp_unavailable_exception 635 b ret_from_except 636 637/* Altivec Unavailable Interrupt */ 638 START_EXCEPTION(altivec_unavailable); 639 NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_ALTIVEC_UNAVAIL, 640 PROLOG_ADDITION_NONE) 641 /* we can probably do a shorter exception entry for that one... */ 642 EXCEPTION_COMMON(0x200) 643#ifdef CONFIG_ALTIVEC 644BEGIN_FTR_SECTION 645 ld r12,_MSR(r1) 646 andi. r0,r12,MSR_PR; 647 beq- 1f 648 bl load_up_altivec 649 b fast_exception_return 6501: 651END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 652#endif 653 INTS_DISABLE 654 bl save_nvgprs 655 addi r3,r1,STACK_FRAME_OVERHEAD 656 bl altivec_unavailable_exception 657 b ret_from_except 658 659/* AltiVec Assist */ 660 START_EXCEPTION(altivec_assist); 661 NORMAL_EXCEPTION_PROLOG(0x220, 662 BOOKE_INTERRUPT_ALTIVEC_ASSIST, 663 PROLOG_ADDITION_NONE) 664 EXCEPTION_COMMON(0x220) 665 INTS_DISABLE 666 bl save_nvgprs 667 addi r3,r1,STACK_FRAME_OVERHEAD 668#ifdef CONFIG_ALTIVEC 669BEGIN_FTR_SECTION 670 bl altivec_assist_exception 671END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 672#else 673 bl unknown_exception 674#endif 675 b ret_from_except 676 677 678/* Decrementer Interrupt */ 679 MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER, 680 decrementer, timer_interrupt, ACK_DEC) 681 682/* Fixed Interval Timer Interrupt */ 683 MASKABLE_EXCEPTION(0x980, BOOKE_INTERRUPT_FIT, 684 fixed_interval, unknown_exception, ACK_FIT) 685 686/* Watchdog Timer Interrupt */ 687 START_EXCEPTION(watchdog); 688 CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG, 689 PROLOG_ADDITION_NONE) 690 EXCEPTION_COMMON_CRIT(0x9f0) 691 bl save_nvgprs 692 bl special_reg_save 693 CHECK_NAPPING(); 694 addi r3,r1,STACK_FRAME_OVERHEAD 695#ifdef CONFIG_BOOKE_WDT 696 bl WatchdogException 697#else 698 bl unknown_exception 699#endif 700 b ret_from_crit_except 701 702/* System Call Interrupt */ 703 START_EXCEPTION(system_call) 704 mr r9,r13 /* keep a copy of userland r13 */ 705 mfspr r11,SPRN_SRR0 /* get return address */ 706 mfspr r12,SPRN_SRR1 /* get previous MSR */ 707 mfspr r13,SPRN_SPRG_PACA /* get our PACA */ 708 b system_call_common 709 710/* Auxiliary Processor Unavailable Interrupt */ 711 START_EXCEPTION(ap_unavailable); 712 NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL, 713 PROLOG_ADDITION_NONE) 714 EXCEPTION_COMMON(0xf20) 715 INTS_DISABLE 716 bl save_nvgprs 717 addi r3,r1,STACK_FRAME_OVERHEAD 718 bl unknown_exception 719 b ret_from_except 720 721/* Debug exception as a critical interrupt*/ 722 START_EXCEPTION(debug_crit); 723 CRIT_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG, 724 PROLOG_ADDITION_2REGS) 725 726 /* 727 * If there is a single step or branch-taken exception in an 728 * exception entry sequence, it was probably meant to apply to 729 * the code where the exception occurred (since exception entry 730 * doesn't turn off DE automatically). We simulate the effect 731 * of turning off DE on entry to an exception handler by turning 732 * off DE in the CSRR1 value and clearing the debug status. 733 */ 734 735 mfspr r14,SPRN_DBSR /* check single-step/branch taken */ 736 andis. r15,r14,(DBSR_IC|DBSR_BT)@h 737 beq+ 1f 738 739#ifdef CONFIG_RELOCATABLE 740 ld r15,PACATOC(r13) 741 ld r14,interrupt_base_book3e@got(r15) 742 ld r15,__end_interrupts@got(r15) 743#else 744 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e) 745 LOAD_REG_IMMEDIATE(r15,__end_interrupts) 746#endif 747 cmpld cr0,r10,r14 748 cmpld cr1,r10,r15 749 blt+ cr0,1f 750 bge+ cr1,1f 751 752 /* here it looks like we got an inappropriate debug exception. */ 753 lis r14,(DBSR_IC|DBSR_BT)@h /* clear the event */ 754 rlwinm r11,r11,0,~MSR_DE /* clear DE in the CSRR1 value */ 755 mtspr SPRN_DBSR,r14 756 mtspr SPRN_CSRR1,r11 757 lwz r10,PACA_EXCRIT+EX_CR(r13) /* restore registers */ 758 ld r1,PACA_EXCRIT+EX_R1(r13) 759 ld r14,PACA_EXCRIT+EX_R14(r13) 760 ld r15,PACA_EXCRIT+EX_R15(r13) 761 mtcr r10 762 ld r10,PACA_EXCRIT+EX_R10(r13) /* restore registers */ 763 ld r11,PACA_EXCRIT+EX_R11(r13) 764 mfspr r13,SPRN_SPRG_CRIT_SCRATCH 765 rfci 766 767 /* Normal debug exception */ 768 /* XXX We only handle coming from userspace for now since we can't 769 * quite save properly an interrupted kernel state yet 770 */ 7711: andi. r14,r11,MSR_PR; /* check for userspace again */ 772 beq kernel_dbg_exc; /* if from kernel mode */ 773 774 /* Now we mash up things to make it look like we are coming on a 775 * normal exception 776 */ 777 mfspr r14,SPRN_DBSR 778 EXCEPTION_COMMON_CRIT(0xd00) 779 std r14,_DSISR(r1) 780 addi r3,r1,STACK_FRAME_OVERHEAD 781 mr r4,r14 782 ld r14,PACA_EXCRIT+EX_R14(r13) 783 ld r15,PACA_EXCRIT+EX_R15(r13) 784 bl save_nvgprs 785 bl DebugException 786 b ret_from_except 787 788kernel_dbg_exc: 789 b . /* NYI */ 790 791/* Debug exception as a debug interrupt*/ 792 START_EXCEPTION(debug_debug); 793 DBG_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG, 794 PROLOG_ADDITION_2REGS) 795 796 /* 797 * If there is a single step or branch-taken exception in an 798 * exception entry sequence, it was probably meant to apply to 799 * the code where the exception occurred (since exception entry 800 * doesn't turn off DE automatically). We simulate the effect 801 * of turning off DE on entry to an exception handler by turning 802 * off DE in the DSRR1 value and clearing the debug status. 803 */ 804 805 mfspr r14,SPRN_DBSR /* check single-step/branch taken */ 806 andis. r15,r14,(DBSR_IC|DBSR_BT)@h 807 beq+ 1f 808 809#ifdef CONFIG_RELOCATABLE 810 ld r15,PACATOC(r13) 811 ld r14,interrupt_base_book3e@got(r15) 812 ld r15,__end_interrupts@got(r15) 813#else 814 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e) 815 LOAD_REG_IMMEDIATE(r15,__end_interrupts) 816#endif 817 cmpld cr0,r10,r14 818 cmpld cr1,r10,r15 819 blt+ cr0,1f 820 bge+ cr1,1f 821 822 /* here it looks like we got an inappropriate debug exception. */ 823 lis r14,(DBSR_IC|DBSR_BT)@h /* clear the event */ 824 rlwinm r11,r11,0,~MSR_DE /* clear DE in the DSRR1 value */ 825 mtspr SPRN_DBSR,r14 826 mtspr SPRN_DSRR1,r11 827 lwz r10,PACA_EXDBG+EX_CR(r13) /* restore registers */ 828 ld r1,PACA_EXDBG+EX_R1(r13) 829 ld r14,PACA_EXDBG+EX_R14(r13) 830 ld r15,PACA_EXDBG+EX_R15(r13) 831 mtcr r10 832 ld r10,PACA_EXDBG+EX_R10(r13) /* restore registers */ 833 ld r11,PACA_EXDBG+EX_R11(r13) 834 mfspr r13,SPRN_SPRG_DBG_SCRATCH 835 rfdi 836 837 /* Normal debug exception */ 838 /* XXX We only handle coming from userspace for now since we can't 839 * quite save properly an interrupted kernel state yet 840 */ 8411: andi. r14,r11,MSR_PR; /* check for userspace again */ 842 beq kernel_dbg_exc; /* if from kernel mode */ 843 844 /* Now we mash up things to make it look like we are coming on a 845 * normal exception 846 */ 847 mfspr r14,SPRN_DBSR 848 EXCEPTION_COMMON_DBG(0xd08) 849 INTS_DISABLE 850 std r14,_DSISR(r1) 851 addi r3,r1,STACK_FRAME_OVERHEAD 852 mr r4,r14 853 ld r14,PACA_EXDBG+EX_R14(r13) 854 ld r15,PACA_EXDBG+EX_R15(r13) 855 bl save_nvgprs 856 bl DebugException 857 b ret_from_except 858 859 START_EXCEPTION(perfmon); 860 NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR, 861 PROLOG_ADDITION_NONE) 862 EXCEPTION_COMMON(0x260) 863 INTS_DISABLE 864 CHECK_NAPPING() 865 addi r3,r1,STACK_FRAME_OVERHEAD 866 bl performance_monitor_exception 867 b ret_from_except_lite 868 869/* Doorbell interrupt */ 870 MASKABLE_EXCEPTION(0x280, BOOKE_INTERRUPT_DOORBELL, 871 doorbell, doorbell_exception, ACK_NONE) 872 873/* Doorbell critical Interrupt */ 874 START_EXCEPTION(doorbell_crit); 875 CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL, 876 PROLOG_ADDITION_NONE) 877 EXCEPTION_COMMON_CRIT(0x2a0) 878 bl save_nvgprs 879 bl special_reg_save 880 CHECK_NAPPING(); 881 addi r3,r1,STACK_FRAME_OVERHEAD 882 bl unknown_exception 883 b ret_from_crit_except 884 885/* 886 * Guest doorbell interrupt 887 * This general exception use GSRRx save/restore registers 888 */ 889 START_EXCEPTION(guest_doorbell); 890 GDBELL_EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL, 891 PROLOG_ADDITION_NONE) 892 EXCEPTION_COMMON(0x2c0) 893 addi r3,r1,STACK_FRAME_OVERHEAD 894 bl save_nvgprs 895 INTS_RESTORE_HARD 896 bl unknown_exception 897 b ret_from_except 898 899/* Guest Doorbell critical Interrupt */ 900 START_EXCEPTION(guest_doorbell_crit); 901 CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT, 902 PROLOG_ADDITION_NONE) 903 EXCEPTION_COMMON_CRIT(0x2e0) 904 bl save_nvgprs 905 bl special_reg_save 906 CHECK_NAPPING(); 907 addi r3,r1,STACK_FRAME_OVERHEAD 908 bl unknown_exception 909 b ret_from_crit_except 910 911/* Hypervisor call */ 912 START_EXCEPTION(hypercall); 913 NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL, 914 PROLOG_ADDITION_NONE) 915 EXCEPTION_COMMON(0x310) 916 addi r3,r1,STACK_FRAME_OVERHEAD 917 bl save_nvgprs 918 INTS_RESTORE_HARD 919 bl unknown_exception 920 b ret_from_except 921 922/* Embedded Hypervisor priviledged */ 923 START_EXCEPTION(ehpriv); 924 NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV, 925 PROLOG_ADDITION_NONE) 926 EXCEPTION_COMMON(0x320) 927 addi r3,r1,STACK_FRAME_OVERHEAD 928 bl save_nvgprs 929 INTS_RESTORE_HARD 930 bl unknown_exception 931 b ret_from_except 932 933/* LRAT Error interrupt */ 934 START_EXCEPTION(lrat_error); 935 NORMAL_EXCEPTION_PROLOG(0x340, BOOKE_INTERRUPT_LRAT_ERROR, 936 PROLOG_ADDITION_NONE) 937 EXCEPTION_COMMON(0x340) 938 addi r3,r1,STACK_FRAME_OVERHEAD 939 bl save_nvgprs 940 INTS_RESTORE_HARD 941 bl unknown_exception 942 b ret_from_except 943 944/* 945 * An interrupt came in while soft-disabled; We mark paca->irq_happened 946 * accordingly and if the interrupt is level sensitive, we hard disable 947 * hard disable (full_mask) corresponds to PACA_IRQ_MUST_HARD_MASK, so 948 * keep these in synch. 949 */ 950 951.macro masked_interrupt_book3e paca_irq full_mask 952 lbz r10,PACAIRQHAPPENED(r13) 953 .if \full_mask == 1 954 ori r10,r10,\paca_irq | PACA_IRQ_HARD_DIS 955 .else 956 ori r10,r10,\paca_irq 957 .endif 958 stb r10,PACAIRQHAPPENED(r13) 959 960 .if \full_mask == 1 961 rldicl r10,r11,48,1 /* clear MSR_EE */ 962 rotldi r11,r10,16 963 mtspr SPRN_SRR1,r11 964 .endif 965 966 lwz r11,PACA_EXGEN+EX_CR(r13) 967 mtcr r11 968 ld r10,PACA_EXGEN+EX_R10(r13) 969 ld r11,PACA_EXGEN+EX_R11(r13) 970 mfspr r13,SPRN_SPRG_GEN_SCRATCH 971 rfi 972 b . 973.endm 974 975masked_interrupt_book3e_0x500: 976 // XXX When adding support for EPR, use PACA_IRQ_EE_EDGE 977 masked_interrupt_book3e PACA_IRQ_EE 1 978 979masked_interrupt_book3e_0x900: 980 ACK_DEC(r10); 981 masked_interrupt_book3e PACA_IRQ_DEC 0 982 983masked_interrupt_book3e_0x980: 984 ACK_FIT(r10); 985 masked_interrupt_book3e PACA_IRQ_DEC 0 986 987masked_interrupt_book3e_0x280: 988masked_interrupt_book3e_0x2c0: 989 masked_interrupt_book3e PACA_IRQ_DBELL 0 990 991/* 992 * Called from arch_local_irq_enable when an interrupt needs 993 * to be resent. r3 contains either 0x500,0x900,0x260 or 0x280 994 * to indicate the kind of interrupt. MSR:EE is already off. 995 * We generate a stackframe like if a real interrupt had happened. 996 * 997 * Note: While MSR:EE is off, we need to make sure that _MSR 998 * in the generated frame has EE set to 1 or the exception 999 * handler will not properly re-enable them. 1000 */ 1001_GLOBAL(__replay_interrupt) 1002 /* We are going to jump to the exception common code which 1003 * will retrieve various register values from the PACA which 1004 * we don't give a damn about. 1005 */ 1006 mflr r10 1007 mfmsr r11 1008 mfcr r4 1009 mtspr SPRN_SPRG_GEN_SCRATCH,r13; 1010 std r1,PACA_EXGEN+EX_R1(r13); 1011 stw r4,PACA_EXGEN+EX_CR(r13); 1012 ori r11,r11,MSR_EE 1013 subi r1,r1,INT_FRAME_SIZE; 1014 cmpwi cr0,r3,0x500 1015 beq exc_0x500_common 1016 cmpwi cr0,r3,0x900 1017 beq exc_0x900_common 1018 cmpwi cr0,r3,0x280 1019 beq exc_0x280_common 1020 blr 1021 1022 1023/* 1024 * This is called from 0x300 and 0x400 handlers after the prologs with 1025 * r14 and r15 containing the fault address and error code, with the 1026 * original values stashed away in the PACA 1027 */ 1028storage_fault_common: 1029 std r14,_DAR(r1) 1030 std r15,_DSISR(r1) 1031 addi r3,r1,STACK_FRAME_OVERHEAD 1032 mr r4,r14 1033 mr r5,r15 1034 ld r14,PACA_EXGEN+EX_R14(r13) 1035 ld r15,PACA_EXGEN+EX_R15(r13) 1036 bl do_page_fault 1037 cmpdi r3,0 1038 bne- 1f 1039 b ret_from_except_lite 10401: bl save_nvgprs 1041 mr r5,r3 1042 addi r3,r1,STACK_FRAME_OVERHEAD 1043 ld r4,_DAR(r1) 1044 bl bad_page_fault 1045 b ret_from_except 1046 1047/* 1048 * Alignment exception doesn't fit entirely in the 0x100 bytes so it 1049 * continues here. 1050 */ 1051alignment_more: 1052 std r14,_DAR(r1) 1053 std r15,_DSISR(r1) 1054 addi r3,r1,STACK_FRAME_OVERHEAD 1055 ld r14,PACA_EXGEN+EX_R14(r13) 1056 ld r15,PACA_EXGEN+EX_R15(r13) 1057 bl save_nvgprs 1058 INTS_RESTORE_HARD 1059 bl alignment_exception 1060 b ret_from_except 1061 1062/* 1063 * We branch here from entry_64.S for the last stage of the exception 1064 * return code path. MSR:EE is expected to be off at that point 1065 */ 1066_GLOBAL(exception_return_book3e) 1067 b 1f 1068 1069/* This is the return from load_up_fpu fast path which could do with 1070 * less GPR restores in fact, but for now we have a single return path 1071 */ 1072 .globl fast_exception_return 1073fast_exception_return: 1074 wrteei 0 10751: mr r0,r13 1076 ld r10,_MSR(r1) 1077 REST_4GPRS(2, r1) 1078 andi. r6,r10,MSR_PR 1079 REST_2GPRS(6, r1) 1080 beq 1f 1081 ACCOUNT_CPU_USER_EXIT(r13, r10, r11) 1082 ld r0,GPR13(r1) 1083 10841: stdcx. r0,0,r1 /* to clear the reservation */ 1085 1086 ld r8,_CCR(r1) 1087 ld r9,_LINK(r1) 1088 ld r10,_CTR(r1) 1089 ld r11,_XER(r1) 1090 mtcr r8 1091 mtlr r9 1092 mtctr r10 1093 mtxer r11 1094 REST_2GPRS(8, r1) 1095 ld r10,GPR10(r1) 1096 ld r11,GPR11(r1) 1097 ld r12,GPR12(r1) 1098 mtspr SPRN_SPRG_GEN_SCRATCH,r0 1099 1100 std r10,PACA_EXGEN+EX_R10(r13); 1101 std r11,PACA_EXGEN+EX_R11(r13); 1102 ld r10,_NIP(r1) 1103 ld r11,_MSR(r1) 1104 ld r0,GPR0(r1) 1105 ld r1,GPR1(r1) 1106 mtspr SPRN_SRR0,r10 1107 mtspr SPRN_SRR1,r11 1108 ld r10,PACA_EXGEN+EX_R10(r13) 1109 ld r11,PACA_EXGEN+EX_R11(r13) 1110 mfspr r13,SPRN_SPRG_GEN_SCRATCH 1111 rfi 1112 1113/* 1114 * Trampolines used when spotting a bad kernel stack pointer in 1115 * the exception entry code. 1116 * 1117 * TODO: move some bits like SRR0 read to trampoline, pass PACA 1118 * index around, etc... to handle crit & mcheck 1119 */ 1120BAD_STACK_TRAMPOLINE(0x000) 1121BAD_STACK_TRAMPOLINE(0x100) 1122BAD_STACK_TRAMPOLINE(0x200) 1123BAD_STACK_TRAMPOLINE(0x220) 1124BAD_STACK_TRAMPOLINE(0x260) 1125BAD_STACK_TRAMPOLINE(0x280) 1126BAD_STACK_TRAMPOLINE(0x2a0) 1127BAD_STACK_TRAMPOLINE(0x2c0) 1128BAD_STACK_TRAMPOLINE(0x2e0) 1129BAD_STACK_TRAMPOLINE(0x300) 1130BAD_STACK_TRAMPOLINE(0x310) 1131BAD_STACK_TRAMPOLINE(0x320) 1132BAD_STACK_TRAMPOLINE(0x340) 1133BAD_STACK_TRAMPOLINE(0x400) 1134BAD_STACK_TRAMPOLINE(0x500) 1135BAD_STACK_TRAMPOLINE(0x600) 1136BAD_STACK_TRAMPOLINE(0x700) 1137BAD_STACK_TRAMPOLINE(0x800) 1138BAD_STACK_TRAMPOLINE(0x900) 1139BAD_STACK_TRAMPOLINE(0x980) 1140BAD_STACK_TRAMPOLINE(0x9f0) 1141BAD_STACK_TRAMPOLINE(0xa00) 1142BAD_STACK_TRAMPOLINE(0xb00) 1143BAD_STACK_TRAMPOLINE(0xc00) 1144BAD_STACK_TRAMPOLINE(0xd00) 1145BAD_STACK_TRAMPOLINE(0xd08) 1146BAD_STACK_TRAMPOLINE(0xe00) 1147BAD_STACK_TRAMPOLINE(0xf00) 1148BAD_STACK_TRAMPOLINE(0xf20) 1149 1150 .globl bad_stack_book3e 1151bad_stack_book3e: 1152 /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */ 1153 mfspr r10,SPRN_SRR0; /* read SRR0 before touching stack */ 1154 ld r1,PACAEMERGSP(r13) 1155 subi r1,r1,64+INT_FRAME_SIZE 1156 std r10,_NIP(r1) 1157 std r11,_MSR(r1) 1158 ld r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */ 1159 lwz r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */ 1160 std r10,GPR1(r1) 1161 std r11,_CCR(r1) 1162 mfspr r10,SPRN_DEAR 1163 mfspr r11,SPRN_ESR 1164 std r10,_DAR(r1) 1165 std r11,_DSISR(r1) 1166 std r0,GPR0(r1); /* save r0 in stackframe */ \ 1167 std r2,GPR2(r1); /* save r2 in stackframe */ \ 1168 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 1169 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 1170 std r9,GPR9(r1); /* save r9 in stackframe */ \ 1171 ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \ 1172 ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \ 1173 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \ 1174 std r3,GPR10(r1); /* save r10 to stackframe */ \ 1175 std r4,GPR11(r1); /* save r11 to stackframe */ \ 1176 std r12,GPR12(r1); /* save r12 in stackframe */ \ 1177 std r5,GPR13(r1); /* save it to stackframe */ \ 1178 mflr r10 1179 mfctr r11 1180 mfxer r12 1181 std r10,_LINK(r1) 1182 std r11,_CTR(r1) 1183 std r12,_XER(r1) 1184 SAVE_10GPRS(14,r1) 1185 SAVE_8GPRS(24,r1) 1186 lhz r12,PACA_TRAP_SAVE(r13) 1187 std r12,_TRAP(r1) 1188 addi r11,r1,INT_FRAME_SIZE 1189 std r11,0(r1) 1190 li r12,0 1191 std r12,0(r11) 1192 ld r2,PACATOC(r13) 11931: addi r3,r1,STACK_FRAME_OVERHEAD 1194 bl kernel_bad_stack 1195 b 1b 1196 1197/* 1198 * Setup the initial TLB for a core. This current implementation 1199 * assume that whatever we are running off will not conflict with 1200 * the new mapping at PAGE_OFFSET. 1201 */ 1202_GLOBAL(initial_tlb_book3e) 1203 1204 /* Look for the first TLB with IPROT set */ 1205 mfspr r4,SPRN_TLB0CFG 1206 andi. r3,r4,TLBnCFG_IPROT 1207 lis r3,MAS0_TLBSEL(0)@h 1208 bne found_iprot 1209 1210 mfspr r4,SPRN_TLB1CFG 1211 andi. r3,r4,TLBnCFG_IPROT 1212 lis r3,MAS0_TLBSEL(1)@h 1213 bne found_iprot 1214 1215 mfspr r4,SPRN_TLB2CFG 1216 andi. r3,r4,TLBnCFG_IPROT 1217 lis r3,MAS0_TLBSEL(2)@h 1218 bne found_iprot 1219 1220 lis r3,MAS0_TLBSEL(3)@h 1221 mfspr r4,SPRN_TLB3CFG 1222 /* fall through */ 1223 1224found_iprot: 1225 andi. r5,r4,TLBnCFG_HES 1226 bne have_hes 1227 1228 mflr r8 /* save LR */ 1229/* 1. Find the index of the entry we're executing in 1230 * 1231 * r3 = MAS0_TLBSEL (for the iprot array) 1232 * r4 = SPRN_TLBnCFG 1233 */ 1234 bl invstr /* Find our address */ 1235invstr: mflr r6 /* Make it accessible */ 1236 mfmsr r7 1237 rlwinm r5,r7,27,31,31 /* extract MSR[IS] */ 1238 mfspr r7,SPRN_PID 1239 slwi r7,r7,16 1240 or r7,r7,r5 1241 mtspr SPRN_MAS6,r7 1242 tlbsx 0,r6 /* search MSR[IS], SPID=PID */ 1243 1244 mfspr r3,SPRN_MAS0 1245 rlwinm r5,r3,16,20,31 /* Extract MAS0(Entry) */ 1246 1247 mfspr r7,SPRN_MAS1 /* Insure IPROT set */ 1248 oris r7,r7,MAS1_IPROT@h 1249 mtspr SPRN_MAS1,r7 1250 tlbwe 1251 1252/* 2. Invalidate all entries except the entry we're executing in 1253 * 1254 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in 1255 * r4 = SPRN_TLBnCFG 1256 * r5 = ESEL of entry we are running in 1257 */ 1258 andi. r4,r4,TLBnCFG_N_ENTRY /* Extract # entries */ 1259 li r6,0 /* Set Entry counter to 0 */ 12601: mr r7,r3 /* Set MAS0(TLBSEL) */ 1261 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */ 1262 mtspr SPRN_MAS0,r7 1263 tlbre 1264 mfspr r7,SPRN_MAS1 1265 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */ 1266 cmpw r5,r6 1267 beq skpinv /* Dont update the current execution TLB */ 1268 mtspr SPRN_MAS1,r7 1269 tlbwe 1270 isync 1271skpinv: addi r6,r6,1 /* Increment */ 1272 cmpw r6,r4 /* Are we done? */ 1273 bne 1b /* If not, repeat */ 1274 1275 /* Invalidate all TLBs */ 1276 PPC_TLBILX_ALL(0,R0) 1277 sync 1278 isync 1279 1280/* 3. Setup a temp mapping and jump to it 1281 * 1282 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in 1283 * r5 = ESEL of entry we are running in 1284 */ 1285 andi. r7,r5,0x1 /* Find an entry not used and is non-zero */ 1286 addi r7,r7,0x1 1287 mr r4,r3 /* Set MAS0(TLBSEL) = 1 */ 1288 mtspr SPRN_MAS0,r4 1289 tlbre 1290 1291 rlwimi r4,r7,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r7) */ 1292 mtspr SPRN_MAS0,r4 1293 1294 mfspr r7,SPRN_MAS1 1295 xori r6,r7,MAS1_TS /* Setup TMP mapping in the other Address space */ 1296 mtspr SPRN_MAS1,r6 1297 1298 tlbwe 1299 1300 mfmsr r6 1301 xori r6,r6,MSR_IS 1302 mtspr SPRN_SRR1,r6 1303 bl 1f /* Find our address */ 13041: mflr r6 1305 addi r6,r6,(2f - 1b) 1306 mtspr SPRN_SRR0,r6 1307 rfi 13082: 1309 1310/* 4. Clear out PIDs & Search info 1311 * 1312 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in 1313 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 1314 * r5 = MAS3 1315 */ 1316 li r6,0 1317 mtspr SPRN_MAS6,r6 1318 mtspr SPRN_PID,r6 1319 1320/* 5. Invalidate mapping we started in 1321 * 1322 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in 1323 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 1324 * r5 = MAS3 1325 */ 1326 mtspr SPRN_MAS0,r3 1327 tlbre 1328 mfspr r6,SPRN_MAS1 1329 rlwinm r6,r6,0,2,31 /* clear IPROT and VALID */ 1330 mtspr SPRN_MAS1,r6 1331 tlbwe 1332 sync 1333 isync 1334 1335/* 1336 * The mapping only needs to be cache-coherent on SMP, except on 1337 * Freescale e500mc derivatives where it's also needed for coherent DMA. 1338 */ 1339#if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC) 1340#define M_IF_NEEDED MAS2_M 1341#else 1342#define M_IF_NEEDED 0 1343#endif 1344 1345/* 6. Setup KERNELBASE mapping in TLB[0] 1346 * 1347 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in 1348 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 1349 * r5 = MAS3 1350 */ 1351 rlwinm r3,r3,0,16,3 /* clear ESEL */ 1352 mtspr SPRN_MAS0,r3 1353 lis r6,(MAS1_VALID|MAS1_IPROT)@h 1354 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l 1355 mtspr SPRN_MAS1,r6 1356 1357 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_NEEDED) 1358 mtspr SPRN_MAS2,r6 1359 1360 rlwinm r5,r5,0,0,25 1361 ori r5,r5,MAS3_SR | MAS3_SW | MAS3_SX 1362 mtspr SPRN_MAS3,r5 1363 li r5,-1 1364 rlwinm r5,r5,0,0,25 1365 1366 tlbwe 1367 1368/* 7. Jump to KERNELBASE mapping 1369 * 1370 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 1371 */ 1372 /* Now we branch the new virtual address mapped by this entry */ 1373 bl 1f /* Find our address */ 13741: mflr r6 1375 addi r6,r6,(2f - 1b) 1376 tovirt(r6,r6) 1377 lis r7,MSR_KERNEL@h 1378 ori r7,r7,MSR_KERNEL@l 1379 mtspr SPRN_SRR0,r6 1380 mtspr SPRN_SRR1,r7 1381 rfi /* start execution out of TLB1[0] entry */ 13822: 1383 1384/* 8. Clear out the temp mapping 1385 * 1386 * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in 1387 */ 1388 mtspr SPRN_MAS0,r4 1389 tlbre 1390 mfspr r5,SPRN_MAS1 1391 rlwinm r5,r5,0,2,31 /* clear IPROT and VALID */ 1392 mtspr SPRN_MAS1,r5 1393 tlbwe 1394 sync 1395 isync 1396 1397 /* We translate LR and return */ 1398 tovirt(r8,r8) 1399 mtlr r8 1400 blr 1401 1402have_hes: 1403 /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the 1404 * kernel linear mapping. We also set MAS8 once for all here though 1405 * that will have to be made dependent on whether we are running under 1406 * a hypervisor I suppose. 1407 */ 1408 1409 /* BEWARE, MAGIC 1410 * This code is called as an ordinary function on the boot CPU. But to 1411 * avoid duplication, this code is also used in SCOM bringup of 1412 * secondary CPUs. We read the code between the initial_tlb_code_start 1413 * and initial_tlb_code_end labels one instruction at a time and RAM it 1414 * into the new core via SCOM. That doesn't process branches, so there 1415 * must be none between those two labels. It also means if this code 1416 * ever takes any parameters, the SCOM code must also be updated to 1417 * provide them. 1418 */ 1419 .globl a2_tlbinit_code_start 1420a2_tlbinit_code_start: 1421 1422 ori r11,r3,MAS0_WQ_ALLWAYS 1423 oris r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */ 1424 mtspr SPRN_MAS0,r11 1425 lis r3,(MAS1_VALID | MAS1_IPROT)@h 1426 ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT 1427 mtspr SPRN_MAS1,r3 1428 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M) 1429 mtspr SPRN_MAS2,r3 1430 li r3,MAS3_SR | MAS3_SW | MAS3_SX 1431 mtspr SPRN_MAS7_MAS3,r3 1432 li r3,0 1433 mtspr SPRN_MAS8,r3 1434 1435 /* Write the TLB entry */ 1436 tlbwe 1437 1438 .globl a2_tlbinit_after_linear_map 1439a2_tlbinit_after_linear_map: 1440 1441 /* Now we branch the new virtual address mapped by this entry */ 1442 LOAD_REG_IMMEDIATE(r3,1f) 1443 mtctr r3 1444 bctr 1445 14461: /* We are now running at PAGE_OFFSET, clean the TLB of everything 1447 * else (including IPROTed things left by firmware) 1448 * r4 = TLBnCFG 1449 * r3 = current address (more or less) 1450 */ 1451 1452 li r5,0 1453 mtspr SPRN_MAS6,r5 1454 tlbsx 0,r3 1455 1456 rlwinm r9,r4,0,TLBnCFG_N_ENTRY 1457 rlwinm r10,r4,8,0xff 1458 addi r10,r10,-1 /* Get inner loop mask */ 1459 1460 li r3,1 1461 1462 mfspr r5,SPRN_MAS1 1463 rlwinm r5,r5,0,(~(MAS1_VALID|MAS1_IPROT)) 1464 1465 mfspr r6,SPRN_MAS2 1466 rldicr r6,r6,0,51 /* Extract EPN */ 1467 1468 mfspr r7,SPRN_MAS0 1469 rlwinm r7,r7,0,0xffff0fff /* Clear HES and WQ */ 1470 1471 rlwinm r8,r7,16,0xfff /* Extract ESEL */ 1472 14732: add r4,r3,r8 1474 and r4,r4,r10 1475 1476 rlwimi r7,r4,16,MAS0_ESEL_MASK 1477 1478 mtspr SPRN_MAS0,r7 1479 mtspr SPRN_MAS1,r5 1480 mtspr SPRN_MAS2,r6 1481 tlbwe 1482 1483 addi r3,r3,1 1484 and. r4,r3,r10 1485 1486 bne 3f 1487 addis r6,r6,(1<<30)@h 14883: 1489 cmpw r3,r9 1490 blt 2b 1491 1492 .globl a2_tlbinit_after_iprot_flush 1493a2_tlbinit_after_iprot_flush: 1494 1495 PPC_TLBILX(0,0,R0) 1496 sync 1497 isync 1498 1499 .globl a2_tlbinit_code_end 1500a2_tlbinit_code_end: 1501 1502 /* We translate LR and return */ 1503 mflr r3 1504 tovirt(r3,r3) 1505 mtlr r3 1506 blr 1507 1508/* 1509 * Main entry (boot CPU, thread 0) 1510 * 1511 * We enter here from head_64.S, possibly after the prom_init trampoline 1512 * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits 1513 * mode. Anything else is as it was left by the bootloader 1514 * 1515 * Initial requirements of this port: 1516 * 1517 * - Kernel loaded at 0 physical 1518 * - A good lump of memory mapped 0:0 by UTLB entry 0 1519 * - MSR:IS & MSR:DS set to 0 1520 * 1521 * Note that some of the above requirements will be relaxed in the future 1522 * as the kernel becomes smarter at dealing with different initial conditions 1523 * but for now you have to be careful 1524 */ 1525_GLOBAL(start_initialization_book3e) 1526 mflr r28 1527 1528 /* First, we need to setup some initial TLBs to map the kernel 1529 * text, data and bss at PAGE_OFFSET. We don't have a real mode 1530 * and always use AS 0, so we just set it up to match our link 1531 * address and never use 0 based addresses. 1532 */ 1533 bl initial_tlb_book3e 1534 1535 /* Init global core bits */ 1536 bl init_core_book3e 1537 1538 /* Init per-thread bits */ 1539 bl init_thread_book3e 1540 1541 /* Return to common init code */ 1542 tovirt(r28,r28) 1543 mtlr r28 1544 blr 1545 1546 1547/* 1548 * Secondary core/processor entry 1549 * 1550 * This is entered for thread 0 of a secondary core, all other threads 1551 * are expected to be stopped. It's similar to start_initialization_book3e 1552 * except that it's generally entered from the holding loop in head_64.S 1553 * after CPUs have been gathered by Open Firmware. 1554 * 1555 * We assume we are in 32 bits mode running with whatever TLB entry was 1556 * set for us by the firmware or POR engine. 1557 */ 1558_GLOBAL(book3e_secondary_core_init_tlb_set) 1559 li r4,1 1560 b generic_secondary_smp_init 1561 1562_GLOBAL(book3e_secondary_core_init) 1563 mflr r28 1564 1565 /* Do we need to setup initial TLB entry ? */ 1566 cmplwi r4,0 1567 bne 2f 1568 1569 /* Setup TLB for this core */ 1570 bl initial_tlb_book3e 1571 1572 /* We can return from the above running at a different 1573 * address, so recalculate r2 (TOC) 1574 */ 1575 bl relative_toc 1576 1577 /* Init global core bits */ 15782: bl init_core_book3e 1579 1580 /* Init per-thread bits */ 15813: bl init_thread_book3e 1582 1583 /* Return to common init code at proper virtual address. 1584 * 1585 * Due to various previous assumptions, we know we entered this 1586 * function at either the final PAGE_OFFSET mapping or using a 1587 * 1:1 mapping at 0, so we don't bother doing a complicated check 1588 * here, we just ensure the return address has the right top bits. 1589 * 1590 * Note that if we ever want to be smarter about where we can be 1591 * started from, we have to be careful that by the time we reach 1592 * the code below we may already be running at a different location 1593 * than the one we were called from since initial_tlb_book3e can 1594 * have moved us already. 1595 */ 1596 cmpdi cr0,r28,0 1597 blt 1f 1598 lis r3,PAGE_OFFSET@highest 1599 sldi r3,r3,32 1600 or r28,r28,r3 16011: mtlr r28 1602 blr 1603 1604_GLOBAL(book3e_secondary_thread_init) 1605 mflr r28 1606 b 3b 1607 1608 .globl init_core_book3e 1609init_core_book3e: 1610 /* Establish the interrupt vector base */ 1611 tovirt(r2,r2) 1612 LOAD_REG_ADDR(r3, interrupt_base_book3e) 1613 mtspr SPRN_IVPR,r3 1614 sync 1615 blr 1616 1617init_thread_book3e: 1618 lis r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h 1619 mtspr SPRN_EPCR,r3 1620 1621 /* Make sure interrupts are off */ 1622 wrteei 0 1623 1624 /* disable all timers and clear out status */ 1625 li r3,0 1626 mtspr SPRN_TCR,r3 1627 mfspr r3,SPRN_TSR 1628 mtspr SPRN_TSR,r3 1629 1630 blr 1631 1632_GLOBAL(__setup_base_ivors) 1633 SET_IVOR(0, 0x020) /* Critical Input */ 1634 SET_IVOR(1, 0x000) /* Machine Check */ 1635 SET_IVOR(2, 0x060) /* Data Storage */ 1636 SET_IVOR(3, 0x080) /* Instruction Storage */ 1637 SET_IVOR(4, 0x0a0) /* External Input */ 1638 SET_IVOR(5, 0x0c0) /* Alignment */ 1639 SET_IVOR(6, 0x0e0) /* Program */ 1640 SET_IVOR(7, 0x100) /* FP Unavailable */ 1641 SET_IVOR(8, 0x120) /* System Call */ 1642 SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */ 1643 SET_IVOR(10, 0x160) /* Decrementer */ 1644 SET_IVOR(11, 0x180) /* Fixed Interval Timer */ 1645 SET_IVOR(12, 0x1a0) /* Watchdog Timer */ 1646 SET_IVOR(13, 0x1c0) /* Data TLB Error */ 1647 SET_IVOR(14, 0x1e0) /* Instruction TLB Error */ 1648 SET_IVOR(15, 0x040) /* Debug */ 1649 1650 sync 1651 1652 blr 1653 1654_GLOBAL(setup_altivec_ivors) 1655 SET_IVOR(32, 0x200) /* AltiVec Unavailable */ 1656 SET_IVOR(33, 0x220) /* AltiVec Assist */ 1657 blr 1658 1659_GLOBAL(setup_perfmon_ivor) 1660 SET_IVOR(35, 0x260) /* Performance Monitor */ 1661 blr 1662 1663_GLOBAL(setup_doorbell_ivors) 1664 SET_IVOR(36, 0x280) /* Processor Doorbell */ 1665 SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */ 1666 blr 1667 1668_GLOBAL(setup_ehv_ivors) 1669 SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */ 1670 SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */ 1671 SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */ 1672 SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */ 1673 blr 1674 1675_GLOBAL(setup_lrat_ivor) 1676 SET_IVOR(42, 0x340) /* LRAT Error */ 1677 blr 1678