1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * PowerPC version 4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 5 * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP 6 * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com> 7 * Adapted for Power Macintosh by Paul Mackerras. 8 * Low-level exception handlers and MMU support 9 * rewritten by Paul Mackerras. 10 * Copyright (C) 1996 Paul Mackerras. 11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 12 * 13 * This file contains the system call entry code, context switch 14 * code, and exception/interrupt return code for PowerPC. 15 */ 16 17#include <linux/errno.h> 18#include <linux/err.h> 19#include <linux/sys.h> 20#include <linux/threads.h> 21#include <asm/reg.h> 22#include <asm/page.h> 23#include <asm/mmu.h> 24#include <asm/cputable.h> 25#include <asm/thread_info.h> 26#include <asm/ppc_asm.h> 27#include <asm/asm-offsets.h> 28#include <asm/unistd.h> 29#include <asm/ptrace.h> 30#include <asm/export.h> 31#include <asm/feature-fixups.h> 32#include <asm/barrier.h> 33#include <asm/kup.h> 34#include <asm/bug.h> 35 36#include "head_32.h" 37 38/* 39 * powerpc relies on return from interrupt/syscall being context synchronising 40 * (which rfi is) to support ARCH_HAS_MEMBARRIER_SYNC_CORE without additional 41 * synchronisation instructions. 42 */ 43 44/* 45 * Align to 4k in order to ensure that all functions modyfing srr0/srr1 46 * fit into one page in order to not encounter a TLB miss between the 47 * modification of srr0/srr1 and the associated rfi. 48 */ 49 .align 12 50 51#if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_E500) 52 .globl prepare_transfer_to_handler 53prepare_transfer_to_handler: 54 /* if from kernel, check interrupted DOZE/NAP mode */ 55 lwz r12,TI_LOCAL_FLAGS(r2) 56 mtcrf 0x01,r12 57 bt- 31-TLF_NAPPING,4f 58 bt- 31-TLF_SLEEPING,7f 59 blr 60 614: rlwinm r12,r12,0,~_TLF_NAPPING 62 stw r12,TI_LOCAL_FLAGS(r2) 63 b power_save_ppc32_restore 64 657: rlwinm r12,r12,0,~_TLF_SLEEPING 66 stw r12,TI_LOCAL_FLAGS(r2) 67 lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */ 68 rlwinm r9,r9,0,~MSR_EE 69 lwz r12,_LINK(r11) /* and return to address in LR */ 70 lwz r2, GPR2(r11) 71 b fast_exception_return 72_ASM_NOKPROBE_SYMBOL(prepare_transfer_to_handler) 73#endif /* CONFIG_PPC_BOOK3S_32 || CONFIG_E500 */ 74 75 .globl transfer_to_syscall 76transfer_to_syscall: 77 SAVE_NVGPRS(r1) 78 79 /* Calling convention has r9 = orig r0, r10 = regs */ 80 addi r10,r1,STACK_FRAME_OVERHEAD 81 mr r9,r0 82 bl system_call_exception 83 84ret_from_syscall: 85 addi r4,r1,STACK_FRAME_OVERHEAD 86 li r5,0 87 bl syscall_exit_prepare 88#ifdef CONFIG_PPC_47x 89 lis r4,icache_44x_need_flush@ha 90 lwz r5,icache_44x_need_flush@l(r4) 91 cmplwi cr0,r5,0 92 bne- 2f 93#endif /* CONFIG_PPC_47x */ 94 lwz r4,_LINK(r1) 95 lwz r5,_CCR(r1) 96 mtlr r4 97 lwz r7,_NIP(r1) 98 lwz r8,_MSR(r1) 99 cmpwi r3,0 100 lwz r3,GPR3(r1) 101syscall_exit_finish: 102 mtspr SPRN_SRR0,r7 103 mtspr SPRN_SRR1,r8 104 105 bne 3f 106 mtcr r5 107 1081: lwz r2,GPR2(r1) 109 lwz r1,GPR1(r1) 110 rfi 111#ifdef CONFIG_40x 112 b . /* Prevent prefetch past rfi */ 113#endif 114 1153: mtcr r5 116 lwz r4,_CTR(r1) 117 lwz r5,_XER(r1) 118 REST_NVGPRS(r1) 119 mtctr r4 120 mtxer r5 121 lwz r0,GPR0(r1) 122 lwz r3,GPR3(r1) 123 REST_8GPRS(4,r1) 124 lwz r12,GPR12(r1) 125 b 1b 126 127#ifdef CONFIG_44x 1282: li r7,0 129 iccci r0,r0 130 stw r7,icache_44x_need_flush@l(r4) 131 b 1b 132#endif /* CONFIG_44x */ 133 134 .globl ret_from_fork 135ret_from_fork: 136 REST_NVGPRS(r1) 137 bl schedule_tail 138 li r3,0 139 b ret_from_syscall 140 141 .globl ret_from_kernel_thread 142ret_from_kernel_thread: 143 REST_NVGPRS(r1) 144 bl schedule_tail 145 mtlr r14 146 mr r3,r15 147 PPC440EP_ERR42 148 blrl 149 li r3,0 150 b ret_from_syscall 151 152/* 153 * This routine switches between two different tasks. The process 154 * state of one is saved on its kernel stack. Then the state 155 * of the other is restored from its kernel stack. The memory 156 * management hardware is updated to the second process's state. 157 * Finally, we can return to the second process. 158 * On entry, r3 points to the THREAD for the current task, r4 159 * points to the THREAD for the new task. 160 * 161 * This routine is always called with interrupts disabled. 162 * 163 * Note: there are two ways to get to the "going out" portion 164 * of this code; either by coming in via the entry (_switch) 165 * or via "fork" which must set up an environment equivalent 166 * to the "_switch" path. If you change this , you'll have to 167 * change the fork code also. 168 * 169 * The code which creates the new task context is in 'copy_thread' 170 * in arch/ppc/kernel/process.c 171 */ 172_GLOBAL(_switch) 173 stwu r1,-INT_FRAME_SIZE(r1) 174 mflr r0 175 stw r0,INT_FRAME_SIZE+4(r1) 176 /* r3-r12 are caller saved -- Cort */ 177 SAVE_NVGPRS(r1) 178 stw r0,_NIP(r1) /* Return to switch caller */ 179 mfcr r10 180 stw r10,_CCR(r1) 181 stw r1,KSP(r3) /* Set old stack pointer */ 182 183#ifdef CONFIG_SMP 184 /* We need a sync somewhere here to make sure that if the 185 * previous task gets rescheduled on another CPU, it sees all 186 * stores it has performed on this one. 187 */ 188 sync 189#endif /* CONFIG_SMP */ 190 191 tophys(r0,r4) 192 mtspr SPRN_SPRG_THREAD,r0 /* Update current THREAD phys addr */ 193 lwz r1,KSP(r4) /* Load new stack pointer */ 194 195 /* save the old current 'last' for return value */ 196 mr r3,r2 197 addi r2,r4,-THREAD /* Update current */ 198 199 lwz r0,_CCR(r1) 200 mtcrf 0xFF,r0 201 /* r3-r12 are destroyed -- Cort */ 202 REST_NVGPRS(r1) 203 204 lwz r4,_NIP(r1) /* Return to _switch caller in new task */ 205 mtlr r4 206 addi r1,r1,INT_FRAME_SIZE 207 blr 208 209 .globl fast_exception_return 210fast_exception_return: 211#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) 212 andi. r10,r9,MSR_RI /* check for recoverable interrupt */ 213 beq 3f /* if not, we've got problems */ 214#endif 215 2162: REST_4GPRS(3, r11) 217 lwz r10,_CCR(r11) 218 REST_2GPRS(1, r11) 219 mtcr r10 220 lwz r10,_LINK(r11) 221 mtlr r10 222 /* Clear the exception_marker on the stack to avoid confusing stacktrace */ 223 li r10, 0 224 stw r10, 8(r11) 225 REST_GPR(10, r11) 226#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS) 227 mtspr SPRN_NRI, r0 228#endif 229 mtspr SPRN_SRR1,r9 230 mtspr SPRN_SRR0,r12 231 REST_GPR(9, r11) 232 REST_GPR(12, r11) 233 lwz r11,GPR11(r11) 234 rfi 235#ifdef CONFIG_40x 236 b . /* Prevent prefetch past rfi */ 237#endif 238_ASM_NOKPROBE_SYMBOL(fast_exception_return) 239 240/* aargh, a nonrecoverable interrupt, panic */ 241/* aargh, we don't know which trap this is */ 2423: 243 li r10,-1 244 stw r10,_TRAP(r11) 245 prepare_transfer_to_handler 246 bl unrecoverable_exception 247 trap /* should not get here */ 248 249 .globl interrupt_return 250interrupt_return: 251 lwz r4,_MSR(r1) 252 addi r3,r1,STACK_FRAME_OVERHEAD 253 andi. r0,r4,MSR_PR 254 beq .Lkernel_interrupt_return 255 bl interrupt_exit_user_prepare 256 cmpwi r3,0 257 bne- .Lrestore_nvgprs 258 259.Lfast_user_interrupt_return: 260 lwz r11,_NIP(r1) 261 lwz r12,_MSR(r1) 262 mtspr SPRN_SRR0,r11 263 mtspr SPRN_SRR1,r12 264 265BEGIN_FTR_SECTION 266 stwcx. r0,0,r1 /* to clear the reservation */ 267FTR_SECTION_ELSE 268 lwarx r0,0,r1 269ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS) 270 271 lwz r3,_CCR(r1) 272 lwz r4,_LINK(r1) 273 lwz r5,_CTR(r1) 274 lwz r6,_XER(r1) 275 li r0,0 276 277 /* 278 * Leaving a stale exception_marker on the stack can confuse 279 * the reliable stack unwinder later on. Clear it. 280 */ 281 stw r0,8(r1) 282 REST_4GPRS(7, r1) 283 REST_2GPRS(11, r1) 284 285 mtcr r3 286 mtlr r4 287 mtctr r5 288 mtspr SPRN_XER,r6 289 290 REST_4GPRS(2, r1) 291 REST_GPR(6, r1) 292 REST_GPR(0, r1) 293 REST_GPR(1, r1) 294 rfi 295#ifdef CONFIG_40x 296 b . /* Prevent prefetch past rfi */ 297#endif 298 299.Lrestore_nvgprs: 300 REST_NVGPRS(r1) 301 b .Lfast_user_interrupt_return 302 303.Lkernel_interrupt_return: 304 bl interrupt_exit_kernel_prepare 305 306.Lfast_kernel_interrupt_return: 307 cmpwi cr1,r3,0 308 lwz r11,_NIP(r1) 309 lwz r12,_MSR(r1) 310 mtspr SPRN_SRR0,r11 311 mtspr SPRN_SRR1,r12 312 313BEGIN_FTR_SECTION 314 stwcx. r0,0,r1 /* to clear the reservation */ 315FTR_SECTION_ELSE 316 lwarx r0,0,r1 317ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS) 318 319 lwz r3,_LINK(r1) 320 lwz r4,_CTR(r1) 321 lwz r5,_XER(r1) 322 lwz r6,_CCR(r1) 323 li r0,0 324 325 REST_4GPRS(7, r1) 326 REST_2GPRS(11, r1) 327 328 mtlr r3 329 mtctr r4 330 mtspr SPRN_XER,r5 331 332 /* 333 * Leaving a stale exception_marker on the stack can confuse 334 * the reliable stack unwinder later on. Clear it. 335 */ 336 stw r0,8(r1) 337 338 REST_4GPRS(2, r1) 339 340 bne- cr1,1f /* emulate stack store */ 341 mtcr r6 342 REST_GPR(6, r1) 343 REST_GPR(0, r1) 344 REST_GPR(1, r1) 345 rfi 346#ifdef CONFIG_40x 347 b . /* Prevent prefetch past rfi */ 348#endif 349 3501: /* 351 * Emulate stack store with update. New r1 value was already calculated 352 * and updated in our interrupt regs by emulate_loadstore, but we can't 353 * store the previous value of r1 to the stack before re-loading our 354 * registers from it, otherwise they could be clobbered. Use 355 * SPRG Scratch0 as temporary storage to hold the store 356 * data, as interrupts are disabled here so it won't be clobbered. 357 */ 358 mtcr r6 359#ifdef CONFIG_BOOKE 360 mtspr SPRN_SPRG_WSCRATCH0, r9 361#else 362 mtspr SPRN_SPRG_SCRATCH0, r9 363#endif 364 addi r9,r1,INT_FRAME_SIZE /* get original r1 */ 365 REST_GPR(6, r1) 366 REST_GPR(0, r1) 367 REST_GPR(1, r1) 368 stw r9,0(r1) /* perform store component of stwu */ 369#ifdef CONFIG_BOOKE 370 mfspr r9, SPRN_SPRG_RSCRATCH0 371#else 372 mfspr r9, SPRN_SPRG_SCRATCH0 373#endif 374 rfi 375#ifdef CONFIG_40x 376 b . /* Prevent prefetch past rfi */ 377#endif 378_ASM_NOKPROBE_SYMBOL(interrupt_return) 379 380#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 381 382/* 383 * Returning from a critical interrupt in user mode doesn't need 384 * to be any different from a normal exception. For a critical 385 * interrupt in the kernel, we just return (without checking for 386 * preemption) since the interrupt may have happened at some crucial 387 * place (e.g. inside the TLB miss handler), and because we will be 388 * running with r1 pointing into critical_stack, not the current 389 * process's kernel stack (and therefore current_thread_info() will 390 * give the wrong answer). 391 * We have to restore various SPRs that may have been in use at the 392 * time of the critical interrupt. 393 * 394 */ 395#ifdef CONFIG_40x 396#define PPC_40x_TURN_OFF_MSR_DR \ 397 /* avoid any possible TLB misses here by turning off MSR.DR, we \ 398 * assume the instructions here are mapped by a pinned TLB entry */ \ 399 li r10,MSR_IR; \ 400 mtmsr r10; \ 401 isync; \ 402 tophys(r1, r1); 403#else 404#define PPC_40x_TURN_OFF_MSR_DR 405#endif 406 407#define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \ 408 REST_NVGPRS(r1); \ 409 lwz r3,_MSR(r1); \ 410 andi. r3,r3,MSR_PR; \ 411 bne interrupt_return; \ 412 lwz r0,GPR0(r1); \ 413 lwz r2,GPR2(r1); \ 414 REST_4GPRS(3, r1); \ 415 REST_2GPRS(7, r1); \ 416 lwz r10,_XER(r1); \ 417 lwz r11,_CTR(r1); \ 418 mtspr SPRN_XER,r10; \ 419 mtctr r11; \ 420 stwcx. r0,0,r1; /* to clear the reservation */ \ 421 lwz r11,_LINK(r1); \ 422 mtlr r11; \ 423 lwz r10,_CCR(r1); \ 424 mtcrf 0xff,r10; \ 425 PPC_40x_TURN_OFF_MSR_DR; \ 426 lwz r9,_DEAR(r1); \ 427 lwz r10,_ESR(r1); \ 428 mtspr SPRN_DEAR,r9; \ 429 mtspr SPRN_ESR,r10; \ 430 lwz r11,_NIP(r1); \ 431 lwz r12,_MSR(r1); \ 432 mtspr exc_lvl_srr0,r11; \ 433 mtspr exc_lvl_srr1,r12; \ 434 lwz r9,GPR9(r1); \ 435 lwz r12,GPR12(r1); \ 436 lwz r10,GPR10(r1); \ 437 lwz r11,GPR11(r1); \ 438 lwz r1,GPR1(r1); \ 439 exc_lvl_rfi; \ 440 b .; /* prevent prefetch past exc_lvl_rfi */ 441 442#define RESTORE_xSRR(exc_lvl_srr0, exc_lvl_srr1) \ 443 lwz r9,_##exc_lvl_srr0(r1); \ 444 lwz r10,_##exc_lvl_srr1(r1); \ 445 mtspr SPRN_##exc_lvl_srr0,r9; \ 446 mtspr SPRN_##exc_lvl_srr1,r10; 447 448#if defined(CONFIG_PPC_BOOK3E_MMU) 449#ifdef CONFIG_PHYS_64BIT 450#define RESTORE_MAS7 \ 451 lwz r11,MAS7(r1); \ 452 mtspr SPRN_MAS7,r11; 453#else 454#define RESTORE_MAS7 455#endif /* CONFIG_PHYS_64BIT */ 456#define RESTORE_MMU_REGS \ 457 lwz r9,MAS0(r1); \ 458 lwz r10,MAS1(r1); \ 459 lwz r11,MAS2(r1); \ 460 mtspr SPRN_MAS0,r9; \ 461 lwz r9,MAS3(r1); \ 462 mtspr SPRN_MAS1,r10; \ 463 lwz r10,MAS6(r1); \ 464 mtspr SPRN_MAS2,r11; \ 465 mtspr SPRN_MAS3,r9; \ 466 mtspr SPRN_MAS6,r10; \ 467 RESTORE_MAS7; 468#elif defined(CONFIG_44x) 469#define RESTORE_MMU_REGS \ 470 lwz r9,MMUCR(r1); \ 471 mtspr SPRN_MMUCR,r9; 472#else 473#define RESTORE_MMU_REGS 474#endif 475 476#ifdef CONFIG_40x 477 .globl ret_from_crit_exc 478ret_from_crit_exc: 479 lis r9,crit_srr0@ha; 480 lwz r9,crit_srr0@l(r9); 481 lis r10,crit_srr1@ha; 482 lwz r10,crit_srr1@l(r10); 483 mtspr SPRN_SRR0,r9; 484 mtspr SPRN_SRR1,r10; 485 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI) 486_ASM_NOKPROBE_SYMBOL(ret_from_crit_exc) 487#endif /* CONFIG_40x */ 488 489#ifdef CONFIG_BOOKE 490 .globl ret_from_crit_exc 491ret_from_crit_exc: 492 RESTORE_xSRR(SRR0,SRR1); 493 RESTORE_MMU_REGS; 494 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI) 495_ASM_NOKPROBE_SYMBOL(ret_from_crit_exc) 496 497 .globl ret_from_debug_exc 498ret_from_debug_exc: 499 RESTORE_xSRR(SRR0,SRR1); 500 RESTORE_xSRR(CSRR0,CSRR1); 501 RESTORE_MMU_REGS; 502 RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, PPC_RFDI) 503_ASM_NOKPROBE_SYMBOL(ret_from_debug_exc) 504 505 .globl ret_from_mcheck_exc 506ret_from_mcheck_exc: 507 RESTORE_xSRR(SRR0,SRR1); 508 RESTORE_xSRR(CSRR0,CSRR1); 509 RESTORE_xSRR(DSRR0,DSRR1); 510 RESTORE_MMU_REGS; 511 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI) 512_ASM_NOKPROBE_SYMBOL(ret_from_mcheck_exc) 513#endif /* CONFIG_BOOKE */ 514#endif /* !(CONFIG_4xx || CONFIG_BOOKE) */ 515 516/* 517 * PROM code for specific machines follows. Put it 518 * here so it's easy to add arch-specific sections later. 519 * -- Cort 520 */ 521#ifdef CONFIG_PPC_RTAS 522/* 523 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be 524 * called with the MMU off. 525 */ 526_GLOBAL(enter_rtas) 527 stwu r1,-INT_FRAME_SIZE(r1) 528 mflr r0 529 stw r0,INT_FRAME_SIZE+4(r1) 530 LOAD_REG_ADDR(r4, rtas) 531 lis r6,1f@ha /* physical return address for rtas */ 532 addi r6,r6,1f@l 533 tophys(r6,r6) 534 lwz r8,RTASENTRY(r4) 535 lwz r4,RTASBASE(r4) 536 mfmsr r9 537 stw r9,8(r1) 538 LOAD_REG_IMMEDIATE(r0,MSR_KERNEL) 539 mtmsr r0 /* disable interrupts so SRR0/1 don't get trashed */ 540 li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR) 541 mtlr r6 542 stw r1, THREAD + RTAS_SP(r2) 543 mtspr SPRN_SRR0,r8 544 mtspr SPRN_SRR1,r9 545 rfi 5461: 547 lis r8, 1f@h 548 ori r8, r8, 1f@l 549 LOAD_REG_IMMEDIATE(r9,MSR_KERNEL) 550 mtspr SPRN_SRR0,r8 551 mtspr SPRN_SRR1,r9 552 rfi /* Reactivate MMU translation */ 5531: 554 lwz r8,INT_FRAME_SIZE+4(r1) /* get return address */ 555 lwz r9,8(r1) /* original msr value */ 556 addi r1,r1,INT_FRAME_SIZE 557 li r0,0 558 stw r0, THREAD + RTAS_SP(r2) 559 mtlr r8 560 mtmsr r9 561 blr /* return to caller */ 562_ASM_NOKPROBE_SYMBOL(enter_rtas) 563#endif /* CONFIG_PPC_RTAS */ 564