1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * PowerPC version 4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 5 * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP 6 * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com> 7 * Adapted for Power Macintosh by Paul Mackerras. 8 * Low-level exception handlers and MMU support 9 * rewritten by Paul Mackerras. 10 * Copyright (C) 1996 Paul Mackerras. 11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 12 * 13 * This file contains the system call entry code, context switch 14 * code, and exception/interrupt return code for PowerPC. 15 */ 16 17#include <linux/errno.h> 18#include <linux/err.h> 19#include <linux/sys.h> 20#include <linux/threads.h> 21#include <linux/linkage.h> 22 23#include <asm/reg.h> 24#include <asm/page.h> 25#include <asm/mmu.h> 26#include <asm/cputable.h> 27#include <asm/thread_info.h> 28#include <asm/ppc_asm.h> 29#include <asm/asm-offsets.h> 30#include <asm/unistd.h> 31#include <asm/ptrace.h> 32#include <asm/export.h> 33#include <asm/feature-fixups.h> 34#include <asm/barrier.h> 35#include <asm/kup.h> 36#include <asm/bug.h> 37#include <asm/interrupt.h> 38 39#include "head_32.h" 40 41/* 42 * powerpc relies on return from interrupt/syscall being context synchronising 43 * (which rfi is) to support ARCH_HAS_MEMBARRIER_SYNC_CORE without additional 44 * synchronisation instructions. 45 */ 46 47/* 48 * Align to 4k in order to ensure that all functions modyfing srr0/srr1 49 * fit into one page in order to not encounter a TLB miss between the 50 * modification of srr0/srr1 and the associated rfi. 51 */ 52 .align 12 53 54#if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_PPC_E500) 55 .globl prepare_transfer_to_handler 56prepare_transfer_to_handler: 57 /* if from kernel, check interrupted DOZE/NAP mode */ 58 lwz r12,TI_LOCAL_FLAGS(r2) 59 mtcrf 0x01,r12 60 bt- 31-TLF_NAPPING,4f 61 bt- 31-TLF_SLEEPING,7f 62 blr 63 644: rlwinm r12,r12,0,~_TLF_NAPPING 65 stw r12,TI_LOCAL_FLAGS(r2) 66 b power_save_ppc32_restore 67 687: rlwinm r12,r12,0,~_TLF_SLEEPING 69 stw r12,TI_LOCAL_FLAGS(r2) 70 lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */ 71 rlwinm r9,r9,0,~MSR_EE 72 lwz r12,_LINK(r11) /* and return to address in LR */ 73 REST_GPR(2, r11) 74 b fast_exception_return 75_ASM_NOKPROBE_SYMBOL(prepare_transfer_to_handler) 76#endif /* CONFIG_PPC_BOOK3S_32 || CONFIG_PPC_E500 */ 77 78#if defined(CONFIG_PPC_KUEP) && defined(CONFIG_PPC_BOOK3S_32) 79SYM_FUNC_START(__kuep_lock) 80 lwz r9, THREAD+THSR0(r2) 81 update_user_segments_by_4 r9, r10, r11, r12 82 blr 83SYM_FUNC_END(__kuep_lock) 84 85SYM_FUNC_START_LOCAL(__kuep_unlock) 86 lwz r9, THREAD+THSR0(r2) 87 rlwinm r9,r9,0,~SR_NX 88 update_user_segments_by_4 r9, r10, r11, r12 89 blr 90SYM_FUNC_END(__kuep_unlock) 91 92.macro kuep_lock 93 bl __kuep_lock 94.endm 95.macro kuep_unlock 96 bl __kuep_unlock 97.endm 98#else 99.macro kuep_lock 100.endm 101.macro kuep_unlock 102.endm 103#endif 104 105 .globl transfer_to_syscall 106transfer_to_syscall: 107 stw r3, ORIG_GPR3(r1) 108 stw r11, GPR1(r1) 109 stw r11, 0(r1) 110 mflr r12 111 stw r12, _LINK(r1) 112#ifdef CONFIG_BOOKE_OR_40x 113 rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */ 114#endif 115 lis r12,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */ 116 SAVE_GPR(2, r1) 117 addi r12,r12,STACK_FRAME_REGS_MARKER@l 118 stw r9,_MSR(r1) 119 li r2, INTERRUPT_SYSCALL 120 stw r12,STACK_INT_FRAME_MARKER(r1) 121 stw r2,_TRAP(r1) 122 SAVE_GPR(0, r1) 123 SAVE_GPRS(3, 8, r1) 124 addi r2,r10,-THREAD 125 SAVE_NVGPRS(r1) 126 kuep_lock 127 128 /* Calling convention has r3 = regs, r4 = orig r0 */ 129 addi r3,r1,STACK_INT_FRAME_REGS 130 mr r4,r0 131 bl system_call_exception 132 133ret_from_syscall: 134 addi r4,r1,STACK_INT_FRAME_REGS 135 li r5,0 136 bl syscall_exit_prepare 137#ifdef CONFIG_PPC_47x 138 lis r4,icache_44x_need_flush@ha 139 lwz r5,icache_44x_need_flush@l(r4) 140 cmplwi cr0,r5,0 141 bne- 2f 142#endif /* CONFIG_PPC_47x */ 143 kuep_unlock 144 lwz r4,_LINK(r1) 145 lwz r5,_CCR(r1) 146 mtlr r4 147 lwz r7,_NIP(r1) 148 lwz r8,_MSR(r1) 149 cmpwi r3,0 150 REST_GPR(3, r1) 151syscall_exit_finish: 152 mtspr SPRN_SRR0,r7 153 mtspr SPRN_SRR1,r8 154 155 bne 3f 156 mtcr r5 157 1581: REST_GPR(2, r1) 159 REST_GPR(1, r1) 160 rfi 161#ifdef CONFIG_40x 162 b . /* Prevent prefetch past rfi */ 163#endif 164 1653: mtcr r5 166 lwz r4,_CTR(r1) 167 lwz r5,_XER(r1) 168 REST_NVGPRS(r1) 169 mtctr r4 170 mtxer r5 171 REST_GPR(0, r1) 172 REST_GPRS(3, 12, r1) 173 b 1b 174 175#ifdef CONFIG_44x 1762: li r7,0 177 iccci r0,r0 178 stw r7,icache_44x_need_flush@l(r4) 179 b 1b 180#endif /* CONFIG_44x */ 181 182 .globl ret_from_fork 183ret_from_fork: 184 REST_NVGPRS(r1) 185 bl schedule_tail 186 li r3,0 /* fork() return value */ 187 b ret_from_syscall 188 189 .globl ret_from_kernel_user_thread 190ret_from_kernel_user_thread: 191 bl schedule_tail 192 mtctr r14 193 mr r3,r15 194 PPC440EP_ERR42 195 bctrl 196 li r3,0 197 b ret_from_syscall 198 199 .globl start_kernel_thread 200start_kernel_thread: 201 bl schedule_tail 202 mtctr r14 203 mr r3,r15 204 PPC440EP_ERR42 205 bctrl 206 /* 207 * This must not return. We actually want to BUG here, not WARN, 208 * because BUG will exit the process which is what the kernel thread 209 * should have done, which may give some hope of continuing. 210 */ 211100: trap 212 EMIT_BUG_ENTRY 100b,__FILE__,__LINE__,0 213 214 .globl fast_exception_return 215fast_exception_return: 216#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) 217 andi. r10,r9,MSR_RI /* check for recoverable interrupt */ 218 beq 3f /* if not, we've got problems */ 219#endif 220 2212: lwz r10,_CCR(r11) 222 REST_GPRS(1, 6, r11) 223 mtcr r10 224 lwz r10,_LINK(r11) 225 mtlr r10 226 /* Clear the exception marker on the stack to avoid confusing stacktrace */ 227 li r10, 0 228 stw r10, 8(r11) 229 REST_GPR(10, r11) 230#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS) 231 mtspr SPRN_NRI, r0 232#endif 233 mtspr SPRN_SRR1,r9 234 mtspr SPRN_SRR0,r12 235 REST_GPR(9, r11) 236 REST_GPR(12, r11) 237 REST_GPR(11, r11) 238 rfi 239#ifdef CONFIG_40x 240 b . /* Prevent prefetch past rfi */ 241#endif 242_ASM_NOKPROBE_SYMBOL(fast_exception_return) 243 244/* aargh, a nonrecoverable interrupt, panic */ 245/* aargh, we don't know which trap this is */ 2463: 247 li r10,-1 248 stw r10,_TRAP(r11) 249 prepare_transfer_to_handler 250 bl unrecoverable_exception 251 trap /* should not get here */ 252 253 .globl interrupt_return 254interrupt_return: 255 lwz r4,_MSR(r1) 256 addi r3,r1,STACK_INT_FRAME_REGS 257 andi. r0,r4,MSR_PR 258 beq .Lkernel_interrupt_return 259 bl interrupt_exit_user_prepare 260 cmpwi r3,0 261 kuep_unlock 262 bne- .Lrestore_nvgprs 263 264.Lfast_user_interrupt_return: 265 lwz r11,_NIP(r1) 266 lwz r12,_MSR(r1) 267 mtspr SPRN_SRR0,r11 268 mtspr SPRN_SRR1,r12 269 270BEGIN_FTR_SECTION 271 stwcx. r0,0,r1 /* to clear the reservation */ 272FTR_SECTION_ELSE 273 lwarx r0,0,r1 274ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS) 275 276 lwz r3,_CCR(r1) 277 lwz r4,_LINK(r1) 278 lwz r5,_CTR(r1) 279 lwz r6,_XER(r1) 280 li r0,0 281 282 /* 283 * Leaving a stale exception marker on the stack can confuse 284 * the reliable stack unwinder later on. Clear it. 285 */ 286 stw r0,8(r1) 287 REST_GPRS(7, 12, r1) 288 289 mtcr r3 290 mtlr r4 291 mtctr r5 292 mtspr SPRN_XER,r6 293 294 REST_GPRS(2, 6, r1) 295 REST_GPR(0, r1) 296 REST_GPR(1, r1) 297 rfi 298#ifdef CONFIG_40x 299 b . /* Prevent prefetch past rfi */ 300#endif 301 302.Lrestore_nvgprs: 303 REST_NVGPRS(r1) 304 b .Lfast_user_interrupt_return 305 306.Lkernel_interrupt_return: 307 bl interrupt_exit_kernel_prepare 308 309.Lfast_kernel_interrupt_return: 310 cmpwi cr1,r3,0 311 lwz r11,_NIP(r1) 312 lwz r12,_MSR(r1) 313 mtspr SPRN_SRR0,r11 314 mtspr SPRN_SRR1,r12 315 316BEGIN_FTR_SECTION 317 stwcx. r0,0,r1 /* to clear the reservation */ 318FTR_SECTION_ELSE 319 lwarx r0,0,r1 320ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS) 321 322 lwz r3,_LINK(r1) 323 lwz r4,_CTR(r1) 324 lwz r5,_XER(r1) 325 lwz r6,_CCR(r1) 326 li r0,0 327 328 REST_GPRS(7, 12, r1) 329 330 mtlr r3 331 mtctr r4 332 mtspr SPRN_XER,r5 333 334 /* 335 * Leaving a stale exception marker on the stack can confuse 336 * the reliable stack unwinder later on. Clear it. 337 */ 338 stw r0,8(r1) 339 340 REST_GPRS(2, 5, r1) 341 342 bne- cr1,1f /* emulate stack store */ 343 mtcr r6 344 REST_GPR(6, r1) 345 REST_GPR(0, r1) 346 REST_GPR(1, r1) 347 rfi 348#ifdef CONFIG_40x 349 b . /* Prevent prefetch past rfi */ 350#endif 351 3521: /* 353 * Emulate stack store with update. New r1 value was already calculated 354 * and updated in our interrupt regs by emulate_loadstore, but we can't 355 * store the previous value of r1 to the stack before re-loading our 356 * registers from it, otherwise they could be clobbered. Use 357 * SPRG Scratch0 as temporary storage to hold the store 358 * data, as interrupts are disabled here so it won't be clobbered. 359 */ 360 mtcr r6 361#ifdef CONFIG_BOOKE 362 mtspr SPRN_SPRG_WSCRATCH0, r9 363#else 364 mtspr SPRN_SPRG_SCRATCH0, r9 365#endif 366 addi r9,r1,INT_FRAME_SIZE /* get original r1 */ 367 REST_GPR(6, r1) 368 REST_GPR(0, r1) 369 REST_GPR(1, r1) 370 stw r9,0(r1) /* perform store component of stwu */ 371#ifdef CONFIG_BOOKE 372 mfspr r9, SPRN_SPRG_RSCRATCH0 373#else 374 mfspr r9, SPRN_SPRG_SCRATCH0 375#endif 376 rfi 377#ifdef CONFIG_40x 378 b . /* Prevent prefetch past rfi */ 379#endif 380_ASM_NOKPROBE_SYMBOL(interrupt_return) 381 382#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 383 384/* 385 * Returning from a critical interrupt in user mode doesn't need 386 * to be any different from a normal exception. For a critical 387 * interrupt in the kernel, we just return (without checking for 388 * preemption) since the interrupt may have happened at some crucial 389 * place (e.g. inside the TLB miss handler), and because we will be 390 * running with r1 pointing into critical_stack, not the current 391 * process's kernel stack (and therefore current_thread_info() will 392 * give the wrong answer). 393 * We have to restore various SPRs that may have been in use at the 394 * time of the critical interrupt. 395 * 396 */ 397#ifdef CONFIG_40x 398#define PPC_40x_TURN_OFF_MSR_DR \ 399 /* avoid any possible TLB misses here by turning off MSR.DR, we \ 400 * assume the instructions here are mapped by a pinned TLB entry */ \ 401 li r10,MSR_IR; \ 402 mtmsr r10; \ 403 isync; \ 404 tophys(r1, r1); 405#else 406#define PPC_40x_TURN_OFF_MSR_DR 407#endif 408 409#define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \ 410 REST_NVGPRS(r1); \ 411 lwz r3,_MSR(r1); \ 412 andi. r3,r3,MSR_PR; \ 413 bne interrupt_return; \ 414 REST_GPR(0, r1); \ 415 REST_GPRS(2, 8, r1); \ 416 lwz r10,_XER(r1); \ 417 lwz r11,_CTR(r1); \ 418 mtspr SPRN_XER,r10; \ 419 mtctr r11; \ 420 stwcx. r0,0,r1; /* to clear the reservation */ \ 421 lwz r11,_LINK(r1); \ 422 mtlr r11; \ 423 lwz r10,_CCR(r1); \ 424 mtcrf 0xff,r10; \ 425 PPC_40x_TURN_OFF_MSR_DR; \ 426 lwz r9,_DEAR(r1); \ 427 lwz r10,_ESR(r1); \ 428 mtspr SPRN_DEAR,r9; \ 429 mtspr SPRN_ESR,r10; \ 430 lwz r11,_NIP(r1); \ 431 lwz r12,_MSR(r1); \ 432 mtspr exc_lvl_srr0,r11; \ 433 mtspr exc_lvl_srr1,r12; \ 434 REST_GPRS(9, 12, r1); \ 435 REST_GPR(1, r1); \ 436 exc_lvl_rfi; \ 437 b .; /* prevent prefetch past exc_lvl_rfi */ 438 439#define RESTORE_xSRR(exc_lvl_srr0, exc_lvl_srr1) \ 440 lwz r9,_##exc_lvl_srr0(r1); \ 441 lwz r10,_##exc_lvl_srr1(r1); \ 442 mtspr SPRN_##exc_lvl_srr0,r9; \ 443 mtspr SPRN_##exc_lvl_srr1,r10; 444 445#if defined(CONFIG_PPC_E500) 446#ifdef CONFIG_PHYS_64BIT 447#define RESTORE_MAS7 \ 448 lwz r11,MAS7(r1); \ 449 mtspr SPRN_MAS7,r11; 450#else 451#define RESTORE_MAS7 452#endif /* CONFIG_PHYS_64BIT */ 453#define RESTORE_MMU_REGS \ 454 lwz r9,MAS0(r1); \ 455 lwz r10,MAS1(r1); \ 456 lwz r11,MAS2(r1); \ 457 mtspr SPRN_MAS0,r9; \ 458 lwz r9,MAS3(r1); \ 459 mtspr SPRN_MAS1,r10; \ 460 lwz r10,MAS6(r1); \ 461 mtspr SPRN_MAS2,r11; \ 462 mtspr SPRN_MAS3,r9; \ 463 mtspr SPRN_MAS6,r10; \ 464 RESTORE_MAS7; 465#elif defined(CONFIG_44x) 466#define RESTORE_MMU_REGS \ 467 lwz r9,MMUCR(r1); \ 468 mtspr SPRN_MMUCR,r9; 469#else 470#define RESTORE_MMU_REGS 471#endif 472 473#ifdef CONFIG_40x 474 .globl ret_from_crit_exc 475ret_from_crit_exc: 476 lis r9,crit_srr0@ha; 477 lwz r9,crit_srr0@l(r9); 478 lis r10,crit_srr1@ha; 479 lwz r10,crit_srr1@l(r10); 480 mtspr SPRN_SRR0,r9; 481 mtspr SPRN_SRR1,r10; 482 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI) 483_ASM_NOKPROBE_SYMBOL(ret_from_crit_exc) 484#endif /* CONFIG_40x */ 485 486#ifdef CONFIG_BOOKE 487 .globl ret_from_crit_exc 488ret_from_crit_exc: 489 RESTORE_xSRR(SRR0,SRR1); 490 RESTORE_MMU_REGS; 491 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI) 492_ASM_NOKPROBE_SYMBOL(ret_from_crit_exc) 493 494 .globl ret_from_debug_exc 495ret_from_debug_exc: 496 RESTORE_xSRR(SRR0,SRR1); 497 RESTORE_xSRR(CSRR0,CSRR1); 498 RESTORE_MMU_REGS; 499 RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, PPC_RFDI) 500_ASM_NOKPROBE_SYMBOL(ret_from_debug_exc) 501 502 .globl ret_from_mcheck_exc 503ret_from_mcheck_exc: 504 RESTORE_xSRR(SRR0,SRR1); 505 RESTORE_xSRR(CSRR0,CSRR1); 506 RESTORE_xSRR(DSRR0,DSRR1); 507 RESTORE_MMU_REGS; 508 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI) 509_ASM_NOKPROBE_SYMBOL(ret_from_mcheck_exc) 510#endif /* CONFIG_BOOKE */ 511#endif /* !(CONFIG_4xx || CONFIG_BOOKE) */ 512