1 /* 2 * PCI address cache; allows the lookup of PCI devices based on I/O address 3 * 4 * Copyright IBM Corporation 2004 5 * Copyright Linas Vepstas <linas@austin.ibm.com> 2004 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 22 #include <linux/list.h> 23 #include <linux/pci.h> 24 #include <linux/rbtree.h> 25 #include <linux/slab.h> 26 #include <linux/spinlock.h> 27 #include <linux/atomic.h> 28 #include <asm/pci-bridge.h> 29 #include <asm/ppc-pci.h> 30 31 32 /** 33 * The pci address cache subsystem. This subsystem places 34 * PCI device address resources into a red-black tree, sorted 35 * according to the address range, so that given only an i/o 36 * address, the corresponding PCI device can be **quickly** 37 * found. It is safe to perform an address lookup in an interrupt 38 * context; this ability is an important feature. 39 * 40 * Currently, the only customer of this code is the EEH subsystem; 41 * thus, this code has been somewhat tailored to suit EEH better. 42 * In particular, the cache does *not* hold the addresses of devices 43 * for which EEH is not enabled. 44 * 45 * (Implementation Note: The RB tree seems to be better/faster 46 * than any hash algo I could think of for this problem, even 47 * with the penalty of slow pointer chases for d-cache misses). 48 */ 49 struct pci_io_addr_range { 50 struct rb_node rb_node; 51 resource_size_t addr_lo; 52 resource_size_t addr_hi; 53 struct eeh_dev *edev; 54 struct pci_dev *pcidev; 55 unsigned long flags; 56 }; 57 58 static struct pci_io_addr_cache { 59 struct rb_root rb_root; 60 spinlock_t piar_lock; 61 } pci_io_addr_cache_root; 62 63 static inline struct eeh_dev *__eeh_addr_cache_get_device(unsigned long addr) 64 { 65 struct rb_node *n = pci_io_addr_cache_root.rb_root.rb_node; 66 67 while (n) { 68 struct pci_io_addr_range *piar; 69 piar = rb_entry(n, struct pci_io_addr_range, rb_node); 70 71 if (addr < piar->addr_lo) 72 n = n->rb_left; 73 else if (addr > piar->addr_hi) 74 n = n->rb_right; 75 else 76 return piar->edev; 77 } 78 79 return NULL; 80 } 81 82 /** 83 * eeh_addr_cache_get_dev - Get device, given only address 84 * @addr: mmio (PIO) phys address or i/o port number 85 * 86 * Given an mmio phys address, or a port number, find a pci device 87 * that implements this address. I/O port numbers are assumed to be offset 88 * from zero (that is, they do *not* have pci_io_addr added in). 89 * It is safe to call this function within an interrupt. 90 */ 91 struct eeh_dev *eeh_addr_cache_get_dev(unsigned long addr) 92 { 93 struct eeh_dev *edev; 94 unsigned long flags; 95 96 spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags); 97 edev = __eeh_addr_cache_get_device(addr); 98 spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags); 99 return edev; 100 } 101 102 #ifdef DEBUG 103 /* 104 * Handy-dandy debug print routine, does nothing more 105 * than print out the contents of our addr cache. 106 */ 107 static void eeh_addr_cache_print(struct pci_io_addr_cache *cache) 108 { 109 struct rb_node *n; 110 int cnt = 0; 111 112 n = rb_first(&cache->rb_root); 113 while (n) { 114 struct pci_io_addr_range *piar; 115 piar = rb_entry(n, struct pci_io_addr_range, rb_node); 116 pr_debug("PCI: %s addr range %d [%pap-%pap]: %s\n", 117 (piar->flags & IORESOURCE_IO) ? "i/o" : "mem", cnt, 118 &piar->addr_lo, &piar->addr_hi, pci_name(piar->pcidev)); 119 cnt++; 120 n = rb_next(n); 121 } 122 } 123 #endif 124 125 /* Insert address range into the rb tree. */ 126 static struct pci_io_addr_range * 127 eeh_addr_cache_insert(struct pci_dev *dev, resource_size_t alo, 128 resource_size_t ahi, unsigned long flags) 129 { 130 struct rb_node **p = &pci_io_addr_cache_root.rb_root.rb_node; 131 struct rb_node *parent = NULL; 132 struct pci_io_addr_range *piar; 133 134 /* Walk tree, find a place to insert into tree */ 135 while (*p) { 136 parent = *p; 137 piar = rb_entry(parent, struct pci_io_addr_range, rb_node); 138 if (ahi < piar->addr_lo) { 139 p = &parent->rb_left; 140 } else if (alo > piar->addr_hi) { 141 p = &parent->rb_right; 142 } else { 143 if (dev != piar->pcidev || 144 alo != piar->addr_lo || ahi != piar->addr_hi) { 145 pr_warn("PIAR: overlapping address range\n"); 146 } 147 return piar; 148 } 149 } 150 piar = kzalloc(sizeof(struct pci_io_addr_range), GFP_ATOMIC); 151 if (!piar) 152 return NULL; 153 154 piar->addr_lo = alo; 155 piar->addr_hi = ahi; 156 piar->edev = pci_dev_to_eeh_dev(dev); 157 piar->pcidev = dev; 158 piar->flags = flags; 159 160 #ifdef DEBUG 161 pr_debug("PIAR: insert range=[%pap:%pap] dev=%s\n", 162 &alo, &ahi, pci_name(dev)); 163 #endif 164 165 rb_link_node(&piar->rb_node, parent, p); 166 rb_insert_color(&piar->rb_node, &pci_io_addr_cache_root.rb_root); 167 168 return piar; 169 } 170 171 static void __eeh_addr_cache_insert_dev(struct pci_dev *dev) 172 { 173 struct pci_dn *pdn; 174 struct eeh_dev *edev; 175 int i; 176 177 pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); 178 if (!pdn) { 179 pr_warn("PCI: no pci dn found for dev=%s\n", 180 pci_name(dev)); 181 return; 182 } 183 184 edev = pdn_to_eeh_dev(pdn); 185 if (!edev) { 186 pr_warn("PCI: no EEH dev found for %s\n", 187 pci_name(dev)); 188 return; 189 } 190 191 /* Skip any devices for which EEH is not enabled. */ 192 if (!edev->pe) { 193 dev_dbg(&dev->dev, "EEH: Skip building address cache\n"); 194 return; 195 } 196 197 /* 198 * Walk resources on this device, poke the first 7 (6 normal BAR and 1 199 * ROM BAR) into the tree. 200 */ 201 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 202 resource_size_t start = pci_resource_start(dev,i); 203 resource_size_t end = pci_resource_end(dev,i); 204 unsigned long flags = pci_resource_flags(dev,i); 205 206 /* We are interested only bus addresses, not dma or other stuff */ 207 if (0 == (flags & (IORESOURCE_IO | IORESOURCE_MEM))) 208 continue; 209 if (start == 0 || ~start == 0 || end == 0 || ~end == 0) 210 continue; 211 eeh_addr_cache_insert(dev, start, end, flags); 212 } 213 } 214 215 /** 216 * eeh_addr_cache_insert_dev - Add a device to the address cache 217 * @dev: PCI device whose I/O addresses we are interested in. 218 * 219 * In order to support the fast lookup of devices based on addresses, 220 * we maintain a cache of devices that can be quickly searched. 221 * This routine adds a device to that cache. 222 */ 223 void eeh_addr_cache_insert_dev(struct pci_dev *dev) 224 { 225 unsigned long flags; 226 227 spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags); 228 __eeh_addr_cache_insert_dev(dev); 229 spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags); 230 } 231 232 static inline void __eeh_addr_cache_rmv_dev(struct pci_dev *dev) 233 { 234 struct rb_node *n; 235 236 restart: 237 n = rb_first(&pci_io_addr_cache_root.rb_root); 238 while (n) { 239 struct pci_io_addr_range *piar; 240 piar = rb_entry(n, struct pci_io_addr_range, rb_node); 241 242 if (piar->pcidev == dev) { 243 rb_erase(n, &pci_io_addr_cache_root.rb_root); 244 kfree(piar); 245 goto restart; 246 } 247 n = rb_next(n); 248 } 249 } 250 251 /** 252 * eeh_addr_cache_rmv_dev - remove pci device from addr cache 253 * @dev: device to remove 254 * 255 * Remove a device from the addr-cache tree. 256 * This is potentially expensive, since it will walk 257 * the tree multiple times (once per resource). 258 * But so what; device removal doesn't need to be that fast. 259 */ 260 void eeh_addr_cache_rmv_dev(struct pci_dev *dev) 261 { 262 unsigned long flags; 263 264 spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags); 265 __eeh_addr_cache_rmv_dev(dev); 266 spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags); 267 } 268 269 /** 270 * eeh_addr_cache_build - Build a cache of I/O addresses 271 * 272 * Build a cache of pci i/o addresses. This cache will be used to 273 * find the pci device that corresponds to a given address. 274 * This routine scans all pci busses to build the cache. 275 * Must be run late in boot process, after the pci controllers 276 * have been scanned for devices (after all device resources are known). 277 */ 278 void eeh_addr_cache_build(void) 279 { 280 struct pci_dn *pdn; 281 struct eeh_dev *edev; 282 struct pci_dev *dev = NULL; 283 284 spin_lock_init(&pci_io_addr_cache_root.piar_lock); 285 286 for_each_pci_dev(dev) { 287 pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); 288 if (!pdn) 289 continue; 290 291 edev = pdn_to_eeh_dev(pdn); 292 if (!edev) 293 continue; 294 295 dev->dev.archdata.edev = edev; 296 edev->pdev = dev; 297 298 eeh_addr_cache_insert_dev(dev); 299 eeh_sysfs_add_device(dev); 300 } 301 302 #ifdef DEBUG 303 /* Verify tree built up above, echo back the list of addrs. */ 304 eeh_addr_cache_print(&pci_io_addr_cache_root); 305 #endif 306 } 307