1 /* 2 * Copyright IBM Corporation 2001, 2005, 2006 3 * Copyright Dave Engebretsen & Todd Inglett 2001 4 * Copyright Linas Vepstas 2005, 2006 5 * Copyright 2001-2012 IBM Corporation. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 * 21 * Please address comments and feedback to Linas Vepstas <linas@austin.ibm.com> 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/debugfs.h> 26 #include <linux/sched.h> 27 #include <linux/init.h> 28 #include <linux/list.h> 29 #include <linux/pci.h> 30 #include <linux/iommu.h> 31 #include <linux/proc_fs.h> 32 #include <linux/rbtree.h> 33 #include <linux/reboot.h> 34 #include <linux/seq_file.h> 35 #include <linux/spinlock.h> 36 #include <linux/export.h> 37 #include <linux/of.h> 38 39 #include <linux/atomic.h> 40 #include <asm/debug.h> 41 #include <asm/eeh.h> 42 #include <asm/eeh_event.h> 43 #include <asm/io.h> 44 #include <asm/iommu.h> 45 #include <asm/machdep.h> 46 #include <asm/ppc-pci.h> 47 #include <asm/rtas.h> 48 49 50 /** Overview: 51 * EEH, or "Enhanced Error Handling" is a PCI bridge technology for 52 * dealing with PCI bus errors that can't be dealt with within the 53 * usual PCI framework, except by check-stopping the CPU. Systems 54 * that are designed for high-availability/reliability cannot afford 55 * to crash due to a "mere" PCI error, thus the need for EEH. 56 * An EEH-capable bridge operates by converting a detected error 57 * into a "slot freeze", taking the PCI adapter off-line, making 58 * the slot behave, from the OS'es point of view, as if the slot 59 * were "empty": all reads return 0xff's and all writes are silently 60 * ignored. EEH slot isolation events can be triggered by parity 61 * errors on the address or data busses (e.g. during posted writes), 62 * which in turn might be caused by low voltage on the bus, dust, 63 * vibration, humidity, radioactivity or plain-old failed hardware. 64 * 65 * Note, however, that one of the leading causes of EEH slot 66 * freeze events are buggy device drivers, buggy device microcode, 67 * or buggy device hardware. This is because any attempt by the 68 * device to bus-master data to a memory address that is not 69 * assigned to the device will trigger a slot freeze. (The idea 70 * is to prevent devices-gone-wild from corrupting system memory). 71 * Buggy hardware/drivers will have a miserable time co-existing 72 * with EEH. 73 * 74 * Ideally, a PCI device driver, when suspecting that an isolation 75 * event has occurred (e.g. by reading 0xff's), will then ask EEH 76 * whether this is the case, and then take appropriate steps to 77 * reset the PCI slot, the PCI device, and then resume operations. 78 * However, until that day, the checking is done here, with the 79 * eeh_check_failure() routine embedded in the MMIO macros. If 80 * the slot is found to be isolated, an "EEH Event" is synthesized 81 * and sent out for processing. 82 */ 83 84 /* If a device driver keeps reading an MMIO register in an interrupt 85 * handler after a slot isolation event, it might be broken. 86 * This sets the threshold for how many read attempts we allow 87 * before printing an error message. 88 */ 89 #define EEH_MAX_FAILS 2100000 90 91 /* Time to wait for a PCI slot to report status, in milliseconds */ 92 #define PCI_BUS_RESET_WAIT_MSEC (5*60*1000) 93 94 /* 95 * EEH probe mode support, which is part of the flags, 96 * is to support multiple platforms for EEH. Some platforms 97 * like pSeries do PCI emunation based on device tree. 98 * However, other platforms like powernv probe PCI devices 99 * from hardware. The flag is used to distinguish that. 100 * In addition, struct eeh_ops::probe would be invoked for 101 * particular OF node or PCI device so that the corresponding 102 * PE would be created there. 103 */ 104 int eeh_subsystem_flags; 105 EXPORT_SYMBOL(eeh_subsystem_flags); 106 107 /* 108 * EEH allowed maximal frozen times. If one particular PE's 109 * frozen count in last hour exceeds this limit, the PE will 110 * be forced to be offline permanently. 111 */ 112 int eeh_max_freezes = 5; 113 114 /* Platform dependent EEH operations */ 115 struct eeh_ops *eeh_ops = NULL; 116 117 /* Lock to avoid races due to multiple reports of an error */ 118 DEFINE_RAW_SPINLOCK(confirm_error_lock); 119 EXPORT_SYMBOL_GPL(confirm_error_lock); 120 121 /* Lock to protect passed flags */ 122 static DEFINE_MUTEX(eeh_dev_mutex); 123 124 /* Buffer for reporting pci register dumps. Its here in BSS, and 125 * not dynamically alloced, so that it ends up in RMO where RTAS 126 * can access it. 127 */ 128 #define EEH_PCI_REGS_LOG_LEN 8192 129 static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN]; 130 131 /* 132 * The struct is used to maintain the EEH global statistic 133 * information. Besides, the EEH global statistics will be 134 * exported to user space through procfs 135 */ 136 struct eeh_stats { 137 u64 no_device; /* PCI device not found */ 138 u64 no_dn; /* OF node not found */ 139 u64 no_cfg_addr; /* Config address not found */ 140 u64 ignored_check; /* EEH check skipped */ 141 u64 total_mmio_ffs; /* Total EEH checks */ 142 u64 false_positives; /* Unnecessary EEH checks */ 143 u64 slot_resets; /* PE reset */ 144 }; 145 146 static struct eeh_stats eeh_stats; 147 148 static int __init eeh_setup(char *str) 149 { 150 if (!strcmp(str, "off")) 151 eeh_add_flag(EEH_FORCE_DISABLED); 152 else if (!strcmp(str, "early_log")) 153 eeh_add_flag(EEH_EARLY_DUMP_LOG); 154 155 return 1; 156 } 157 __setup("eeh=", eeh_setup); 158 159 /* 160 * This routine captures assorted PCI configuration space data 161 * for the indicated PCI device, and puts them into a buffer 162 * for RTAS error logging. 163 */ 164 static size_t eeh_dump_dev_log(struct eeh_dev *edev, char *buf, size_t len) 165 { 166 struct pci_dn *pdn = eeh_dev_to_pdn(edev); 167 u32 cfg; 168 int cap, i; 169 int n = 0, l = 0; 170 char buffer[128]; 171 172 n += scnprintf(buf+n, len-n, "%04x:%02x:%02x.%01x\n", 173 edev->phb->global_number, pdn->busno, 174 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn)); 175 pr_warn("EEH: of node=%04x:%02x:%02x.%01x\n", 176 edev->phb->global_number, pdn->busno, 177 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn)); 178 179 eeh_ops->read_config(pdn, PCI_VENDOR_ID, 4, &cfg); 180 n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg); 181 pr_warn("EEH: PCI device/vendor: %08x\n", cfg); 182 183 eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cfg); 184 n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg); 185 pr_warn("EEH: PCI cmd/status register: %08x\n", cfg); 186 187 /* Gather bridge-specific registers */ 188 if (edev->mode & EEH_DEV_BRIDGE) { 189 eeh_ops->read_config(pdn, PCI_SEC_STATUS, 2, &cfg); 190 n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg); 191 pr_warn("EEH: Bridge secondary status: %04x\n", cfg); 192 193 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &cfg); 194 n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg); 195 pr_warn("EEH: Bridge control: %04x\n", cfg); 196 } 197 198 /* Dump out the PCI-X command and status regs */ 199 cap = edev->pcix_cap; 200 if (cap) { 201 eeh_ops->read_config(pdn, cap, 4, &cfg); 202 n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg); 203 pr_warn("EEH: PCI-X cmd: %08x\n", cfg); 204 205 eeh_ops->read_config(pdn, cap+4, 4, &cfg); 206 n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg); 207 pr_warn("EEH: PCI-X status: %08x\n", cfg); 208 } 209 210 /* If PCI-E capable, dump PCI-E cap 10 */ 211 cap = edev->pcie_cap; 212 if (cap) { 213 n += scnprintf(buf+n, len-n, "pci-e cap10:\n"); 214 pr_warn("EEH: PCI-E capabilities and status follow:\n"); 215 216 for (i=0; i<=8; i++) { 217 eeh_ops->read_config(pdn, cap+4*i, 4, &cfg); 218 n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); 219 220 if ((i % 4) == 0) { 221 if (i != 0) 222 pr_warn("%s\n", buffer); 223 224 l = scnprintf(buffer, sizeof(buffer), 225 "EEH: PCI-E %02x: %08x ", 226 4*i, cfg); 227 } else { 228 l += scnprintf(buffer+l, sizeof(buffer)-l, 229 "%08x ", cfg); 230 } 231 232 } 233 234 pr_warn("%s\n", buffer); 235 } 236 237 /* If AER capable, dump it */ 238 cap = edev->aer_cap; 239 if (cap) { 240 n += scnprintf(buf+n, len-n, "pci-e AER:\n"); 241 pr_warn("EEH: PCI-E AER capability register set follows:\n"); 242 243 for (i=0; i<=13; i++) { 244 eeh_ops->read_config(pdn, cap+4*i, 4, &cfg); 245 n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); 246 247 if ((i % 4) == 0) { 248 if (i != 0) 249 pr_warn("%s\n", buffer); 250 251 l = scnprintf(buffer, sizeof(buffer), 252 "EEH: PCI-E AER %02x: %08x ", 253 4*i, cfg); 254 } else { 255 l += scnprintf(buffer+l, sizeof(buffer)-l, 256 "%08x ", cfg); 257 } 258 } 259 260 pr_warn("%s\n", buffer); 261 } 262 263 return n; 264 } 265 266 static void *eeh_dump_pe_log(void *data, void *flag) 267 { 268 struct eeh_pe *pe = data; 269 struct eeh_dev *edev, *tmp; 270 size_t *plen = flag; 271 272 eeh_pe_for_each_dev(pe, edev, tmp) 273 *plen += eeh_dump_dev_log(edev, pci_regs_buf + *plen, 274 EEH_PCI_REGS_LOG_LEN - *plen); 275 276 return NULL; 277 } 278 279 /** 280 * eeh_slot_error_detail - Generate combined log including driver log and error log 281 * @pe: EEH PE 282 * @severity: temporary or permanent error log 283 * 284 * This routine should be called to generate the combined log, which 285 * is comprised of driver log and error log. The driver log is figured 286 * out from the config space of the corresponding PCI device, while 287 * the error log is fetched through platform dependent function call. 288 */ 289 void eeh_slot_error_detail(struct eeh_pe *pe, int severity) 290 { 291 size_t loglen = 0; 292 293 /* 294 * When the PHB is fenced or dead, it's pointless to collect 295 * the data from PCI config space because it should return 296 * 0xFF's. For ER, we still retrieve the data from the PCI 297 * config space. 298 * 299 * For pHyp, we have to enable IO for log retrieval. Otherwise, 300 * 0xFF's is always returned from PCI config space. 301 */ 302 if (!(pe->type & EEH_PE_PHB)) { 303 if (eeh_has_flag(EEH_ENABLE_IO_FOR_LOG)) 304 eeh_pci_enable(pe, EEH_OPT_THAW_MMIO); 305 306 /* 307 * The config space of some PCI devices can't be accessed 308 * when their PEs are in frozen state. Otherwise, fenced 309 * PHB might be seen. Those PEs are identified with flag 310 * EEH_PE_CFG_RESTRICTED, indicating EEH_PE_CFG_BLOCKED 311 * is set automatically when the PE is put to EEH_PE_ISOLATED. 312 * 313 * Restoring BARs possibly triggers PCI config access in 314 * (OPAL) firmware and then causes fenced PHB. If the 315 * PCI config is blocked with flag EEH_PE_CFG_BLOCKED, it's 316 * pointless to restore BARs and dump config space. 317 */ 318 eeh_ops->configure_bridge(pe); 319 if (!(pe->state & EEH_PE_CFG_BLOCKED)) { 320 eeh_pe_restore_bars(pe); 321 322 pci_regs_buf[0] = 0; 323 eeh_pe_traverse(pe, eeh_dump_pe_log, &loglen); 324 } 325 } 326 327 eeh_ops->get_log(pe, severity, pci_regs_buf, loglen); 328 } 329 330 /** 331 * eeh_token_to_phys - Convert EEH address token to phys address 332 * @token: I/O token, should be address in the form 0xA.... 333 * 334 * This routine should be called to convert virtual I/O address 335 * to physical one. 336 */ 337 static inline unsigned long eeh_token_to_phys(unsigned long token) 338 { 339 pte_t *ptep; 340 unsigned long pa; 341 int hugepage_shift; 342 343 /* 344 * We won't find hugepages here(this is iomem). Hence we are not 345 * worried about _PAGE_SPLITTING/collapse. Also we will not hit 346 * page table free, because of init_mm. 347 */ 348 ptep = __find_linux_pte_or_hugepte(init_mm.pgd, token, 349 NULL, &hugepage_shift); 350 if (!ptep) 351 return token; 352 WARN_ON(hugepage_shift); 353 pa = pte_pfn(*ptep) << PAGE_SHIFT; 354 355 return pa | (token & (PAGE_SIZE-1)); 356 } 357 358 /* 359 * On PowerNV platform, we might already have fenced PHB there. 360 * For that case, it's meaningless to recover frozen PE. Intead, 361 * We have to handle fenced PHB firstly. 362 */ 363 static int eeh_phb_check_failure(struct eeh_pe *pe) 364 { 365 struct eeh_pe *phb_pe; 366 unsigned long flags; 367 int ret; 368 369 if (!eeh_has_flag(EEH_PROBE_MODE_DEV)) 370 return -EPERM; 371 372 /* Find the PHB PE */ 373 phb_pe = eeh_phb_pe_get(pe->phb); 374 if (!phb_pe) { 375 pr_warn("%s Can't find PE for PHB#%d\n", 376 __func__, pe->phb->global_number); 377 return -EEXIST; 378 } 379 380 /* If the PHB has been in problematic state */ 381 eeh_serialize_lock(&flags); 382 if (phb_pe->state & EEH_PE_ISOLATED) { 383 ret = 0; 384 goto out; 385 } 386 387 /* Check PHB state */ 388 ret = eeh_ops->get_state(phb_pe, NULL); 389 if ((ret < 0) || 390 (ret == EEH_STATE_NOT_SUPPORT) || 391 (ret & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) == 392 (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) { 393 ret = 0; 394 goto out; 395 } 396 397 /* Isolate the PHB and send event */ 398 eeh_pe_state_mark(phb_pe, EEH_PE_ISOLATED); 399 eeh_serialize_unlock(flags); 400 401 pr_err("EEH: PHB#%x failure detected, location: %s\n", 402 phb_pe->phb->global_number, eeh_pe_loc_get(phb_pe)); 403 dump_stack(); 404 eeh_send_failure_event(phb_pe); 405 406 return 1; 407 out: 408 eeh_serialize_unlock(flags); 409 return ret; 410 } 411 412 /** 413 * eeh_dev_check_failure - Check if all 1's data is due to EEH slot freeze 414 * @edev: eeh device 415 * 416 * Check for an EEH failure for the given device node. Call this 417 * routine if the result of a read was all 0xff's and you want to 418 * find out if this is due to an EEH slot freeze. This routine 419 * will query firmware for the EEH status. 420 * 421 * Returns 0 if there has not been an EEH error; otherwise returns 422 * a non-zero value and queues up a slot isolation event notification. 423 * 424 * It is safe to call this routine in an interrupt context. 425 */ 426 int eeh_dev_check_failure(struct eeh_dev *edev) 427 { 428 int ret; 429 int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); 430 unsigned long flags; 431 struct pci_dn *pdn; 432 struct pci_dev *dev; 433 struct eeh_pe *pe, *parent_pe, *phb_pe; 434 int rc = 0; 435 const char *location = NULL; 436 437 eeh_stats.total_mmio_ffs++; 438 439 if (!eeh_enabled()) 440 return 0; 441 442 if (!edev) { 443 eeh_stats.no_dn++; 444 return 0; 445 } 446 dev = eeh_dev_to_pci_dev(edev); 447 pe = eeh_dev_to_pe(edev); 448 449 /* Access to IO BARs might get this far and still not want checking. */ 450 if (!pe) { 451 eeh_stats.ignored_check++; 452 pr_debug("EEH: Ignored check for %s\n", 453 eeh_pci_name(dev)); 454 return 0; 455 } 456 457 if (!pe->addr && !pe->config_addr) { 458 eeh_stats.no_cfg_addr++; 459 return 0; 460 } 461 462 /* 463 * On PowerNV platform, we might already have fenced PHB 464 * there and we need take care of that firstly. 465 */ 466 ret = eeh_phb_check_failure(pe); 467 if (ret > 0) 468 return ret; 469 470 /* 471 * If the PE isn't owned by us, we shouldn't check the 472 * state. Instead, let the owner handle it if the PE has 473 * been frozen. 474 */ 475 if (eeh_pe_passed(pe)) 476 return 0; 477 478 /* If we already have a pending isolation event for this 479 * slot, we know it's bad already, we don't need to check. 480 * Do this checking under a lock; as multiple PCI devices 481 * in one slot might report errors simultaneously, and we 482 * only want one error recovery routine running. 483 */ 484 eeh_serialize_lock(&flags); 485 rc = 1; 486 if (pe->state & EEH_PE_ISOLATED) { 487 pe->check_count++; 488 if (pe->check_count % EEH_MAX_FAILS == 0) { 489 pdn = eeh_dev_to_pdn(edev); 490 if (pdn->node) 491 location = of_get_property(pdn->node, "ibm,loc-code", NULL); 492 printk(KERN_ERR "EEH: %d reads ignored for recovering device at " 493 "location=%s driver=%s pci addr=%s\n", 494 pe->check_count, 495 location ? location : "unknown", 496 eeh_driver_name(dev), eeh_pci_name(dev)); 497 printk(KERN_ERR "EEH: Might be infinite loop in %s driver\n", 498 eeh_driver_name(dev)); 499 dump_stack(); 500 } 501 goto dn_unlock; 502 } 503 504 /* 505 * Now test for an EEH failure. This is VERY expensive. 506 * Note that the eeh_config_addr may be a parent device 507 * in the case of a device behind a bridge, or it may be 508 * function zero of a multi-function device. 509 * In any case they must share a common PHB. 510 */ 511 ret = eeh_ops->get_state(pe, NULL); 512 513 /* Note that config-io to empty slots may fail; 514 * they are empty when they don't have children. 515 * We will punt with the following conditions: Failure to get 516 * PE's state, EEH not support and Permanently unavailable 517 * state, PE is in good state. 518 */ 519 if ((ret < 0) || 520 (ret == EEH_STATE_NOT_SUPPORT) || 521 ((ret & active_flags) == active_flags)) { 522 eeh_stats.false_positives++; 523 pe->false_positives++; 524 rc = 0; 525 goto dn_unlock; 526 } 527 528 /* 529 * It should be corner case that the parent PE has been 530 * put into frozen state as well. We should take care 531 * that at first. 532 */ 533 parent_pe = pe->parent; 534 while (parent_pe) { 535 /* Hit the ceiling ? */ 536 if (parent_pe->type & EEH_PE_PHB) 537 break; 538 539 /* Frozen parent PE ? */ 540 ret = eeh_ops->get_state(parent_pe, NULL); 541 if (ret > 0 && 542 (ret & active_flags) != active_flags) 543 pe = parent_pe; 544 545 /* Next parent level */ 546 parent_pe = parent_pe->parent; 547 } 548 549 eeh_stats.slot_resets++; 550 551 /* Avoid repeated reports of this failure, including problems 552 * with other functions on this device, and functions under 553 * bridges. 554 */ 555 eeh_pe_state_mark(pe, EEH_PE_ISOLATED); 556 eeh_serialize_unlock(flags); 557 558 /* Most EEH events are due to device driver bugs. Having 559 * a stack trace will help the device-driver authors figure 560 * out what happened. So print that out. 561 */ 562 phb_pe = eeh_phb_pe_get(pe->phb); 563 pr_err("EEH: Frozen PHB#%x-PE#%x detected\n", 564 pe->phb->global_number, pe->addr); 565 pr_err("EEH: PE location: %s, PHB location: %s\n", 566 eeh_pe_loc_get(pe), eeh_pe_loc_get(phb_pe)); 567 dump_stack(); 568 569 eeh_send_failure_event(pe); 570 571 return 1; 572 573 dn_unlock: 574 eeh_serialize_unlock(flags); 575 return rc; 576 } 577 578 EXPORT_SYMBOL_GPL(eeh_dev_check_failure); 579 580 /** 581 * eeh_check_failure - Check if all 1's data is due to EEH slot freeze 582 * @token: I/O address 583 * 584 * Check for an EEH failure at the given I/O address. Call this 585 * routine if the result of a read was all 0xff's and you want to 586 * find out if this is due to an EEH slot freeze event. This routine 587 * will query firmware for the EEH status. 588 * 589 * Note this routine is safe to call in an interrupt context. 590 */ 591 int eeh_check_failure(const volatile void __iomem *token) 592 { 593 unsigned long addr; 594 struct eeh_dev *edev; 595 596 /* Finding the phys addr + pci device; this is pretty quick. */ 597 addr = eeh_token_to_phys((unsigned long __force) token); 598 edev = eeh_addr_cache_get_dev(addr); 599 if (!edev) { 600 eeh_stats.no_device++; 601 return 0; 602 } 603 604 return eeh_dev_check_failure(edev); 605 } 606 EXPORT_SYMBOL(eeh_check_failure); 607 608 609 /** 610 * eeh_pci_enable - Enable MMIO or DMA transfers for this slot 611 * @pe: EEH PE 612 * 613 * This routine should be called to reenable frozen MMIO or DMA 614 * so that it would work correctly again. It's useful while doing 615 * recovery or log collection on the indicated device. 616 */ 617 int eeh_pci_enable(struct eeh_pe *pe, int function) 618 { 619 int active_flag, rc; 620 621 /* 622 * pHyp doesn't allow to enable IO or DMA on unfrozen PE. 623 * Also, it's pointless to enable them on unfrozen PE. So 624 * we have to check before enabling IO or DMA. 625 */ 626 switch (function) { 627 case EEH_OPT_THAW_MMIO: 628 active_flag = EEH_STATE_MMIO_ACTIVE | EEH_STATE_MMIO_ENABLED; 629 break; 630 case EEH_OPT_THAW_DMA: 631 active_flag = EEH_STATE_DMA_ACTIVE; 632 break; 633 case EEH_OPT_DISABLE: 634 case EEH_OPT_ENABLE: 635 case EEH_OPT_FREEZE_PE: 636 active_flag = 0; 637 break; 638 default: 639 pr_warn("%s: Invalid function %d\n", 640 __func__, function); 641 return -EINVAL; 642 } 643 644 /* 645 * Check if IO or DMA has been enabled before 646 * enabling them. 647 */ 648 if (active_flag) { 649 rc = eeh_ops->get_state(pe, NULL); 650 if (rc < 0) 651 return rc; 652 653 /* Needn't enable it at all */ 654 if (rc == EEH_STATE_NOT_SUPPORT) 655 return 0; 656 657 /* It's already enabled */ 658 if (rc & active_flag) 659 return 0; 660 } 661 662 663 /* Issue the request */ 664 rc = eeh_ops->set_option(pe, function); 665 if (rc) 666 pr_warn("%s: Unexpected state change %d on " 667 "PHB#%d-PE#%x, err=%d\n", 668 __func__, function, pe->phb->global_number, 669 pe->addr, rc); 670 671 /* Check if the request is finished successfully */ 672 if (active_flag) { 673 rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC); 674 if (rc < 0) 675 return rc; 676 677 if (rc & active_flag) 678 return 0; 679 680 return -EIO; 681 } 682 683 return rc; 684 } 685 686 static void *eeh_disable_and_save_dev_state(void *data, void *userdata) 687 { 688 struct eeh_dev *edev = data; 689 struct pci_dev *pdev = eeh_dev_to_pci_dev(edev); 690 struct pci_dev *dev = userdata; 691 692 /* 693 * The caller should have disabled and saved the 694 * state for the specified device 695 */ 696 if (!pdev || pdev == dev) 697 return NULL; 698 699 /* Ensure we have D0 power state */ 700 pci_set_power_state(pdev, PCI_D0); 701 702 /* Save device state */ 703 pci_save_state(pdev); 704 705 /* 706 * Disable device to avoid any DMA traffic and 707 * interrupt from the device 708 */ 709 pci_write_config_word(pdev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); 710 711 return NULL; 712 } 713 714 static void *eeh_restore_dev_state(void *data, void *userdata) 715 { 716 struct eeh_dev *edev = data; 717 struct pci_dn *pdn = eeh_dev_to_pdn(edev); 718 struct pci_dev *pdev = eeh_dev_to_pci_dev(edev); 719 struct pci_dev *dev = userdata; 720 721 if (!pdev) 722 return NULL; 723 724 /* Apply customization from firmware */ 725 if (pdn && eeh_ops->restore_config) 726 eeh_ops->restore_config(pdn); 727 728 /* The caller should restore state for the specified device */ 729 if (pdev != dev) 730 pci_restore_state(pdev); 731 732 return NULL; 733 } 734 735 /** 736 * pcibios_set_pcie_reset_state - Set PCI-E reset state 737 * @dev: pci device struct 738 * @state: reset state to enter 739 * 740 * Return value: 741 * 0 if success 742 */ 743 int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) 744 { 745 struct eeh_dev *edev = pci_dev_to_eeh_dev(dev); 746 struct eeh_pe *pe = eeh_dev_to_pe(edev); 747 748 if (!pe) { 749 pr_err("%s: No PE found on PCI device %s\n", 750 __func__, pci_name(dev)); 751 return -EINVAL; 752 } 753 754 switch (state) { 755 case pcie_deassert_reset: 756 eeh_ops->reset(pe, EEH_RESET_DEACTIVATE); 757 eeh_unfreeze_pe(pe, false); 758 if (!(pe->type & EEH_PE_VF)) 759 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED); 760 eeh_pe_dev_traverse(pe, eeh_restore_dev_state, dev); 761 eeh_pe_state_clear(pe, EEH_PE_ISOLATED); 762 break; 763 case pcie_hot_reset: 764 eeh_pe_state_mark_with_cfg(pe, EEH_PE_ISOLATED); 765 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE); 766 eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev); 767 if (!(pe->type & EEH_PE_VF)) 768 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED); 769 eeh_ops->reset(pe, EEH_RESET_HOT); 770 break; 771 case pcie_warm_reset: 772 eeh_pe_state_mark_with_cfg(pe, EEH_PE_ISOLATED); 773 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE); 774 eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev); 775 if (!(pe->type & EEH_PE_VF)) 776 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED); 777 eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL); 778 break; 779 default: 780 eeh_pe_state_clear(pe, EEH_PE_ISOLATED | EEH_PE_CFG_BLOCKED); 781 return -EINVAL; 782 }; 783 784 return 0; 785 } 786 787 /** 788 * eeh_set_pe_freset - Check the required reset for the indicated device 789 * @data: EEH device 790 * @flag: return value 791 * 792 * Each device might have its preferred reset type: fundamental or 793 * hot reset. The routine is used to collected the information for 794 * the indicated device and its children so that the bunch of the 795 * devices could be reset properly. 796 */ 797 static void *eeh_set_dev_freset(void *data, void *flag) 798 { 799 struct pci_dev *dev; 800 unsigned int *freset = (unsigned int *)flag; 801 struct eeh_dev *edev = (struct eeh_dev *)data; 802 803 dev = eeh_dev_to_pci_dev(edev); 804 if (dev) 805 *freset |= dev->needs_freset; 806 807 return NULL; 808 } 809 810 /** 811 * eeh_reset_pe_once - Assert the pci #RST line for 1/4 second 812 * @pe: EEH PE 813 * 814 * Assert the PCI #RST line for 1/4 second. 815 */ 816 static void eeh_reset_pe_once(struct eeh_pe *pe) 817 { 818 unsigned int freset = 0; 819 820 /* Determine type of EEH reset required for 821 * Partitionable Endpoint, a hot-reset (1) 822 * or a fundamental reset (3). 823 * A fundamental reset required by any device under 824 * Partitionable Endpoint trumps hot-reset. 825 */ 826 eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset); 827 828 if (freset) 829 eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL); 830 else 831 eeh_ops->reset(pe, EEH_RESET_HOT); 832 833 eeh_ops->reset(pe, EEH_RESET_DEACTIVATE); 834 } 835 836 /** 837 * eeh_reset_pe - Reset the indicated PE 838 * @pe: EEH PE 839 * 840 * This routine should be called to reset indicated device, including 841 * PE. A PE might include multiple PCI devices and sometimes PCI bridges 842 * might be involved as well. 843 */ 844 int eeh_reset_pe(struct eeh_pe *pe) 845 { 846 int flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); 847 int i, state, ret; 848 849 /* Mark as reset and block config space */ 850 eeh_pe_state_mark(pe, EEH_PE_RESET | EEH_PE_CFG_BLOCKED); 851 852 /* Take three shots at resetting the bus */ 853 for (i = 0; i < 3; i++) { 854 eeh_reset_pe_once(pe); 855 856 /* 857 * EEH_PE_ISOLATED is expected to be removed after 858 * BAR restore. 859 */ 860 state = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC); 861 if ((state & flags) == flags) { 862 ret = 0; 863 goto out; 864 } 865 866 if (state < 0) { 867 pr_warn("%s: Unrecoverable slot failure on PHB#%d-PE#%x", 868 __func__, pe->phb->global_number, pe->addr); 869 ret = -ENOTRECOVERABLE; 870 goto out; 871 } 872 873 /* We might run out of credits */ 874 ret = -EIO; 875 pr_warn("%s: Failure %d resetting PHB#%x-PE#%x\n (%d)\n", 876 __func__, state, pe->phb->global_number, pe->addr, (i + 1)); 877 } 878 879 out: 880 eeh_pe_state_clear(pe, EEH_PE_RESET | EEH_PE_CFG_BLOCKED); 881 return ret; 882 } 883 884 /** 885 * eeh_save_bars - Save device bars 886 * @edev: PCI device associated EEH device 887 * 888 * Save the values of the device bars. Unlike the restore 889 * routine, this routine is *not* recursive. This is because 890 * PCI devices are added individually; but, for the restore, 891 * an entire slot is reset at a time. 892 */ 893 void eeh_save_bars(struct eeh_dev *edev) 894 { 895 struct pci_dn *pdn; 896 int i; 897 898 pdn = eeh_dev_to_pdn(edev); 899 if (!pdn) 900 return; 901 902 for (i = 0; i < 16; i++) 903 eeh_ops->read_config(pdn, i * 4, 4, &edev->config_space[i]); 904 905 /* 906 * For PCI bridges including root port, we need enable bus 907 * master explicitly. Otherwise, it can't fetch IODA table 908 * entries correctly. So we cache the bit in advance so that 909 * we can restore it after reset, either PHB range or PE range. 910 */ 911 if (edev->mode & EEH_DEV_BRIDGE) 912 edev->config_space[1] |= PCI_COMMAND_MASTER; 913 } 914 915 /** 916 * eeh_ops_register - Register platform dependent EEH operations 917 * @ops: platform dependent EEH operations 918 * 919 * Register the platform dependent EEH operation callback 920 * functions. The platform should call this function before 921 * any other EEH operations. 922 */ 923 int __init eeh_ops_register(struct eeh_ops *ops) 924 { 925 if (!ops->name) { 926 pr_warn("%s: Invalid EEH ops name for %p\n", 927 __func__, ops); 928 return -EINVAL; 929 } 930 931 if (eeh_ops && eeh_ops != ops) { 932 pr_warn("%s: EEH ops of platform %s already existing (%s)\n", 933 __func__, eeh_ops->name, ops->name); 934 return -EEXIST; 935 } 936 937 eeh_ops = ops; 938 939 return 0; 940 } 941 942 /** 943 * eeh_ops_unregister - Unreigster platform dependent EEH operations 944 * @name: name of EEH platform operations 945 * 946 * Unregister the platform dependent EEH operation callback 947 * functions. 948 */ 949 int __exit eeh_ops_unregister(const char *name) 950 { 951 if (!name || !strlen(name)) { 952 pr_warn("%s: Invalid EEH ops name\n", 953 __func__); 954 return -EINVAL; 955 } 956 957 if (eeh_ops && !strcmp(eeh_ops->name, name)) { 958 eeh_ops = NULL; 959 return 0; 960 } 961 962 return -EEXIST; 963 } 964 965 static int eeh_reboot_notifier(struct notifier_block *nb, 966 unsigned long action, void *unused) 967 { 968 eeh_clear_flag(EEH_ENABLED); 969 return NOTIFY_DONE; 970 } 971 972 static struct notifier_block eeh_reboot_nb = { 973 .notifier_call = eeh_reboot_notifier, 974 }; 975 976 /** 977 * eeh_init - EEH initialization 978 * 979 * Initialize EEH by trying to enable it for all of the adapters in the system. 980 * As a side effect we can determine here if eeh is supported at all. 981 * Note that we leave EEH on so failed config cycles won't cause a machine 982 * check. If a user turns off EEH for a particular adapter they are really 983 * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't 984 * grant access to a slot if EEH isn't enabled, and so we always enable 985 * EEH for all slots/all devices. 986 * 987 * The eeh-force-off option disables EEH checking globally, for all slots. 988 * Even if force-off is set, the EEH hardware is still enabled, so that 989 * newer systems can boot. 990 */ 991 int eeh_init(void) 992 { 993 struct pci_controller *hose, *tmp; 994 struct pci_dn *pdn; 995 static int cnt = 0; 996 int ret = 0; 997 998 /* 999 * We have to delay the initialization on PowerNV after 1000 * the PCI hierarchy tree has been built because the PEs 1001 * are figured out based on PCI devices instead of device 1002 * tree nodes 1003 */ 1004 if (machine_is(powernv) && cnt++ <= 0) 1005 return ret; 1006 1007 /* Register reboot notifier */ 1008 ret = register_reboot_notifier(&eeh_reboot_nb); 1009 if (ret) { 1010 pr_warn("%s: Failed to register notifier (%d)\n", 1011 __func__, ret); 1012 return ret; 1013 } 1014 1015 /* call platform initialization function */ 1016 if (!eeh_ops) { 1017 pr_warn("%s: Platform EEH operation not found\n", 1018 __func__); 1019 return -EEXIST; 1020 } else if ((ret = eeh_ops->init())) 1021 return ret; 1022 1023 /* Initialize EEH event */ 1024 ret = eeh_event_init(); 1025 if (ret) 1026 return ret; 1027 1028 /* Enable EEH for all adapters */ 1029 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1030 pdn = hose->pci_data; 1031 traverse_pci_dn(pdn, eeh_ops->probe, NULL); 1032 } 1033 1034 /* 1035 * Call platform post-initialization. Actually, It's good chance 1036 * to inform platform that EEH is ready to supply service if the 1037 * I/O cache stuff has been built up. 1038 */ 1039 if (eeh_ops->post_init) { 1040 ret = eeh_ops->post_init(); 1041 if (ret) 1042 return ret; 1043 } 1044 1045 if (eeh_enabled()) 1046 pr_info("EEH: PCI Enhanced I/O Error Handling Enabled\n"); 1047 else 1048 pr_info("EEH: No capable adapters found\n"); 1049 1050 return ret; 1051 } 1052 1053 core_initcall_sync(eeh_init); 1054 1055 /** 1056 * eeh_add_device_early - Enable EEH for the indicated device node 1057 * @pdn: PCI device node for which to set up EEH 1058 * 1059 * This routine must be used to perform EEH initialization for PCI 1060 * devices that were added after system boot (e.g. hotplug, dlpar). 1061 * This routine must be called before any i/o is performed to the 1062 * adapter (inluding any config-space i/o). 1063 * Whether this actually enables EEH or not for this device depends 1064 * on the CEC architecture, type of the device, on earlier boot 1065 * command-line arguments & etc. 1066 */ 1067 void eeh_add_device_early(struct pci_dn *pdn) 1068 { 1069 struct pci_controller *phb; 1070 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1071 1072 if (!edev) 1073 return; 1074 1075 if (!eeh_has_flag(EEH_PROBE_MODE_DEVTREE)) 1076 return; 1077 1078 /* USB Bus children of PCI devices will not have BUID's */ 1079 phb = edev->phb; 1080 if (NULL == phb || 1081 (eeh_has_flag(EEH_PROBE_MODE_DEVTREE) && 0 == phb->buid)) 1082 return; 1083 1084 eeh_ops->probe(pdn, NULL); 1085 } 1086 1087 /** 1088 * eeh_add_device_tree_early - Enable EEH for the indicated device 1089 * @pdn: PCI device node 1090 * 1091 * This routine must be used to perform EEH initialization for the 1092 * indicated PCI device that was added after system boot (e.g. 1093 * hotplug, dlpar). 1094 */ 1095 void eeh_add_device_tree_early(struct pci_dn *pdn) 1096 { 1097 struct pci_dn *n; 1098 1099 if (!pdn) 1100 return; 1101 1102 list_for_each_entry(n, &pdn->child_list, list) 1103 eeh_add_device_tree_early(n); 1104 eeh_add_device_early(pdn); 1105 } 1106 EXPORT_SYMBOL_GPL(eeh_add_device_tree_early); 1107 1108 /** 1109 * eeh_add_device_late - Perform EEH initialization for the indicated pci device 1110 * @dev: pci device for which to set up EEH 1111 * 1112 * This routine must be used to complete EEH initialization for PCI 1113 * devices that were added after system boot (e.g. hotplug, dlpar). 1114 */ 1115 void eeh_add_device_late(struct pci_dev *dev) 1116 { 1117 struct pci_dn *pdn; 1118 struct eeh_dev *edev; 1119 1120 if (!dev || !eeh_enabled()) 1121 return; 1122 1123 pr_debug("EEH: Adding device %s\n", pci_name(dev)); 1124 1125 pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); 1126 edev = pdn_to_eeh_dev(pdn); 1127 if (edev->pdev == dev) { 1128 pr_debug("EEH: Already referenced !\n"); 1129 return; 1130 } 1131 1132 /* 1133 * The EEH cache might not be removed correctly because of 1134 * unbalanced kref to the device during unplug time, which 1135 * relies on pcibios_release_device(). So we have to remove 1136 * that here explicitly. 1137 */ 1138 if (edev->pdev) { 1139 eeh_rmv_from_parent_pe(edev); 1140 eeh_addr_cache_rmv_dev(edev->pdev); 1141 eeh_sysfs_remove_device(edev->pdev); 1142 edev->mode &= ~EEH_DEV_SYSFS; 1143 1144 /* 1145 * We definitely should have the PCI device removed 1146 * though it wasn't correctly. So we needn't call 1147 * into error handler afterwards. 1148 */ 1149 edev->mode |= EEH_DEV_NO_HANDLER; 1150 1151 edev->pdev = NULL; 1152 dev->dev.archdata.edev = NULL; 1153 } 1154 1155 if (eeh_has_flag(EEH_PROBE_MODE_DEV)) 1156 eeh_ops->probe(pdn, NULL); 1157 1158 edev->pdev = dev; 1159 dev->dev.archdata.edev = edev; 1160 1161 eeh_addr_cache_insert_dev(dev); 1162 } 1163 1164 /** 1165 * eeh_add_device_tree_late - Perform EEH initialization for the indicated PCI bus 1166 * @bus: PCI bus 1167 * 1168 * This routine must be used to perform EEH initialization for PCI 1169 * devices which are attached to the indicated PCI bus. The PCI bus 1170 * is added after system boot through hotplug or dlpar. 1171 */ 1172 void eeh_add_device_tree_late(struct pci_bus *bus) 1173 { 1174 struct pci_dev *dev; 1175 1176 list_for_each_entry(dev, &bus->devices, bus_list) { 1177 eeh_add_device_late(dev); 1178 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 1179 struct pci_bus *subbus = dev->subordinate; 1180 if (subbus) 1181 eeh_add_device_tree_late(subbus); 1182 } 1183 } 1184 } 1185 EXPORT_SYMBOL_GPL(eeh_add_device_tree_late); 1186 1187 /** 1188 * eeh_add_sysfs_files - Add EEH sysfs files for the indicated PCI bus 1189 * @bus: PCI bus 1190 * 1191 * This routine must be used to add EEH sysfs files for PCI 1192 * devices which are attached to the indicated PCI bus. The PCI bus 1193 * is added after system boot through hotplug or dlpar. 1194 */ 1195 void eeh_add_sysfs_files(struct pci_bus *bus) 1196 { 1197 struct pci_dev *dev; 1198 1199 list_for_each_entry(dev, &bus->devices, bus_list) { 1200 eeh_sysfs_add_device(dev); 1201 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 1202 struct pci_bus *subbus = dev->subordinate; 1203 if (subbus) 1204 eeh_add_sysfs_files(subbus); 1205 } 1206 } 1207 } 1208 EXPORT_SYMBOL_GPL(eeh_add_sysfs_files); 1209 1210 /** 1211 * eeh_remove_device - Undo EEH setup for the indicated pci device 1212 * @dev: pci device to be removed 1213 * 1214 * This routine should be called when a device is removed from 1215 * a running system (e.g. by hotplug or dlpar). It unregisters 1216 * the PCI device from the EEH subsystem. I/O errors affecting 1217 * this device will no longer be detected after this call; thus, 1218 * i/o errors affecting this slot may leave this device unusable. 1219 */ 1220 void eeh_remove_device(struct pci_dev *dev) 1221 { 1222 struct eeh_dev *edev; 1223 1224 if (!dev || !eeh_enabled()) 1225 return; 1226 edev = pci_dev_to_eeh_dev(dev); 1227 1228 /* Unregister the device with the EEH/PCI address search system */ 1229 pr_debug("EEH: Removing device %s\n", pci_name(dev)); 1230 1231 if (!edev || !edev->pdev || !edev->pe) { 1232 pr_debug("EEH: Not referenced !\n"); 1233 return; 1234 } 1235 1236 /* 1237 * During the hotplug for EEH error recovery, we need the EEH 1238 * device attached to the parent PE in order for BAR restore 1239 * a bit later. So we keep it for BAR restore and remove it 1240 * from the parent PE during the BAR resotre. 1241 */ 1242 edev->pdev = NULL; 1243 1244 /* 1245 * The flag "in_error" is used to trace EEH devices for VFs 1246 * in error state or not. It's set in eeh_report_error(). If 1247 * it's not set, eeh_report_{reset,resume}() won't be called 1248 * for the VF EEH device. 1249 */ 1250 edev->in_error = false; 1251 dev->dev.archdata.edev = NULL; 1252 if (!(edev->pe->state & EEH_PE_KEEP)) 1253 eeh_rmv_from_parent_pe(edev); 1254 else 1255 edev->mode |= EEH_DEV_DISCONNECTED; 1256 1257 /* 1258 * We're removing from the PCI subsystem, that means 1259 * the PCI device driver can't support EEH or not 1260 * well. So we rely on hotplug completely to do recovery 1261 * for the specific PCI device. 1262 */ 1263 edev->mode |= EEH_DEV_NO_HANDLER; 1264 1265 eeh_addr_cache_rmv_dev(dev); 1266 eeh_sysfs_remove_device(dev); 1267 edev->mode &= ~EEH_DEV_SYSFS; 1268 } 1269 1270 int eeh_unfreeze_pe(struct eeh_pe *pe, bool sw_state) 1271 { 1272 int ret; 1273 1274 ret = eeh_pci_enable(pe, EEH_OPT_THAW_MMIO); 1275 if (ret) { 1276 pr_warn("%s: Failure %d enabling IO on PHB#%x-PE#%x\n", 1277 __func__, ret, pe->phb->global_number, pe->addr); 1278 return ret; 1279 } 1280 1281 ret = eeh_pci_enable(pe, EEH_OPT_THAW_DMA); 1282 if (ret) { 1283 pr_warn("%s: Failure %d enabling DMA on PHB#%x-PE#%x\n", 1284 __func__, ret, pe->phb->global_number, pe->addr); 1285 return ret; 1286 } 1287 1288 /* Clear software isolated state */ 1289 if (sw_state && (pe->state & EEH_PE_ISOLATED)) 1290 eeh_pe_state_clear(pe, EEH_PE_ISOLATED); 1291 1292 return ret; 1293 } 1294 1295 1296 static struct pci_device_id eeh_reset_ids[] = { 1297 { PCI_DEVICE(0x19a2, 0x0710) }, /* Emulex, BE */ 1298 { PCI_DEVICE(0x10df, 0xe220) }, /* Emulex, Lancer */ 1299 { PCI_DEVICE(0x14e4, 0x1657) }, /* Broadcom BCM5719 */ 1300 { 0 } 1301 }; 1302 1303 static int eeh_pe_change_owner(struct eeh_pe *pe) 1304 { 1305 struct eeh_dev *edev, *tmp; 1306 struct pci_dev *pdev; 1307 struct pci_device_id *id; 1308 int flags, ret; 1309 1310 /* Check PE state */ 1311 flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); 1312 ret = eeh_ops->get_state(pe, NULL); 1313 if (ret < 0 || ret == EEH_STATE_NOT_SUPPORT) 1314 return 0; 1315 1316 /* Unfrozen PE, nothing to do */ 1317 if ((ret & flags) == flags) 1318 return 0; 1319 1320 /* Frozen PE, check if it needs PE level reset */ 1321 eeh_pe_for_each_dev(pe, edev, tmp) { 1322 pdev = eeh_dev_to_pci_dev(edev); 1323 if (!pdev) 1324 continue; 1325 1326 for (id = &eeh_reset_ids[0]; id->vendor != 0; id++) { 1327 if (id->vendor != PCI_ANY_ID && 1328 id->vendor != pdev->vendor) 1329 continue; 1330 if (id->device != PCI_ANY_ID && 1331 id->device != pdev->device) 1332 continue; 1333 if (id->subvendor != PCI_ANY_ID && 1334 id->subvendor != pdev->subsystem_vendor) 1335 continue; 1336 if (id->subdevice != PCI_ANY_ID && 1337 id->subdevice != pdev->subsystem_device) 1338 continue; 1339 1340 return eeh_pe_reset_and_recover(pe); 1341 } 1342 } 1343 1344 return eeh_unfreeze_pe(pe, true); 1345 } 1346 1347 /** 1348 * eeh_dev_open - Increase count of pass through devices for PE 1349 * @pdev: PCI device 1350 * 1351 * Increase count of passed through devices for the indicated 1352 * PE. In the result, the EEH errors detected on the PE won't be 1353 * reported. The PE owner will be responsible for detection 1354 * and recovery. 1355 */ 1356 int eeh_dev_open(struct pci_dev *pdev) 1357 { 1358 struct eeh_dev *edev; 1359 int ret = -ENODEV; 1360 1361 mutex_lock(&eeh_dev_mutex); 1362 1363 /* No PCI device ? */ 1364 if (!pdev) 1365 goto out; 1366 1367 /* No EEH device or PE ? */ 1368 edev = pci_dev_to_eeh_dev(pdev); 1369 if (!edev || !edev->pe) 1370 goto out; 1371 1372 /* 1373 * The PE might have been put into frozen state, but we 1374 * didn't detect that yet. The passed through PCI devices 1375 * in frozen PE won't work properly. Clear the frozen state 1376 * in advance. 1377 */ 1378 ret = eeh_pe_change_owner(edev->pe); 1379 if (ret) 1380 goto out; 1381 1382 /* Increase PE's pass through count */ 1383 atomic_inc(&edev->pe->pass_dev_cnt); 1384 mutex_unlock(&eeh_dev_mutex); 1385 1386 return 0; 1387 out: 1388 mutex_unlock(&eeh_dev_mutex); 1389 return ret; 1390 } 1391 EXPORT_SYMBOL_GPL(eeh_dev_open); 1392 1393 /** 1394 * eeh_dev_release - Decrease count of pass through devices for PE 1395 * @pdev: PCI device 1396 * 1397 * Decrease count of pass through devices for the indicated PE. If 1398 * there is no passed through device in PE, the EEH errors detected 1399 * on the PE will be reported and handled as usual. 1400 */ 1401 void eeh_dev_release(struct pci_dev *pdev) 1402 { 1403 struct eeh_dev *edev; 1404 1405 mutex_lock(&eeh_dev_mutex); 1406 1407 /* No PCI device ? */ 1408 if (!pdev) 1409 goto out; 1410 1411 /* No EEH device ? */ 1412 edev = pci_dev_to_eeh_dev(pdev); 1413 if (!edev || !edev->pe || !eeh_pe_passed(edev->pe)) 1414 goto out; 1415 1416 /* Decrease PE's pass through count */ 1417 WARN_ON(atomic_dec_if_positive(&edev->pe->pass_dev_cnt) < 0); 1418 eeh_pe_change_owner(edev->pe); 1419 out: 1420 mutex_unlock(&eeh_dev_mutex); 1421 } 1422 EXPORT_SYMBOL(eeh_dev_release); 1423 1424 #ifdef CONFIG_IOMMU_API 1425 1426 static int dev_has_iommu_table(struct device *dev, void *data) 1427 { 1428 struct pci_dev *pdev = to_pci_dev(dev); 1429 struct pci_dev **ppdev = data; 1430 1431 if (!dev) 1432 return 0; 1433 1434 if (dev->iommu_group) { 1435 *ppdev = pdev; 1436 return 1; 1437 } 1438 1439 return 0; 1440 } 1441 1442 /** 1443 * eeh_iommu_group_to_pe - Convert IOMMU group to EEH PE 1444 * @group: IOMMU group 1445 * 1446 * The routine is called to convert IOMMU group to EEH PE. 1447 */ 1448 struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group) 1449 { 1450 struct pci_dev *pdev = NULL; 1451 struct eeh_dev *edev; 1452 int ret; 1453 1454 /* No IOMMU group ? */ 1455 if (!group) 1456 return NULL; 1457 1458 ret = iommu_group_for_each_dev(group, &pdev, dev_has_iommu_table); 1459 if (!ret || !pdev) 1460 return NULL; 1461 1462 /* No EEH device or PE ? */ 1463 edev = pci_dev_to_eeh_dev(pdev); 1464 if (!edev || !edev->pe) 1465 return NULL; 1466 1467 return edev->pe; 1468 } 1469 EXPORT_SYMBOL_GPL(eeh_iommu_group_to_pe); 1470 1471 #endif /* CONFIG_IOMMU_API */ 1472 1473 /** 1474 * eeh_pe_set_option - Set options for the indicated PE 1475 * @pe: EEH PE 1476 * @option: requested option 1477 * 1478 * The routine is called to enable or disable EEH functionality 1479 * on the indicated PE, to enable IO or DMA for the frozen PE. 1480 */ 1481 int eeh_pe_set_option(struct eeh_pe *pe, int option) 1482 { 1483 int ret = 0; 1484 1485 /* Invalid PE ? */ 1486 if (!pe) 1487 return -ENODEV; 1488 1489 /* 1490 * EEH functionality could possibly be disabled, just 1491 * return error for the case. And the EEH functinality 1492 * isn't expected to be disabled on one specific PE. 1493 */ 1494 switch (option) { 1495 case EEH_OPT_ENABLE: 1496 if (eeh_enabled()) { 1497 ret = eeh_pe_change_owner(pe); 1498 break; 1499 } 1500 ret = -EIO; 1501 break; 1502 case EEH_OPT_DISABLE: 1503 break; 1504 case EEH_OPT_THAW_MMIO: 1505 case EEH_OPT_THAW_DMA: 1506 case EEH_OPT_FREEZE_PE: 1507 if (!eeh_ops || !eeh_ops->set_option) { 1508 ret = -ENOENT; 1509 break; 1510 } 1511 1512 ret = eeh_pci_enable(pe, option); 1513 break; 1514 default: 1515 pr_debug("%s: Option %d out of range (%d, %d)\n", 1516 __func__, option, EEH_OPT_DISABLE, EEH_OPT_THAW_DMA); 1517 ret = -EINVAL; 1518 } 1519 1520 return ret; 1521 } 1522 EXPORT_SYMBOL_GPL(eeh_pe_set_option); 1523 1524 /** 1525 * eeh_pe_get_state - Retrieve PE's state 1526 * @pe: EEH PE 1527 * 1528 * Retrieve the PE's state, which includes 3 aspects: enabled 1529 * DMA, enabled IO and asserted reset. 1530 */ 1531 int eeh_pe_get_state(struct eeh_pe *pe) 1532 { 1533 int result, ret = 0; 1534 bool rst_active, dma_en, mmio_en; 1535 1536 /* Existing PE ? */ 1537 if (!pe) 1538 return -ENODEV; 1539 1540 if (!eeh_ops || !eeh_ops->get_state) 1541 return -ENOENT; 1542 1543 /* 1544 * If the parent PE is owned by the host kernel and is undergoing 1545 * error recovery, we should return the PE state as temporarily 1546 * unavailable so that the error recovery on the guest is suspended 1547 * until the recovery completes on the host. 1548 */ 1549 if (pe->parent && 1550 !(pe->state & EEH_PE_REMOVED) && 1551 (pe->parent->state & (EEH_PE_ISOLATED | EEH_PE_RECOVERING))) 1552 return EEH_PE_STATE_UNAVAIL; 1553 1554 result = eeh_ops->get_state(pe, NULL); 1555 rst_active = !!(result & EEH_STATE_RESET_ACTIVE); 1556 dma_en = !!(result & EEH_STATE_DMA_ENABLED); 1557 mmio_en = !!(result & EEH_STATE_MMIO_ENABLED); 1558 1559 if (rst_active) 1560 ret = EEH_PE_STATE_RESET; 1561 else if (dma_en && mmio_en) 1562 ret = EEH_PE_STATE_NORMAL; 1563 else if (!dma_en && !mmio_en) 1564 ret = EEH_PE_STATE_STOPPED_IO_DMA; 1565 else if (!dma_en && mmio_en) 1566 ret = EEH_PE_STATE_STOPPED_DMA; 1567 else 1568 ret = EEH_PE_STATE_UNAVAIL; 1569 1570 return ret; 1571 } 1572 EXPORT_SYMBOL_GPL(eeh_pe_get_state); 1573 1574 static int eeh_pe_reenable_devices(struct eeh_pe *pe) 1575 { 1576 struct eeh_dev *edev, *tmp; 1577 struct pci_dev *pdev; 1578 int ret = 0; 1579 1580 /* Restore config space */ 1581 eeh_pe_restore_bars(pe); 1582 1583 /* 1584 * Reenable PCI devices as the devices passed 1585 * through are always enabled before the reset. 1586 */ 1587 eeh_pe_for_each_dev(pe, edev, tmp) { 1588 pdev = eeh_dev_to_pci_dev(edev); 1589 if (!pdev) 1590 continue; 1591 1592 ret = pci_reenable_device(pdev); 1593 if (ret) { 1594 pr_warn("%s: Failure %d reenabling %s\n", 1595 __func__, ret, pci_name(pdev)); 1596 return ret; 1597 } 1598 } 1599 1600 /* The PE is still in frozen state */ 1601 return eeh_unfreeze_pe(pe, true); 1602 } 1603 1604 /** 1605 * eeh_pe_reset - Issue PE reset according to specified type 1606 * @pe: EEH PE 1607 * @option: reset type 1608 * 1609 * The routine is called to reset the specified PE with the 1610 * indicated type, either fundamental reset or hot reset. 1611 * PE reset is the most important part for error recovery. 1612 */ 1613 int eeh_pe_reset(struct eeh_pe *pe, int option) 1614 { 1615 int ret = 0; 1616 1617 /* Invalid PE ? */ 1618 if (!pe) 1619 return -ENODEV; 1620 1621 if (!eeh_ops || !eeh_ops->set_option || !eeh_ops->reset) 1622 return -ENOENT; 1623 1624 switch (option) { 1625 case EEH_RESET_DEACTIVATE: 1626 ret = eeh_ops->reset(pe, option); 1627 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED); 1628 if (ret) 1629 break; 1630 1631 ret = eeh_pe_reenable_devices(pe); 1632 break; 1633 case EEH_RESET_HOT: 1634 case EEH_RESET_FUNDAMENTAL: 1635 /* 1636 * Proactively freeze the PE to drop all MMIO access 1637 * during reset, which should be banned as it's always 1638 * cause recursive EEH error. 1639 */ 1640 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE); 1641 1642 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED); 1643 ret = eeh_ops->reset(pe, option); 1644 break; 1645 default: 1646 pr_debug("%s: Unsupported option %d\n", 1647 __func__, option); 1648 ret = -EINVAL; 1649 } 1650 1651 return ret; 1652 } 1653 EXPORT_SYMBOL_GPL(eeh_pe_reset); 1654 1655 /** 1656 * eeh_pe_configure - Configure PCI bridges after PE reset 1657 * @pe: EEH PE 1658 * 1659 * The routine is called to restore the PCI config space for 1660 * those PCI devices, especially PCI bridges affected by PE 1661 * reset issued previously. 1662 */ 1663 int eeh_pe_configure(struct eeh_pe *pe) 1664 { 1665 int ret = 0; 1666 1667 /* Invalid PE ? */ 1668 if (!pe) 1669 return -ENODEV; 1670 1671 return ret; 1672 } 1673 EXPORT_SYMBOL_GPL(eeh_pe_configure); 1674 1675 /** 1676 * eeh_pe_inject_err - Injecting the specified PCI error to the indicated PE 1677 * @pe: the indicated PE 1678 * @type: error type 1679 * @function: error function 1680 * @addr: address 1681 * @mask: address mask 1682 * 1683 * The routine is called to inject the specified PCI error, which 1684 * is determined by @type and @function, to the indicated PE for 1685 * testing purpose. 1686 */ 1687 int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func, 1688 unsigned long addr, unsigned long mask) 1689 { 1690 /* Invalid PE ? */ 1691 if (!pe) 1692 return -ENODEV; 1693 1694 /* Unsupported operation ? */ 1695 if (!eeh_ops || !eeh_ops->err_inject) 1696 return -ENOENT; 1697 1698 /* Check on PCI error type */ 1699 if (type != EEH_ERR_TYPE_32 && type != EEH_ERR_TYPE_64) 1700 return -EINVAL; 1701 1702 /* Check on PCI error function */ 1703 if (func < EEH_ERR_FUNC_MIN || func > EEH_ERR_FUNC_MAX) 1704 return -EINVAL; 1705 1706 return eeh_ops->err_inject(pe, type, func, addr, mask); 1707 } 1708 EXPORT_SYMBOL_GPL(eeh_pe_inject_err); 1709 1710 static int proc_eeh_show(struct seq_file *m, void *v) 1711 { 1712 if (!eeh_enabled()) { 1713 seq_printf(m, "EEH Subsystem is globally disabled\n"); 1714 seq_printf(m, "eeh_total_mmio_ffs=%llu\n", eeh_stats.total_mmio_ffs); 1715 } else { 1716 seq_printf(m, "EEH Subsystem is enabled\n"); 1717 seq_printf(m, 1718 "no device=%llu\n" 1719 "no device node=%llu\n" 1720 "no config address=%llu\n" 1721 "check not wanted=%llu\n" 1722 "eeh_total_mmio_ffs=%llu\n" 1723 "eeh_false_positives=%llu\n" 1724 "eeh_slot_resets=%llu\n", 1725 eeh_stats.no_device, 1726 eeh_stats.no_dn, 1727 eeh_stats.no_cfg_addr, 1728 eeh_stats.ignored_check, 1729 eeh_stats.total_mmio_ffs, 1730 eeh_stats.false_positives, 1731 eeh_stats.slot_resets); 1732 } 1733 1734 return 0; 1735 } 1736 1737 static int proc_eeh_open(struct inode *inode, struct file *file) 1738 { 1739 return single_open(file, proc_eeh_show, NULL); 1740 } 1741 1742 static const struct file_operations proc_eeh_operations = { 1743 .open = proc_eeh_open, 1744 .read = seq_read, 1745 .llseek = seq_lseek, 1746 .release = single_release, 1747 }; 1748 1749 #ifdef CONFIG_DEBUG_FS 1750 static int eeh_enable_dbgfs_set(void *data, u64 val) 1751 { 1752 if (val) 1753 eeh_clear_flag(EEH_FORCE_DISABLED); 1754 else 1755 eeh_add_flag(EEH_FORCE_DISABLED); 1756 1757 /* Notify the backend */ 1758 if (eeh_ops->post_init) 1759 eeh_ops->post_init(); 1760 1761 return 0; 1762 } 1763 1764 static int eeh_enable_dbgfs_get(void *data, u64 *val) 1765 { 1766 if (eeh_enabled()) 1767 *val = 0x1ul; 1768 else 1769 *val = 0x0ul; 1770 return 0; 1771 } 1772 1773 static int eeh_freeze_dbgfs_set(void *data, u64 val) 1774 { 1775 eeh_max_freezes = val; 1776 return 0; 1777 } 1778 1779 static int eeh_freeze_dbgfs_get(void *data, u64 *val) 1780 { 1781 *val = eeh_max_freezes; 1782 return 0; 1783 } 1784 1785 DEFINE_SIMPLE_ATTRIBUTE(eeh_enable_dbgfs_ops, eeh_enable_dbgfs_get, 1786 eeh_enable_dbgfs_set, "0x%llx\n"); 1787 DEFINE_SIMPLE_ATTRIBUTE(eeh_freeze_dbgfs_ops, eeh_freeze_dbgfs_get, 1788 eeh_freeze_dbgfs_set, "0x%llx\n"); 1789 #endif 1790 1791 static int __init eeh_init_proc(void) 1792 { 1793 if (machine_is(pseries) || machine_is(powernv)) { 1794 proc_create("powerpc/eeh", 0, NULL, &proc_eeh_operations); 1795 #ifdef CONFIG_DEBUG_FS 1796 debugfs_create_file("eeh_enable", 0600, 1797 powerpc_debugfs_root, NULL, 1798 &eeh_enable_dbgfs_ops); 1799 debugfs_create_file("eeh_max_freezes", 0600, 1800 powerpc_debugfs_root, NULL, 1801 &eeh_freeze_dbgfs_ops); 1802 #endif 1803 } 1804 1805 return 0; 1806 } 1807 __initcall(eeh_init_proc); 1808