1 /* 2 * Copyright IBM Corporation 2001, 2005, 2006 3 * Copyright Dave Engebretsen & Todd Inglett 2001 4 * Copyright Linas Vepstas 2005, 2006 5 * Copyright 2001-2012 IBM Corporation. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 * 21 * Please address comments and feedback to Linas Vepstas <linas@austin.ibm.com> 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/sched.h> 26 #include <linux/init.h> 27 #include <linux/list.h> 28 #include <linux/pci.h> 29 #include <linux/iommu.h> 30 #include <linux/proc_fs.h> 31 #include <linux/rbtree.h> 32 #include <linux/reboot.h> 33 #include <linux/seq_file.h> 34 #include <linux/spinlock.h> 35 #include <linux/export.h> 36 #include <linux/of.h> 37 38 #include <linux/atomic.h> 39 #include <asm/debugfs.h> 40 #include <asm/eeh.h> 41 #include <asm/eeh_event.h> 42 #include <asm/io.h> 43 #include <asm/iommu.h> 44 #include <asm/machdep.h> 45 #include <asm/ppc-pci.h> 46 #include <asm/rtas.h> 47 #include <asm/pte-walk.h> 48 49 50 /** Overview: 51 * EEH, or "Enhanced Error Handling" is a PCI bridge technology for 52 * dealing with PCI bus errors that can't be dealt with within the 53 * usual PCI framework, except by check-stopping the CPU. Systems 54 * that are designed for high-availability/reliability cannot afford 55 * to crash due to a "mere" PCI error, thus the need for EEH. 56 * An EEH-capable bridge operates by converting a detected error 57 * into a "slot freeze", taking the PCI adapter off-line, making 58 * the slot behave, from the OS'es point of view, as if the slot 59 * were "empty": all reads return 0xff's and all writes are silently 60 * ignored. EEH slot isolation events can be triggered by parity 61 * errors on the address or data busses (e.g. during posted writes), 62 * which in turn might be caused by low voltage on the bus, dust, 63 * vibration, humidity, radioactivity or plain-old failed hardware. 64 * 65 * Note, however, that one of the leading causes of EEH slot 66 * freeze events are buggy device drivers, buggy device microcode, 67 * or buggy device hardware. This is because any attempt by the 68 * device to bus-master data to a memory address that is not 69 * assigned to the device will trigger a slot freeze. (The idea 70 * is to prevent devices-gone-wild from corrupting system memory). 71 * Buggy hardware/drivers will have a miserable time co-existing 72 * with EEH. 73 * 74 * Ideally, a PCI device driver, when suspecting that an isolation 75 * event has occurred (e.g. by reading 0xff's), will then ask EEH 76 * whether this is the case, and then take appropriate steps to 77 * reset the PCI slot, the PCI device, and then resume operations. 78 * However, until that day, the checking is done here, with the 79 * eeh_check_failure() routine embedded in the MMIO macros. If 80 * the slot is found to be isolated, an "EEH Event" is synthesized 81 * and sent out for processing. 82 */ 83 84 /* If a device driver keeps reading an MMIO register in an interrupt 85 * handler after a slot isolation event, it might be broken. 86 * This sets the threshold for how many read attempts we allow 87 * before printing an error message. 88 */ 89 #define EEH_MAX_FAILS 2100000 90 91 /* Time to wait for a PCI slot to report status, in milliseconds */ 92 #define PCI_BUS_RESET_WAIT_MSEC (5*60*1000) 93 94 /* 95 * EEH probe mode support, which is part of the flags, 96 * is to support multiple platforms for EEH. Some platforms 97 * like pSeries do PCI emunation based on device tree. 98 * However, other platforms like powernv probe PCI devices 99 * from hardware. The flag is used to distinguish that. 100 * In addition, struct eeh_ops::probe would be invoked for 101 * particular OF node or PCI device so that the corresponding 102 * PE would be created there. 103 */ 104 int eeh_subsystem_flags; 105 EXPORT_SYMBOL(eeh_subsystem_flags); 106 107 /* 108 * EEH allowed maximal frozen times. If one particular PE's 109 * frozen count in last hour exceeds this limit, the PE will 110 * be forced to be offline permanently. 111 */ 112 u32 eeh_max_freezes = 5; 113 114 /* 115 * Controls whether a recovery event should be scheduled when an 116 * isolated device is discovered. This is only really useful for 117 * debugging problems with the EEH core. 118 */ 119 bool eeh_debugfs_no_recover; 120 121 /* Platform dependent EEH operations */ 122 struct eeh_ops *eeh_ops = NULL; 123 124 /* Lock to avoid races due to multiple reports of an error */ 125 DEFINE_RAW_SPINLOCK(confirm_error_lock); 126 EXPORT_SYMBOL_GPL(confirm_error_lock); 127 128 /* Lock to protect passed flags */ 129 static DEFINE_MUTEX(eeh_dev_mutex); 130 131 /* Buffer for reporting pci register dumps. Its here in BSS, and 132 * not dynamically alloced, so that it ends up in RMO where RTAS 133 * can access it. 134 */ 135 #define EEH_PCI_REGS_LOG_LEN 8192 136 static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN]; 137 138 /* 139 * The struct is used to maintain the EEH global statistic 140 * information. Besides, the EEH global statistics will be 141 * exported to user space through procfs 142 */ 143 struct eeh_stats { 144 u64 no_device; /* PCI device not found */ 145 u64 no_dn; /* OF node not found */ 146 u64 no_cfg_addr; /* Config address not found */ 147 u64 ignored_check; /* EEH check skipped */ 148 u64 total_mmio_ffs; /* Total EEH checks */ 149 u64 false_positives; /* Unnecessary EEH checks */ 150 u64 slot_resets; /* PE reset */ 151 }; 152 153 static struct eeh_stats eeh_stats; 154 155 static int __init eeh_setup(char *str) 156 { 157 if (!strcmp(str, "off")) 158 eeh_add_flag(EEH_FORCE_DISABLED); 159 else if (!strcmp(str, "early_log")) 160 eeh_add_flag(EEH_EARLY_DUMP_LOG); 161 162 return 1; 163 } 164 __setup("eeh=", eeh_setup); 165 166 /* 167 * This routine captures assorted PCI configuration space data 168 * for the indicated PCI device, and puts them into a buffer 169 * for RTAS error logging. 170 */ 171 static size_t eeh_dump_dev_log(struct eeh_dev *edev, char *buf, size_t len) 172 { 173 struct pci_dn *pdn = eeh_dev_to_pdn(edev); 174 u32 cfg; 175 int cap, i; 176 int n = 0, l = 0; 177 char buffer[128]; 178 179 if (!pdn) { 180 pr_warn("EEH: Note: No error log for absent device.\n"); 181 return 0; 182 } 183 184 n += scnprintf(buf+n, len-n, "%04x:%02x:%02x.%01x\n", 185 pdn->phb->global_number, pdn->busno, 186 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn)); 187 pr_warn("EEH: of node=%04x:%02x:%02x.%01x\n", 188 pdn->phb->global_number, pdn->busno, 189 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn)); 190 191 eeh_ops->read_config(pdn, PCI_VENDOR_ID, 4, &cfg); 192 n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg); 193 pr_warn("EEH: PCI device/vendor: %08x\n", cfg); 194 195 eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cfg); 196 n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg); 197 pr_warn("EEH: PCI cmd/status register: %08x\n", cfg); 198 199 /* Gather bridge-specific registers */ 200 if (edev->mode & EEH_DEV_BRIDGE) { 201 eeh_ops->read_config(pdn, PCI_SEC_STATUS, 2, &cfg); 202 n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg); 203 pr_warn("EEH: Bridge secondary status: %04x\n", cfg); 204 205 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &cfg); 206 n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg); 207 pr_warn("EEH: Bridge control: %04x\n", cfg); 208 } 209 210 /* Dump out the PCI-X command and status regs */ 211 cap = edev->pcix_cap; 212 if (cap) { 213 eeh_ops->read_config(pdn, cap, 4, &cfg); 214 n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg); 215 pr_warn("EEH: PCI-X cmd: %08x\n", cfg); 216 217 eeh_ops->read_config(pdn, cap+4, 4, &cfg); 218 n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg); 219 pr_warn("EEH: PCI-X status: %08x\n", cfg); 220 } 221 222 /* If PCI-E capable, dump PCI-E cap 10 */ 223 cap = edev->pcie_cap; 224 if (cap) { 225 n += scnprintf(buf+n, len-n, "pci-e cap10:\n"); 226 pr_warn("EEH: PCI-E capabilities and status follow:\n"); 227 228 for (i=0; i<=8; i++) { 229 eeh_ops->read_config(pdn, cap+4*i, 4, &cfg); 230 n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); 231 232 if ((i % 4) == 0) { 233 if (i != 0) 234 pr_warn("%s\n", buffer); 235 236 l = scnprintf(buffer, sizeof(buffer), 237 "EEH: PCI-E %02x: %08x ", 238 4*i, cfg); 239 } else { 240 l += scnprintf(buffer+l, sizeof(buffer)-l, 241 "%08x ", cfg); 242 } 243 244 } 245 246 pr_warn("%s\n", buffer); 247 } 248 249 /* If AER capable, dump it */ 250 cap = edev->aer_cap; 251 if (cap) { 252 n += scnprintf(buf+n, len-n, "pci-e AER:\n"); 253 pr_warn("EEH: PCI-E AER capability register set follows:\n"); 254 255 for (i=0; i<=13; i++) { 256 eeh_ops->read_config(pdn, cap+4*i, 4, &cfg); 257 n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); 258 259 if ((i % 4) == 0) { 260 if (i != 0) 261 pr_warn("%s\n", buffer); 262 263 l = scnprintf(buffer, sizeof(buffer), 264 "EEH: PCI-E AER %02x: %08x ", 265 4*i, cfg); 266 } else { 267 l += scnprintf(buffer+l, sizeof(buffer)-l, 268 "%08x ", cfg); 269 } 270 } 271 272 pr_warn("%s\n", buffer); 273 } 274 275 return n; 276 } 277 278 static void *eeh_dump_pe_log(struct eeh_pe *pe, void *flag) 279 { 280 struct eeh_dev *edev, *tmp; 281 size_t *plen = flag; 282 283 eeh_pe_for_each_dev(pe, edev, tmp) 284 *plen += eeh_dump_dev_log(edev, pci_regs_buf + *plen, 285 EEH_PCI_REGS_LOG_LEN - *plen); 286 287 return NULL; 288 } 289 290 /** 291 * eeh_slot_error_detail - Generate combined log including driver log and error log 292 * @pe: EEH PE 293 * @severity: temporary or permanent error log 294 * 295 * This routine should be called to generate the combined log, which 296 * is comprised of driver log and error log. The driver log is figured 297 * out from the config space of the corresponding PCI device, while 298 * the error log is fetched through platform dependent function call. 299 */ 300 void eeh_slot_error_detail(struct eeh_pe *pe, int severity) 301 { 302 size_t loglen = 0; 303 304 /* 305 * When the PHB is fenced or dead, it's pointless to collect 306 * the data from PCI config space because it should return 307 * 0xFF's. For ER, we still retrieve the data from the PCI 308 * config space. 309 * 310 * For pHyp, we have to enable IO for log retrieval. Otherwise, 311 * 0xFF's is always returned from PCI config space. 312 * 313 * When the @severity is EEH_LOG_PERM, the PE is going to be 314 * removed. Prior to that, the drivers for devices included in 315 * the PE will be closed. The drivers rely on working IO path 316 * to bring the devices to quiet state. Otherwise, PCI traffic 317 * from those devices after they are removed is like to cause 318 * another unexpected EEH error. 319 */ 320 if (!(pe->type & EEH_PE_PHB)) { 321 if (eeh_has_flag(EEH_ENABLE_IO_FOR_LOG) || 322 severity == EEH_LOG_PERM) 323 eeh_pci_enable(pe, EEH_OPT_THAW_MMIO); 324 325 /* 326 * The config space of some PCI devices can't be accessed 327 * when their PEs are in frozen state. Otherwise, fenced 328 * PHB might be seen. Those PEs are identified with flag 329 * EEH_PE_CFG_RESTRICTED, indicating EEH_PE_CFG_BLOCKED 330 * is set automatically when the PE is put to EEH_PE_ISOLATED. 331 * 332 * Restoring BARs possibly triggers PCI config access in 333 * (OPAL) firmware and then causes fenced PHB. If the 334 * PCI config is blocked with flag EEH_PE_CFG_BLOCKED, it's 335 * pointless to restore BARs and dump config space. 336 */ 337 eeh_ops->configure_bridge(pe); 338 if (!(pe->state & EEH_PE_CFG_BLOCKED)) { 339 eeh_pe_restore_bars(pe); 340 341 pci_regs_buf[0] = 0; 342 eeh_pe_traverse(pe, eeh_dump_pe_log, &loglen); 343 } 344 } 345 346 eeh_ops->get_log(pe, severity, pci_regs_buf, loglen); 347 } 348 349 /** 350 * eeh_token_to_phys - Convert EEH address token to phys address 351 * @token: I/O token, should be address in the form 0xA.... 352 * 353 * This routine should be called to convert virtual I/O address 354 * to physical one. 355 */ 356 static inline unsigned long eeh_token_to_phys(unsigned long token) 357 { 358 pte_t *ptep; 359 unsigned long pa; 360 int hugepage_shift; 361 362 /* 363 * We won't find hugepages here(this is iomem). Hence we are not 364 * worried about _PAGE_SPLITTING/collapse. Also we will not hit 365 * page table free, because of init_mm. 366 */ 367 ptep = find_init_mm_pte(token, &hugepage_shift); 368 if (!ptep) 369 return token; 370 WARN_ON(hugepage_shift); 371 pa = pte_pfn(*ptep) << PAGE_SHIFT; 372 373 return pa | (token & (PAGE_SIZE-1)); 374 } 375 376 /* 377 * On PowerNV platform, we might already have fenced PHB there. 378 * For that case, it's meaningless to recover frozen PE. Intead, 379 * We have to handle fenced PHB firstly. 380 */ 381 static int eeh_phb_check_failure(struct eeh_pe *pe) 382 { 383 struct eeh_pe *phb_pe; 384 unsigned long flags; 385 int ret; 386 387 if (!eeh_has_flag(EEH_PROBE_MODE_DEV)) 388 return -EPERM; 389 390 /* Find the PHB PE */ 391 phb_pe = eeh_phb_pe_get(pe->phb); 392 if (!phb_pe) { 393 pr_warn("%s Can't find PE for PHB#%x\n", 394 __func__, pe->phb->global_number); 395 return -EEXIST; 396 } 397 398 /* If the PHB has been in problematic state */ 399 eeh_serialize_lock(&flags); 400 if (phb_pe->state & EEH_PE_ISOLATED) { 401 ret = 0; 402 goto out; 403 } 404 405 /* Check PHB state */ 406 ret = eeh_ops->get_state(phb_pe, NULL); 407 if ((ret < 0) || 408 (ret == EEH_STATE_NOT_SUPPORT) || eeh_state_active(ret)) { 409 ret = 0; 410 goto out; 411 } 412 413 /* Isolate the PHB and send event */ 414 eeh_pe_mark_isolated(phb_pe); 415 eeh_serialize_unlock(flags); 416 417 pr_err("EEH: PHB#%x failure detected, location: %s\n", 418 phb_pe->phb->global_number, eeh_pe_loc_get(phb_pe)); 419 dump_stack(); 420 eeh_send_failure_event(phb_pe); 421 422 return 1; 423 out: 424 eeh_serialize_unlock(flags); 425 return ret; 426 } 427 428 /** 429 * eeh_dev_check_failure - Check if all 1's data is due to EEH slot freeze 430 * @edev: eeh device 431 * 432 * Check for an EEH failure for the given device node. Call this 433 * routine if the result of a read was all 0xff's and you want to 434 * find out if this is due to an EEH slot freeze. This routine 435 * will query firmware for the EEH status. 436 * 437 * Returns 0 if there has not been an EEH error; otherwise returns 438 * a non-zero value and queues up a slot isolation event notification. 439 * 440 * It is safe to call this routine in an interrupt context. 441 */ 442 int eeh_dev_check_failure(struct eeh_dev *edev) 443 { 444 int ret; 445 unsigned long flags; 446 struct device_node *dn; 447 struct pci_dev *dev; 448 struct eeh_pe *pe, *parent_pe, *phb_pe; 449 int rc = 0; 450 const char *location = NULL; 451 452 eeh_stats.total_mmio_ffs++; 453 454 if (!eeh_enabled()) 455 return 0; 456 457 if (!edev) { 458 eeh_stats.no_dn++; 459 return 0; 460 } 461 dev = eeh_dev_to_pci_dev(edev); 462 pe = eeh_dev_to_pe(edev); 463 464 /* Access to IO BARs might get this far and still not want checking. */ 465 if (!pe) { 466 eeh_stats.ignored_check++; 467 pr_debug("EEH: Ignored check for %s\n", 468 eeh_pci_name(dev)); 469 return 0; 470 } 471 472 if (!pe->addr && !pe->config_addr) { 473 eeh_stats.no_cfg_addr++; 474 return 0; 475 } 476 477 /* 478 * On PowerNV platform, we might already have fenced PHB 479 * there and we need take care of that firstly. 480 */ 481 ret = eeh_phb_check_failure(pe); 482 if (ret > 0) 483 return ret; 484 485 /* 486 * If the PE isn't owned by us, we shouldn't check the 487 * state. Instead, let the owner handle it if the PE has 488 * been frozen. 489 */ 490 if (eeh_pe_passed(pe)) 491 return 0; 492 493 /* If we already have a pending isolation event for this 494 * slot, we know it's bad already, we don't need to check. 495 * Do this checking under a lock; as multiple PCI devices 496 * in one slot might report errors simultaneously, and we 497 * only want one error recovery routine running. 498 */ 499 eeh_serialize_lock(&flags); 500 rc = 1; 501 if (pe->state & EEH_PE_ISOLATED) { 502 pe->check_count++; 503 if (pe->check_count % EEH_MAX_FAILS == 0) { 504 dn = pci_device_to_OF_node(dev); 505 if (dn) 506 location = of_get_property(dn, "ibm,loc-code", 507 NULL); 508 printk(KERN_ERR "EEH: %d reads ignored for recovering device at " 509 "location=%s driver=%s pci addr=%s\n", 510 pe->check_count, 511 location ? location : "unknown", 512 eeh_driver_name(dev), eeh_pci_name(dev)); 513 printk(KERN_ERR "EEH: Might be infinite loop in %s driver\n", 514 eeh_driver_name(dev)); 515 dump_stack(); 516 } 517 goto dn_unlock; 518 } 519 520 /* 521 * Now test for an EEH failure. This is VERY expensive. 522 * Note that the eeh_config_addr may be a parent device 523 * in the case of a device behind a bridge, or it may be 524 * function zero of a multi-function device. 525 * In any case they must share a common PHB. 526 */ 527 ret = eeh_ops->get_state(pe, NULL); 528 529 /* Note that config-io to empty slots may fail; 530 * they are empty when they don't have children. 531 * We will punt with the following conditions: Failure to get 532 * PE's state, EEH not support and Permanently unavailable 533 * state, PE is in good state. 534 */ 535 if ((ret < 0) || 536 (ret == EEH_STATE_NOT_SUPPORT) || eeh_state_active(ret)) { 537 eeh_stats.false_positives++; 538 pe->false_positives++; 539 rc = 0; 540 goto dn_unlock; 541 } 542 543 /* 544 * It should be corner case that the parent PE has been 545 * put into frozen state as well. We should take care 546 * that at first. 547 */ 548 parent_pe = pe->parent; 549 while (parent_pe) { 550 /* Hit the ceiling ? */ 551 if (parent_pe->type & EEH_PE_PHB) 552 break; 553 554 /* Frozen parent PE ? */ 555 ret = eeh_ops->get_state(parent_pe, NULL); 556 if (ret > 0 && !eeh_state_active(ret)) { 557 pe = parent_pe; 558 pr_err("EEH: Failure of PHB#%x-PE#%x will be handled at parent PHB#%x-PE#%x.\n", 559 pe->phb->global_number, pe->addr, 560 pe->phb->global_number, parent_pe->addr); 561 } 562 563 /* Next parent level */ 564 parent_pe = parent_pe->parent; 565 } 566 567 eeh_stats.slot_resets++; 568 569 /* Avoid repeated reports of this failure, including problems 570 * with other functions on this device, and functions under 571 * bridges. 572 */ 573 eeh_pe_mark_isolated(pe); 574 eeh_serialize_unlock(flags); 575 576 /* Most EEH events are due to device driver bugs. Having 577 * a stack trace will help the device-driver authors figure 578 * out what happened. So print that out. 579 */ 580 phb_pe = eeh_phb_pe_get(pe->phb); 581 pr_err("EEH: Frozen PHB#%x-PE#%x detected\n", 582 pe->phb->global_number, pe->addr); 583 pr_err("EEH: PE location: %s, PHB location: %s\n", 584 eeh_pe_loc_get(pe), eeh_pe_loc_get(phb_pe)); 585 dump_stack(); 586 587 eeh_send_failure_event(pe); 588 589 return 1; 590 591 dn_unlock: 592 eeh_serialize_unlock(flags); 593 return rc; 594 } 595 596 EXPORT_SYMBOL_GPL(eeh_dev_check_failure); 597 598 /** 599 * eeh_check_failure - Check if all 1's data is due to EEH slot freeze 600 * @token: I/O address 601 * 602 * Check for an EEH failure at the given I/O address. Call this 603 * routine if the result of a read was all 0xff's and you want to 604 * find out if this is due to an EEH slot freeze event. This routine 605 * will query firmware for the EEH status. 606 * 607 * Note this routine is safe to call in an interrupt context. 608 */ 609 int eeh_check_failure(const volatile void __iomem *token) 610 { 611 unsigned long addr; 612 struct eeh_dev *edev; 613 614 /* Finding the phys addr + pci device; this is pretty quick. */ 615 addr = eeh_token_to_phys((unsigned long __force) token); 616 edev = eeh_addr_cache_get_dev(addr); 617 if (!edev) { 618 eeh_stats.no_device++; 619 return 0; 620 } 621 622 return eeh_dev_check_failure(edev); 623 } 624 EXPORT_SYMBOL(eeh_check_failure); 625 626 627 /** 628 * eeh_pci_enable - Enable MMIO or DMA transfers for this slot 629 * @pe: EEH PE 630 * 631 * This routine should be called to reenable frozen MMIO or DMA 632 * so that it would work correctly again. It's useful while doing 633 * recovery or log collection on the indicated device. 634 */ 635 int eeh_pci_enable(struct eeh_pe *pe, int function) 636 { 637 int active_flag, rc; 638 639 /* 640 * pHyp doesn't allow to enable IO or DMA on unfrozen PE. 641 * Also, it's pointless to enable them on unfrozen PE. So 642 * we have to check before enabling IO or DMA. 643 */ 644 switch (function) { 645 case EEH_OPT_THAW_MMIO: 646 active_flag = EEH_STATE_MMIO_ACTIVE | EEH_STATE_MMIO_ENABLED; 647 break; 648 case EEH_OPT_THAW_DMA: 649 active_flag = EEH_STATE_DMA_ACTIVE; 650 break; 651 case EEH_OPT_DISABLE: 652 case EEH_OPT_ENABLE: 653 case EEH_OPT_FREEZE_PE: 654 active_flag = 0; 655 break; 656 default: 657 pr_warn("%s: Invalid function %d\n", 658 __func__, function); 659 return -EINVAL; 660 } 661 662 /* 663 * Check if IO or DMA has been enabled before 664 * enabling them. 665 */ 666 if (active_flag) { 667 rc = eeh_ops->get_state(pe, NULL); 668 if (rc < 0) 669 return rc; 670 671 /* Needn't enable it at all */ 672 if (rc == EEH_STATE_NOT_SUPPORT) 673 return 0; 674 675 /* It's already enabled */ 676 if (rc & active_flag) 677 return 0; 678 } 679 680 681 /* Issue the request */ 682 rc = eeh_ops->set_option(pe, function); 683 if (rc) 684 pr_warn("%s: Unexpected state change %d on " 685 "PHB#%x-PE#%x, err=%d\n", 686 __func__, function, pe->phb->global_number, 687 pe->addr, rc); 688 689 /* Check if the request is finished successfully */ 690 if (active_flag) { 691 rc = eeh_wait_state(pe, PCI_BUS_RESET_WAIT_MSEC); 692 if (rc < 0) 693 return rc; 694 695 if (rc & active_flag) 696 return 0; 697 698 return -EIO; 699 } 700 701 return rc; 702 } 703 704 static void *eeh_disable_and_save_dev_state(struct eeh_dev *edev, 705 void *userdata) 706 { 707 struct pci_dev *pdev = eeh_dev_to_pci_dev(edev); 708 struct pci_dev *dev = userdata; 709 710 /* 711 * The caller should have disabled and saved the 712 * state for the specified device 713 */ 714 if (!pdev || pdev == dev) 715 return NULL; 716 717 /* Ensure we have D0 power state */ 718 pci_set_power_state(pdev, PCI_D0); 719 720 /* Save device state */ 721 pci_save_state(pdev); 722 723 /* 724 * Disable device to avoid any DMA traffic and 725 * interrupt from the device 726 */ 727 pci_write_config_word(pdev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); 728 729 return NULL; 730 } 731 732 static void *eeh_restore_dev_state(struct eeh_dev *edev, void *userdata) 733 { 734 struct pci_dn *pdn = eeh_dev_to_pdn(edev); 735 struct pci_dev *pdev = eeh_dev_to_pci_dev(edev); 736 struct pci_dev *dev = userdata; 737 738 if (!pdev) 739 return NULL; 740 741 /* Apply customization from firmware */ 742 if (pdn && eeh_ops->restore_config) 743 eeh_ops->restore_config(pdn); 744 745 /* The caller should restore state for the specified device */ 746 if (pdev != dev) 747 pci_restore_state(pdev); 748 749 return NULL; 750 } 751 752 int eeh_restore_vf_config(struct pci_dn *pdn) 753 { 754 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 755 u32 devctl, cmd, cap2, aer_capctl; 756 int old_mps; 757 758 if (edev->pcie_cap) { 759 /* Restore MPS */ 760 old_mps = (ffs(pdn->mps) - 8) << 5; 761 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 762 2, &devctl); 763 devctl &= ~PCI_EXP_DEVCTL_PAYLOAD; 764 devctl |= old_mps; 765 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 766 2, devctl); 767 768 /* Disable Completion Timeout if possible */ 769 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP2, 770 4, &cap2); 771 if (cap2 & PCI_EXP_DEVCAP2_COMP_TMOUT_DIS) { 772 eeh_ops->read_config(pdn, 773 edev->pcie_cap + PCI_EXP_DEVCTL2, 774 4, &cap2); 775 cap2 |= PCI_EXP_DEVCTL2_COMP_TMOUT_DIS; 776 eeh_ops->write_config(pdn, 777 edev->pcie_cap + PCI_EXP_DEVCTL2, 778 4, cap2); 779 } 780 } 781 782 /* Enable SERR and parity checking */ 783 eeh_ops->read_config(pdn, PCI_COMMAND, 2, &cmd); 784 cmd |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 785 eeh_ops->write_config(pdn, PCI_COMMAND, 2, cmd); 786 787 /* Enable report various errors */ 788 if (edev->pcie_cap) { 789 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 790 2, &devctl); 791 devctl &= ~PCI_EXP_DEVCTL_CERE; 792 devctl |= (PCI_EXP_DEVCTL_NFERE | 793 PCI_EXP_DEVCTL_FERE | 794 PCI_EXP_DEVCTL_URRE); 795 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 796 2, devctl); 797 } 798 799 /* Enable ECRC generation and check */ 800 if (edev->pcie_cap && edev->aer_cap) { 801 eeh_ops->read_config(pdn, edev->aer_cap + PCI_ERR_CAP, 802 4, &aer_capctl); 803 aer_capctl |= (PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE); 804 eeh_ops->write_config(pdn, edev->aer_cap + PCI_ERR_CAP, 805 4, aer_capctl); 806 } 807 808 return 0; 809 } 810 811 /** 812 * pcibios_set_pcie_reset_state - Set PCI-E reset state 813 * @dev: pci device struct 814 * @state: reset state to enter 815 * 816 * Return value: 817 * 0 if success 818 */ 819 int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) 820 { 821 struct eeh_dev *edev = pci_dev_to_eeh_dev(dev); 822 struct eeh_pe *pe = eeh_dev_to_pe(edev); 823 824 if (!pe) { 825 pr_err("%s: No PE found on PCI device %s\n", 826 __func__, pci_name(dev)); 827 return -EINVAL; 828 } 829 830 switch (state) { 831 case pcie_deassert_reset: 832 eeh_ops->reset(pe, EEH_RESET_DEACTIVATE); 833 eeh_unfreeze_pe(pe); 834 if (!(pe->type & EEH_PE_VF)) 835 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true); 836 eeh_pe_dev_traverse(pe, eeh_restore_dev_state, dev); 837 eeh_pe_state_clear(pe, EEH_PE_ISOLATED, true); 838 break; 839 case pcie_hot_reset: 840 eeh_pe_mark_isolated(pe); 841 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true); 842 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE); 843 eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev); 844 if (!(pe->type & EEH_PE_VF)) 845 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED); 846 eeh_ops->reset(pe, EEH_RESET_HOT); 847 break; 848 case pcie_warm_reset: 849 eeh_pe_mark_isolated(pe); 850 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true); 851 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE); 852 eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev); 853 if (!(pe->type & EEH_PE_VF)) 854 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED); 855 eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL); 856 break; 857 default: 858 eeh_pe_state_clear(pe, EEH_PE_ISOLATED | EEH_PE_CFG_BLOCKED, true); 859 return -EINVAL; 860 }; 861 862 return 0; 863 } 864 865 /** 866 * eeh_set_pe_freset - Check the required reset for the indicated device 867 * @data: EEH device 868 * @flag: return value 869 * 870 * Each device might have its preferred reset type: fundamental or 871 * hot reset. The routine is used to collected the information for 872 * the indicated device and its children so that the bunch of the 873 * devices could be reset properly. 874 */ 875 static void *eeh_set_dev_freset(struct eeh_dev *edev, void *flag) 876 { 877 struct pci_dev *dev; 878 unsigned int *freset = (unsigned int *)flag; 879 880 dev = eeh_dev_to_pci_dev(edev); 881 if (dev) 882 *freset |= dev->needs_freset; 883 884 return NULL; 885 } 886 887 static void eeh_pe_refreeze_passed(struct eeh_pe *root) 888 { 889 struct eeh_pe *pe; 890 int state; 891 892 eeh_for_each_pe(root, pe) { 893 if (eeh_pe_passed(pe)) { 894 state = eeh_ops->get_state(pe, NULL); 895 if (state & 896 (EEH_STATE_MMIO_ACTIVE | EEH_STATE_MMIO_ENABLED)) { 897 pr_info("EEH: Passed-through PE PHB#%x-PE#%x was thawed by reset, re-freezing for safety.\n", 898 pe->phb->global_number, pe->addr); 899 eeh_pe_set_option(pe, EEH_OPT_FREEZE_PE); 900 } 901 } 902 } 903 } 904 905 /** 906 * eeh_pe_reset_full - Complete a full reset process on the indicated PE 907 * @pe: EEH PE 908 * 909 * This function executes a full reset procedure on a PE, including setting 910 * the appropriate flags, performing a fundamental or hot reset, and then 911 * deactivating the reset status. It is designed to be used within the EEH 912 * subsystem, as opposed to eeh_pe_reset which is exported to drivers and 913 * only performs a single operation at a time. 914 * 915 * This function will attempt to reset a PE three times before failing. 916 */ 917 int eeh_pe_reset_full(struct eeh_pe *pe, bool include_passed) 918 { 919 int reset_state = (EEH_PE_RESET | EEH_PE_CFG_BLOCKED); 920 int type = EEH_RESET_HOT; 921 unsigned int freset = 0; 922 int i, state = 0, ret; 923 924 /* 925 * Determine the type of reset to perform - hot or fundamental. 926 * Hot reset is the default operation, unless any device under the 927 * PE requires a fundamental reset. 928 */ 929 eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset); 930 931 if (freset) 932 type = EEH_RESET_FUNDAMENTAL; 933 934 /* Mark the PE as in reset state and block config space accesses */ 935 eeh_pe_state_mark(pe, reset_state); 936 937 /* Make three attempts at resetting the bus */ 938 for (i = 0; i < 3; i++) { 939 ret = eeh_pe_reset(pe, type, include_passed); 940 if (!ret) 941 ret = eeh_pe_reset(pe, EEH_RESET_DEACTIVATE, 942 include_passed); 943 if (ret) { 944 ret = -EIO; 945 pr_warn("EEH: Failure %d resetting PHB#%x-PE#%x (attempt %d)\n\n", 946 state, pe->phb->global_number, pe->addr, i + 1); 947 continue; 948 } 949 if (i) 950 pr_warn("EEH: PHB#%x-PE#%x: Successful reset (attempt %d)\n", 951 pe->phb->global_number, pe->addr, i + 1); 952 953 /* Wait until the PE is in a functioning state */ 954 state = eeh_wait_state(pe, PCI_BUS_RESET_WAIT_MSEC); 955 if (state < 0) { 956 pr_warn("EEH: Unrecoverable slot failure on PHB#%x-PE#%x", 957 pe->phb->global_number, pe->addr); 958 ret = -ENOTRECOVERABLE; 959 break; 960 } 961 if (eeh_state_active(state)) 962 break; 963 else 964 pr_warn("EEH: PHB#%x-PE#%x: Slot inactive after reset: 0x%x (attempt %d)\n", 965 pe->phb->global_number, pe->addr, state, i + 1); 966 } 967 968 /* Resetting the PE may have unfrozen child PEs. If those PEs have been 969 * (potentially) passed through to a guest, re-freeze them: 970 */ 971 if (!include_passed) 972 eeh_pe_refreeze_passed(pe); 973 974 eeh_pe_state_clear(pe, reset_state, true); 975 return ret; 976 } 977 978 /** 979 * eeh_save_bars - Save device bars 980 * @edev: PCI device associated EEH device 981 * 982 * Save the values of the device bars. Unlike the restore 983 * routine, this routine is *not* recursive. This is because 984 * PCI devices are added individually; but, for the restore, 985 * an entire slot is reset at a time. 986 */ 987 void eeh_save_bars(struct eeh_dev *edev) 988 { 989 struct pci_dn *pdn; 990 int i; 991 992 pdn = eeh_dev_to_pdn(edev); 993 if (!pdn) 994 return; 995 996 for (i = 0; i < 16; i++) 997 eeh_ops->read_config(pdn, i * 4, 4, &edev->config_space[i]); 998 999 /* 1000 * For PCI bridges including root port, we need enable bus 1001 * master explicitly. Otherwise, it can't fetch IODA table 1002 * entries correctly. So we cache the bit in advance so that 1003 * we can restore it after reset, either PHB range or PE range. 1004 */ 1005 if (edev->mode & EEH_DEV_BRIDGE) 1006 edev->config_space[1] |= PCI_COMMAND_MASTER; 1007 } 1008 1009 /** 1010 * eeh_ops_register - Register platform dependent EEH operations 1011 * @ops: platform dependent EEH operations 1012 * 1013 * Register the platform dependent EEH operation callback 1014 * functions. The platform should call this function before 1015 * any other EEH operations. 1016 */ 1017 int __init eeh_ops_register(struct eeh_ops *ops) 1018 { 1019 if (!ops->name) { 1020 pr_warn("%s: Invalid EEH ops name for %p\n", 1021 __func__, ops); 1022 return -EINVAL; 1023 } 1024 1025 if (eeh_ops && eeh_ops != ops) { 1026 pr_warn("%s: EEH ops of platform %s already existing (%s)\n", 1027 __func__, eeh_ops->name, ops->name); 1028 return -EEXIST; 1029 } 1030 1031 eeh_ops = ops; 1032 1033 return 0; 1034 } 1035 1036 /** 1037 * eeh_ops_unregister - Unreigster platform dependent EEH operations 1038 * @name: name of EEH platform operations 1039 * 1040 * Unregister the platform dependent EEH operation callback 1041 * functions. 1042 */ 1043 int __exit eeh_ops_unregister(const char *name) 1044 { 1045 if (!name || !strlen(name)) { 1046 pr_warn("%s: Invalid EEH ops name\n", 1047 __func__); 1048 return -EINVAL; 1049 } 1050 1051 if (eeh_ops && !strcmp(eeh_ops->name, name)) { 1052 eeh_ops = NULL; 1053 return 0; 1054 } 1055 1056 return -EEXIST; 1057 } 1058 1059 static int eeh_reboot_notifier(struct notifier_block *nb, 1060 unsigned long action, void *unused) 1061 { 1062 eeh_clear_flag(EEH_ENABLED); 1063 return NOTIFY_DONE; 1064 } 1065 1066 static struct notifier_block eeh_reboot_nb = { 1067 .notifier_call = eeh_reboot_notifier, 1068 }; 1069 1070 void eeh_probe_devices(void) 1071 { 1072 struct pci_controller *hose, *tmp; 1073 struct pci_dn *pdn; 1074 1075 /* Enable EEH for all adapters */ 1076 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1077 pdn = hose->pci_data; 1078 traverse_pci_dn(pdn, eeh_ops->probe, NULL); 1079 } 1080 if (eeh_enabled()) 1081 pr_info("EEH: PCI Enhanced I/O Error Handling Enabled\n"); 1082 else 1083 pr_info("EEH: No capable adapters found\n"); 1084 1085 } 1086 1087 /** 1088 * eeh_init - EEH initialization 1089 * 1090 * Initialize EEH by trying to enable it for all of the adapters in the system. 1091 * As a side effect we can determine here if eeh is supported at all. 1092 * Note that we leave EEH on so failed config cycles won't cause a machine 1093 * check. If a user turns off EEH for a particular adapter they are really 1094 * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't 1095 * grant access to a slot if EEH isn't enabled, and so we always enable 1096 * EEH for all slots/all devices. 1097 * 1098 * The eeh-force-off option disables EEH checking globally, for all slots. 1099 * Even if force-off is set, the EEH hardware is still enabled, so that 1100 * newer systems can boot. 1101 */ 1102 static int eeh_init(void) 1103 { 1104 struct pci_controller *hose, *tmp; 1105 int ret = 0; 1106 1107 /* Register reboot notifier */ 1108 ret = register_reboot_notifier(&eeh_reboot_nb); 1109 if (ret) { 1110 pr_warn("%s: Failed to register notifier (%d)\n", 1111 __func__, ret); 1112 return ret; 1113 } 1114 1115 /* call platform initialization function */ 1116 if (!eeh_ops) { 1117 pr_warn("%s: Platform EEH operation not found\n", 1118 __func__); 1119 return -EEXIST; 1120 } else if ((ret = eeh_ops->init())) 1121 return ret; 1122 1123 /* Initialize PHB PEs */ 1124 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 1125 eeh_dev_phb_init_dynamic(hose); 1126 1127 /* Initialize EEH event */ 1128 return eeh_event_init(); 1129 } 1130 1131 core_initcall_sync(eeh_init); 1132 1133 /** 1134 * eeh_add_device_early - Enable EEH for the indicated device node 1135 * @pdn: PCI device node for which to set up EEH 1136 * 1137 * This routine must be used to perform EEH initialization for PCI 1138 * devices that were added after system boot (e.g. hotplug, dlpar). 1139 * This routine must be called before any i/o is performed to the 1140 * adapter (inluding any config-space i/o). 1141 * Whether this actually enables EEH or not for this device depends 1142 * on the CEC architecture, type of the device, on earlier boot 1143 * command-line arguments & etc. 1144 */ 1145 void eeh_add_device_early(struct pci_dn *pdn) 1146 { 1147 struct pci_controller *phb = pdn ? pdn->phb : NULL; 1148 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1149 1150 if (!edev) 1151 return; 1152 1153 if (!eeh_has_flag(EEH_PROBE_MODE_DEVTREE)) 1154 return; 1155 1156 /* USB Bus children of PCI devices will not have BUID's */ 1157 if (NULL == phb || 1158 (eeh_has_flag(EEH_PROBE_MODE_DEVTREE) && 0 == phb->buid)) 1159 return; 1160 1161 eeh_ops->probe(pdn, NULL); 1162 } 1163 1164 /** 1165 * eeh_add_device_tree_early - Enable EEH for the indicated device 1166 * @pdn: PCI device node 1167 * 1168 * This routine must be used to perform EEH initialization for the 1169 * indicated PCI device that was added after system boot (e.g. 1170 * hotplug, dlpar). 1171 */ 1172 void eeh_add_device_tree_early(struct pci_dn *pdn) 1173 { 1174 struct pci_dn *n; 1175 1176 if (!pdn) 1177 return; 1178 1179 list_for_each_entry(n, &pdn->child_list, list) 1180 eeh_add_device_tree_early(n); 1181 eeh_add_device_early(pdn); 1182 } 1183 EXPORT_SYMBOL_GPL(eeh_add_device_tree_early); 1184 1185 /** 1186 * eeh_add_device_late - Perform EEH initialization for the indicated pci device 1187 * @dev: pci device for which to set up EEH 1188 * 1189 * This routine must be used to complete EEH initialization for PCI 1190 * devices that were added after system boot (e.g. hotplug, dlpar). 1191 */ 1192 void eeh_add_device_late(struct pci_dev *dev) 1193 { 1194 struct pci_dn *pdn; 1195 struct eeh_dev *edev; 1196 1197 if (!dev || !eeh_enabled()) 1198 return; 1199 1200 pr_debug("EEH: Adding device %s\n", pci_name(dev)); 1201 1202 pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); 1203 edev = pdn_to_eeh_dev(pdn); 1204 if (edev->pdev == dev) { 1205 pr_debug("EEH: Already referenced !\n"); 1206 return; 1207 } 1208 1209 /* 1210 * The EEH cache might not be removed correctly because of 1211 * unbalanced kref to the device during unplug time, which 1212 * relies on pcibios_release_device(). So we have to remove 1213 * that here explicitly. 1214 */ 1215 if (edev->pdev) { 1216 eeh_rmv_from_parent_pe(edev); 1217 eeh_addr_cache_rmv_dev(edev->pdev); 1218 eeh_sysfs_remove_device(edev->pdev); 1219 edev->mode &= ~EEH_DEV_SYSFS; 1220 1221 /* 1222 * We definitely should have the PCI device removed 1223 * though it wasn't correctly. So we needn't call 1224 * into error handler afterwards. 1225 */ 1226 edev->mode |= EEH_DEV_NO_HANDLER; 1227 1228 edev->pdev = NULL; 1229 dev->dev.archdata.edev = NULL; 1230 } 1231 1232 if (eeh_has_flag(EEH_PROBE_MODE_DEV)) 1233 eeh_ops->probe(pdn, NULL); 1234 1235 edev->pdev = dev; 1236 dev->dev.archdata.edev = edev; 1237 1238 eeh_addr_cache_insert_dev(dev); 1239 } 1240 1241 /** 1242 * eeh_add_device_tree_late - Perform EEH initialization for the indicated PCI bus 1243 * @bus: PCI bus 1244 * 1245 * This routine must be used to perform EEH initialization for PCI 1246 * devices which are attached to the indicated PCI bus. The PCI bus 1247 * is added after system boot through hotplug or dlpar. 1248 */ 1249 void eeh_add_device_tree_late(struct pci_bus *bus) 1250 { 1251 struct pci_dev *dev; 1252 1253 list_for_each_entry(dev, &bus->devices, bus_list) { 1254 eeh_add_device_late(dev); 1255 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 1256 struct pci_bus *subbus = dev->subordinate; 1257 if (subbus) 1258 eeh_add_device_tree_late(subbus); 1259 } 1260 } 1261 } 1262 EXPORT_SYMBOL_GPL(eeh_add_device_tree_late); 1263 1264 /** 1265 * eeh_add_sysfs_files - Add EEH sysfs files for the indicated PCI bus 1266 * @bus: PCI bus 1267 * 1268 * This routine must be used to add EEH sysfs files for PCI 1269 * devices which are attached to the indicated PCI bus. The PCI bus 1270 * is added after system boot through hotplug or dlpar. 1271 */ 1272 void eeh_add_sysfs_files(struct pci_bus *bus) 1273 { 1274 struct pci_dev *dev; 1275 1276 list_for_each_entry(dev, &bus->devices, bus_list) { 1277 eeh_sysfs_add_device(dev); 1278 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 1279 struct pci_bus *subbus = dev->subordinate; 1280 if (subbus) 1281 eeh_add_sysfs_files(subbus); 1282 } 1283 } 1284 } 1285 EXPORT_SYMBOL_GPL(eeh_add_sysfs_files); 1286 1287 /** 1288 * eeh_remove_device - Undo EEH setup for the indicated pci device 1289 * @dev: pci device to be removed 1290 * 1291 * This routine should be called when a device is removed from 1292 * a running system (e.g. by hotplug or dlpar). It unregisters 1293 * the PCI device from the EEH subsystem. I/O errors affecting 1294 * this device will no longer be detected after this call; thus, 1295 * i/o errors affecting this slot may leave this device unusable. 1296 */ 1297 void eeh_remove_device(struct pci_dev *dev) 1298 { 1299 struct eeh_dev *edev; 1300 1301 if (!dev || !eeh_enabled()) 1302 return; 1303 edev = pci_dev_to_eeh_dev(dev); 1304 1305 /* Unregister the device with the EEH/PCI address search system */ 1306 pr_debug("EEH: Removing device %s\n", pci_name(dev)); 1307 1308 if (!edev || !edev->pdev || !edev->pe) { 1309 pr_debug("EEH: Not referenced !\n"); 1310 return; 1311 } 1312 1313 /* 1314 * During the hotplug for EEH error recovery, we need the EEH 1315 * device attached to the parent PE in order for BAR restore 1316 * a bit later. So we keep it for BAR restore and remove it 1317 * from the parent PE during the BAR resotre. 1318 */ 1319 edev->pdev = NULL; 1320 1321 /* 1322 * The flag "in_error" is used to trace EEH devices for VFs 1323 * in error state or not. It's set in eeh_report_error(). If 1324 * it's not set, eeh_report_{reset,resume}() won't be called 1325 * for the VF EEH device. 1326 */ 1327 edev->in_error = false; 1328 dev->dev.archdata.edev = NULL; 1329 if (!(edev->pe->state & EEH_PE_KEEP)) 1330 eeh_rmv_from_parent_pe(edev); 1331 else 1332 edev->mode |= EEH_DEV_DISCONNECTED; 1333 1334 /* 1335 * We're removing from the PCI subsystem, that means 1336 * the PCI device driver can't support EEH or not 1337 * well. So we rely on hotplug completely to do recovery 1338 * for the specific PCI device. 1339 */ 1340 edev->mode |= EEH_DEV_NO_HANDLER; 1341 1342 eeh_addr_cache_rmv_dev(dev); 1343 eeh_sysfs_remove_device(dev); 1344 edev->mode &= ~EEH_DEV_SYSFS; 1345 } 1346 1347 int eeh_unfreeze_pe(struct eeh_pe *pe) 1348 { 1349 int ret; 1350 1351 ret = eeh_pci_enable(pe, EEH_OPT_THAW_MMIO); 1352 if (ret) { 1353 pr_warn("%s: Failure %d enabling IO on PHB#%x-PE#%x\n", 1354 __func__, ret, pe->phb->global_number, pe->addr); 1355 return ret; 1356 } 1357 1358 ret = eeh_pci_enable(pe, EEH_OPT_THAW_DMA); 1359 if (ret) { 1360 pr_warn("%s: Failure %d enabling DMA on PHB#%x-PE#%x\n", 1361 __func__, ret, pe->phb->global_number, pe->addr); 1362 return ret; 1363 } 1364 1365 return ret; 1366 } 1367 1368 1369 static struct pci_device_id eeh_reset_ids[] = { 1370 { PCI_DEVICE(0x19a2, 0x0710) }, /* Emulex, BE */ 1371 { PCI_DEVICE(0x10df, 0xe220) }, /* Emulex, Lancer */ 1372 { PCI_DEVICE(0x14e4, 0x1657) }, /* Broadcom BCM5719 */ 1373 { 0 } 1374 }; 1375 1376 static int eeh_pe_change_owner(struct eeh_pe *pe) 1377 { 1378 struct eeh_dev *edev, *tmp; 1379 struct pci_dev *pdev; 1380 struct pci_device_id *id; 1381 int ret; 1382 1383 /* Check PE state */ 1384 ret = eeh_ops->get_state(pe, NULL); 1385 if (ret < 0 || ret == EEH_STATE_NOT_SUPPORT) 1386 return 0; 1387 1388 /* Unfrozen PE, nothing to do */ 1389 if (eeh_state_active(ret)) 1390 return 0; 1391 1392 /* Frozen PE, check if it needs PE level reset */ 1393 eeh_pe_for_each_dev(pe, edev, tmp) { 1394 pdev = eeh_dev_to_pci_dev(edev); 1395 if (!pdev) 1396 continue; 1397 1398 for (id = &eeh_reset_ids[0]; id->vendor != 0; id++) { 1399 if (id->vendor != PCI_ANY_ID && 1400 id->vendor != pdev->vendor) 1401 continue; 1402 if (id->device != PCI_ANY_ID && 1403 id->device != pdev->device) 1404 continue; 1405 if (id->subvendor != PCI_ANY_ID && 1406 id->subvendor != pdev->subsystem_vendor) 1407 continue; 1408 if (id->subdevice != PCI_ANY_ID && 1409 id->subdevice != pdev->subsystem_device) 1410 continue; 1411 1412 return eeh_pe_reset_and_recover(pe); 1413 } 1414 } 1415 1416 ret = eeh_unfreeze_pe(pe); 1417 if (!ret) 1418 eeh_pe_state_clear(pe, EEH_PE_ISOLATED, true); 1419 return ret; 1420 } 1421 1422 /** 1423 * eeh_dev_open - Increase count of pass through devices for PE 1424 * @pdev: PCI device 1425 * 1426 * Increase count of passed through devices for the indicated 1427 * PE. In the result, the EEH errors detected on the PE won't be 1428 * reported. The PE owner will be responsible for detection 1429 * and recovery. 1430 */ 1431 int eeh_dev_open(struct pci_dev *pdev) 1432 { 1433 struct eeh_dev *edev; 1434 int ret = -ENODEV; 1435 1436 mutex_lock(&eeh_dev_mutex); 1437 1438 /* No PCI device ? */ 1439 if (!pdev) 1440 goto out; 1441 1442 /* No EEH device or PE ? */ 1443 edev = pci_dev_to_eeh_dev(pdev); 1444 if (!edev || !edev->pe) 1445 goto out; 1446 1447 /* 1448 * The PE might have been put into frozen state, but we 1449 * didn't detect that yet. The passed through PCI devices 1450 * in frozen PE won't work properly. Clear the frozen state 1451 * in advance. 1452 */ 1453 ret = eeh_pe_change_owner(edev->pe); 1454 if (ret) 1455 goto out; 1456 1457 /* Increase PE's pass through count */ 1458 atomic_inc(&edev->pe->pass_dev_cnt); 1459 mutex_unlock(&eeh_dev_mutex); 1460 1461 return 0; 1462 out: 1463 mutex_unlock(&eeh_dev_mutex); 1464 return ret; 1465 } 1466 EXPORT_SYMBOL_GPL(eeh_dev_open); 1467 1468 /** 1469 * eeh_dev_release - Decrease count of pass through devices for PE 1470 * @pdev: PCI device 1471 * 1472 * Decrease count of pass through devices for the indicated PE. If 1473 * there is no passed through device in PE, the EEH errors detected 1474 * on the PE will be reported and handled as usual. 1475 */ 1476 void eeh_dev_release(struct pci_dev *pdev) 1477 { 1478 struct eeh_dev *edev; 1479 1480 mutex_lock(&eeh_dev_mutex); 1481 1482 /* No PCI device ? */ 1483 if (!pdev) 1484 goto out; 1485 1486 /* No EEH device ? */ 1487 edev = pci_dev_to_eeh_dev(pdev); 1488 if (!edev || !edev->pe || !eeh_pe_passed(edev->pe)) 1489 goto out; 1490 1491 /* Decrease PE's pass through count */ 1492 WARN_ON(atomic_dec_if_positive(&edev->pe->pass_dev_cnt) < 0); 1493 eeh_pe_change_owner(edev->pe); 1494 out: 1495 mutex_unlock(&eeh_dev_mutex); 1496 } 1497 EXPORT_SYMBOL(eeh_dev_release); 1498 1499 #ifdef CONFIG_IOMMU_API 1500 1501 static int dev_has_iommu_table(struct device *dev, void *data) 1502 { 1503 struct pci_dev *pdev = to_pci_dev(dev); 1504 struct pci_dev **ppdev = data; 1505 1506 if (!dev) 1507 return 0; 1508 1509 if (device_iommu_mapped(dev)) { 1510 *ppdev = pdev; 1511 return 1; 1512 } 1513 1514 return 0; 1515 } 1516 1517 /** 1518 * eeh_iommu_group_to_pe - Convert IOMMU group to EEH PE 1519 * @group: IOMMU group 1520 * 1521 * The routine is called to convert IOMMU group to EEH PE. 1522 */ 1523 struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group) 1524 { 1525 struct pci_dev *pdev = NULL; 1526 struct eeh_dev *edev; 1527 int ret; 1528 1529 /* No IOMMU group ? */ 1530 if (!group) 1531 return NULL; 1532 1533 ret = iommu_group_for_each_dev(group, &pdev, dev_has_iommu_table); 1534 if (!ret || !pdev) 1535 return NULL; 1536 1537 /* No EEH device or PE ? */ 1538 edev = pci_dev_to_eeh_dev(pdev); 1539 if (!edev || !edev->pe) 1540 return NULL; 1541 1542 return edev->pe; 1543 } 1544 EXPORT_SYMBOL_GPL(eeh_iommu_group_to_pe); 1545 1546 #endif /* CONFIG_IOMMU_API */ 1547 1548 /** 1549 * eeh_pe_set_option - Set options for the indicated PE 1550 * @pe: EEH PE 1551 * @option: requested option 1552 * 1553 * The routine is called to enable or disable EEH functionality 1554 * on the indicated PE, to enable IO or DMA for the frozen PE. 1555 */ 1556 int eeh_pe_set_option(struct eeh_pe *pe, int option) 1557 { 1558 int ret = 0; 1559 1560 /* Invalid PE ? */ 1561 if (!pe) 1562 return -ENODEV; 1563 1564 /* 1565 * EEH functionality could possibly be disabled, just 1566 * return error for the case. And the EEH functinality 1567 * isn't expected to be disabled on one specific PE. 1568 */ 1569 switch (option) { 1570 case EEH_OPT_ENABLE: 1571 if (eeh_enabled()) { 1572 ret = eeh_pe_change_owner(pe); 1573 break; 1574 } 1575 ret = -EIO; 1576 break; 1577 case EEH_OPT_DISABLE: 1578 break; 1579 case EEH_OPT_THAW_MMIO: 1580 case EEH_OPT_THAW_DMA: 1581 case EEH_OPT_FREEZE_PE: 1582 if (!eeh_ops || !eeh_ops->set_option) { 1583 ret = -ENOENT; 1584 break; 1585 } 1586 1587 ret = eeh_pci_enable(pe, option); 1588 break; 1589 default: 1590 pr_debug("%s: Option %d out of range (%d, %d)\n", 1591 __func__, option, EEH_OPT_DISABLE, EEH_OPT_THAW_DMA); 1592 ret = -EINVAL; 1593 } 1594 1595 return ret; 1596 } 1597 EXPORT_SYMBOL_GPL(eeh_pe_set_option); 1598 1599 /** 1600 * eeh_pe_get_state - Retrieve PE's state 1601 * @pe: EEH PE 1602 * 1603 * Retrieve the PE's state, which includes 3 aspects: enabled 1604 * DMA, enabled IO and asserted reset. 1605 */ 1606 int eeh_pe_get_state(struct eeh_pe *pe) 1607 { 1608 int result, ret = 0; 1609 bool rst_active, dma_en, mmio_en; 1610 1611 /* Existing PE ? */ 1612 if (!pe) 1613 return -ENODEV; 1614 1615 if (!eeh_ops || !eeh_ops->get_state) 1616 return -ENOENT; 1617 1618 /* 1619 * If the parent PE is owned by the host kernel and is undergoing 1620 * error recovery, we should return the PE state as temporarily 1621 * unavailable so that the error recovery on the guest is suspended 1622 * until the recovery completes on the host. 1623 */ 1624 if (pe->parent && 1625 !(pe->state & EEH_PE_REMOVED) && 1626 (pe->parent->state & (EEH_PE_ISOLATED | EEH_PE_RECOVERING))) 1627 return EEH_PE_STATE_UNAVAIL; 1628 1629 result = eeh_ops->get_state(pe, NULL); 1630 rst_active = !!(result & EEH_STATE_RESET_ACTIVE); 1631 dma_en = !!(result & EEH_STATE_DMA_ENABLED); 1632 mmio_en = !!(result & EEH_STATE_MMIO_ENABLED); 1633 1634 if (rst_active) 1635 ret = EEH_PE_STATE_RESET; 1636 else if (dma_en && mmio_en) 1637 ret = EEH_PE_STATE_NORMAL; 1638 else if (!dma_en && !mmio_en) 1639 ret = EEH_PE_STATE_STOPPED_IO_DMA; 1640 else if (!dma_en && mmio_en) 1641 ret = EEH_PE_STATE_STOPPED_DMA; 1642 else 1643 ret = EEH_PE_STATE_UNAVAIL; 1644 1645 return ret; 1646 } 1647 EXPORT_SYMBOL_GPL(eeh_pe_get_state); 1648 1649 static int eeh_pe_reenable_devices(struct eeh_pe *pe, bool include_passed) 1650 { 1651 struct eeh_dev *edev, *tmp; 1652 struct pci_dev *pdev; 1653 int ret = 0; 1654 1655 eeh_pe_restore_bars(pe); 1656 1657 /* 1658 * Reenable PCI devices as the devices passed 1659 * through are always enabled before the reset. 1660 */ 1661 eeh_pe_for_each_dev(pe, edev, tmp) { 1662 pdev = eeh_dev_to_pci_dev(edev); 1663 if (!pdev) 1664 continue; 1665 1666 ret = pci_reenable_device(pdev); 1667 if (ret) { 1668 pr_warn("%s: Failure %d reenabling %s\n", 1669 __func__, ret, pci_name(pdev)); 1670 return ret; 1671 } 1672 } 1673 1674 /* The PE is still in frozen state */ 1675 if (include_passed || !eeh_pe_passed(pe)) { 1676 ret = eeh_unfreeze_pe(pe); 1677 } else 1678 pr_info("EEH: Note: Leaving passthrough PHB#%x-PE#%x frozen.\n", 1679 pe->phb->global_number, pe->addr); 1680 if (!ret) 1681 eeh_pe_state_clear(pe, EEH_PE_ISOLATED, include_passed); 1682 return ret; 1683 } 1684 1685 1686 /** 1687 * eeh_pe_reset - Issue PE reset according to specified type 1688 * @pe: EEH PE 1689 * @option: reset type 1690 * 1691 * The routine is called to reset the specified PE with the 1692 * indicated type, either fundamental reset or hot reset. 1693 * PE reset is the most important part for error recovery. 1694 */ 1695 int eeh_pe_reset(struct eeh_pe *pe, int option, bool include_passed) 1696 { 1697 int ret = 0; 1698 1699 /* Invalid PE ? */ 1700 if (!pe) 1701 return -ENODEV; 1702 1703 if (!eeh_ops || !eeh_ops->set_option || !eeh_ops->reset) 1704 return -ENOENT; 1705 1706 switch (option) { 1707 case EEH_RESET_DEACTIVATE: 1708 ret = eeh_ops->reset(pe, option); 1709 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, include_passed); 1710 if (ret) 1711 break; 1712 1713 ret = eeh_pe_reenable_devices(pe, include_passed); 1714 break; 1715 case EEH_RESET_HOT: 1716 case EEH_RESET_FUNDAMENTAL: 1717 /* 1718 * Proactively freeze the PE to drop all MMIO access 1719 * during reset, which should be banned as it's always 1720 * cause recursive EEH error. 1721 */ 1722 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE); 1723 1724 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED); 1725 ret = eeh_ops->reset(pe, option); 1726 break; 1727 default: 1728 pr_debug("%s: Unsupported option %d\n", 1729 __func__, option); 1730 ret = -EINVAL; 1731 } 1732 1733 return ret; 1734 } 1735 EXPORT_SYMBOL_GPL(eeh_pe_reset); 1736 1737 /** 1738 * eeh_pe_configure - Configure PCI bridges after PE reset 1739 * @pe: EEH PE 1740 * 1741 * The routine is called to restore the PCI config space for 1742 * those PCI devices, especially PCI bridges affected by PE 1743 * reset issued previously. 1744 */ 1745 int eeh_pe_configure(struct eeh_pe *pe) 1746 { 1747 int ret = 0; 1748 1749 /* Invalid PE ? */ 1750 if (!pe) 1751 return -ENODEV; 1752 1753 return ret; 1754 } 1755 EXPORT_SYMBOL_GPL(eeh_pe_configure); 1756 1757 /** 1758 * eeh_pe_inject_err - Injecting the specified PCI error to the indicated PE 1759 * @pe: the indicated PE 1760 * @type: error type 1761 * @function: error function 1762 * @addr: address 1763 * @mask: address mask 1764 * 1765 * The routine is called to inject the specified PCI error, which 1766 * is determined by @type and @function, to the indicated PE for 1767 * testing purpose. 1768 */ 1769 int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func, 1770 unsigned long addr, unsigned long mask) 1771 { 1772 /* Invalid PE ? */ 1773 if (!pe) 1774 return -ENODEV; 1775 1776 /* Unsupported operation ? */ 1777 if (!eeh_ops || !eeh_ops->err_inject) 1778 return -ENOENT; 1779 1780 /* Check on PCI error type */ 1781 if (type != EEH_ERR_TYPE_32 && type != EEH_ERR_TYPE_64) 1782 return -EINVAL; 1783 1784 /* Check on PCI error function */ 1785 if (func < EEH_ERR_FUNC_MIN || func > EEH_ERR_FUNC_MAX) 1786 return -EINVAL; 1787 1788 return eeh_ops->err_inject(pe, type, func, addr, mask); 1789 } 1790 EXPORT_SYMBOL_GPL(eeh_pe_inject_err); 1791 1792 static int proc_eeh_show(struct seq_file *m, void *v) 1793 { 1794 if (!eeh_enabled()) { 1795 seq_printf(m, "EEH Subsystem is globally disabled\n"); 1796 seq_printf(m, "eeh_total_mmio_ffs=%llu\n", eeh_stats.total_mmio_ffs); 1797 } else { 1798 seq_printf(m, "EEH Subsystem is enabled\n"); 1799 seq_printf(m, 1800 "no device=%llu\n" 1801 "no device node=%llu\n" 1802 "no config address=%llu\n" 1803 "check not wanted=%llu\n" 1804 "eeh_total_mmio_ffs=%llu\n" 1805 "eeh_false_positives=%llu\n" 1806 "eeh_slot_resets=%llu\n", 1807 eeh_stats.no_device, 1808 eeh_stats.no_dn, 1809 eeh_stats.no_cfg_addr, 1810 eeh_stats.ignored_check, 1811 eeh_stats.total_mmio_ffs, 1812 eeh_stats.false_positives, 1813 eeh_stats.slot_resets); 1814 } 1815 1816 return 0; 1817 } 1818 1819 #ifdef CONFIG_DEBUG_FS 1820 static int eeh_enable_dbgfs_set(void *data, u64 val) 1821 { 1822 if (val) 1823 eeh_clear_flag(EEH_FORCE_DISABLED); 1824 else 1825 eeh_add_flag(EEH_FORCE_DISABLED); 1826 1827 return 0; 1828 } 1829 1830 static int eeh_enable_dbgfs_get(void *data, u64 *val) 1831 { 1832 if (eeh_enabled()) 1833 *val = 0x1ul; 1834 else 1835 *val = 0x0ul; 1836 return 0; 1837 } 1838 1839 DEFINE_DEBUGFS_ATTRIBUTE(eeh_enable_dbgfs_ops, eeh_enable_dbgfs_get, 1840 eeh_enable_dbgfs_set, "0x%llx\n"); 1841 1842 static ssize_t eeh_force_recover_write(struct file *filp, 1843 const char __user *user_buf, 1844 size_t count, loff_t *ppos) 1845 { 1846 struct pci_controller *hose; 1847 uint32_t phbid, pe_no; 1848 struct eeh_pe *pe; 1849 char buf[20]; 1850 int ret; 1851 1852 ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count); 1853 if (!ret) 1854 return -EFAULT; 1855 1856 /* 1857 * When PE is NULL the event is a "special" event. Rather than 1858 * recovering a specific PE it forces the EEH core to scan for failed 1859 * PHBs and recovers each. This needs to be done before any device 1860 * recoveries can occur. 1861 */ 1862 if (!strncmp(buf, "hwcheck", 7)) { 1863 __eeh_send_failure_event(NULL); 1864 return count; 1865 } 1866 1867 ret = sscanf(buf, "%x:%x", &phbid, &pe_no); 1868 if (ret != 2) 1869 return -EINVAL; 1870 1871 hose = pci_find_controller_for_domain(phbid); 1872 if (!hose) 1873 return -ENODEV; 1874 1875 /* Retrieve PE */ 1876 pe = eeh_pe_get(hose, pe_no, 0); 1877 if (!pe) 1878 return -ENODEV; 1879 1880 /* 1881 * We don't do any state checking here since the detection 1882 * process is async to the recovery process. The recovery 1883 * thread *should* not break even if we schedule a recovery 1884 * from an odd state (e.g. PE removed, or recovery of a 1885 * non-isolated PE) 1886 */ 1887 __eeh_send_failure_event(pe); 1888 1889 return ret < 0 ? ret : count; 1890 } 1891 1892 static const struct file_operations eeh_force_recover_fops = { 1893 .open = simple_open, 1894 .llseek = no_llseek, 1895 .write = eeh_force_recover_write, 1896 }; 1897 #endif 1898 1899 static int __init eeh_init_proc(void) 1900 { 1901 if (machine_is(pseries) || machine_is(powernv)) { 1902 proc_create_single("powerpc/eeh", 0, NULL, proc_eeh_show); 1903 #ifdef CONFIG_DEBUG_FS 1904 debugfs_create_file_unsafe("eeh_enable", 0600, 1905 powerpc_debugfs_root, NULL, 1906 &eeh_enable_dbgfs_ops); 1907 debugfs_create_u32("eeh_max_freezes", 0600, 1908 powerpc_debugfs_root, &eeh_max_freezes); 1909 debugfs_create_bool("eeh_disable_recovery", 0600, 1910 powerpc_debugfs_root, 1911 &eeh_debugfs_no_recover); 1912 debugfs_create_file_unsafe("eeh_force_recover", 0600, 1913 powerpc_debugfs_root, NULL, 1914 &eeh_force_recover_fops); 1915 eeh_cache_debugfs_init(); 1916 #endif 1917 } 1918 1919 return 0; 1920 } 1921 __initcall(eeh_init_proc); 1922