1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright IBM Corporation 2001, 2005, 2006 4 * Copyright Dave Engebretsen & Todd Inglett 2001 5 * Copyright Linas Vepstas 2005, 2006 6 * Copyright 2001-2012 IBM Corporation. 7 * 8 * Please address comments and feedback to Linas Vepstas <linas@austin.ibm.com> 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/sched.h> 13 #include <linux/init.h> 14 #include <linux/list.h> 15 #include <linux/pci.h> 16 #include <linux/iommu.h> 17 #include <linux/proc_fs.h> 18 #include <linux/rbtree.h> 19 #include <linux/reboot.h> 20 #include <linux/seq_file.h> 21 #include <linux/spinlock.h> 22 #include <linux/export.h> 23 #include <linux/of.h> 24 25 #include <linux/atomic.h> 26 #include <asm/debugfs.h> 27 #include <asm/eeh.h> 28 #include <asm/eeh_event.h> 29 #include <asm/io.h> 30 #include <asm/iommu.h> 31 #include <asm/machdep.h> 32 #include <asm/ppc-pci.h> 33 #include <asm/rtas.h> 34 #include <asm/pte-walk.h> 35 36 37 /** Overview: 38 * EEH, or "Enhanced Error Handling" is a PCI bridge technology for 39 * dealing with PCI bus errors that can't be dealt with within the 40 * usual PCI framework, except by check-stopping the CPU. Systems 41 * that are designed for high-availability/reliability cannot afford 42 * to crash due to a "mere" PCI error, thus the need for EEH. 43 * An EEH-capable bridge operates by converting a detected error 44 * into a "slot freeze", taking the PCI adapter off-line, making 45 * the slot behave, from the OS'es point of view, as if the slot 46 * were "empty": all reads return 0xff's and all writes are silently 47 * ignored. EEH slot isolation events can be triggered by parity 48 * errors on the address or data busses (e.g. during posted writes), 49 * which in turn might be caused by low voltage on the bus, dust, 50 * vibration, humidity, radioactivity or plain-old failed hardware. 51 * 52 * Note, however, that one of the leading causes of EEH slot 53 * freeze events are buggy device drivers, buggy device microcode, 54 * or buggy device hardware. This is because any attempt by the 55 * device to bus-master data to a memory address that is not 56 * assigned to the device will trigger a slot freeze. (The idea 57 * is to prevent devices-gone-wild from corrupting system memory). 58 * Buggy hardware/drivers will have a miserable time co-existing 59 * with EEH. 60 * 61 * Ideally, a PCI device driver, when suspecting that an isolation 62 * event has occurred (e.g. by reading 0xff's), will then ask EEH 63 * whether this is the case, and then take appropriate steps to 64 * reset the PCI slot, the PCI device, and then resume operations. 65 * However, until that day, the checking is done here, with the 66 * eeh_check_failure() routine embedded in the MMIO macros. If 67 * the slot is found to be isolated, an "EEH Event" is synthesized 68 * and sent out for processing. 69 */ 70 71 /* If a device driver keeps reading an MMIO register in an interrupt 72 * handler after a slot isolation event, it might be broken. 73 * This sets the threshold for how many read attempts we allow 74 * before printing an error message. 75 */ 76 #define EEH_MAX_FAILS 2100000 77 78 /* Time to wait for a PCI slot to report status, in milliseconds */ 79 #define PCI_BUS_RESET_WAIT_MSEC (5*60*1000) 80 81 /* 82 * EEH probe mode support, which is part of the flags, 83 * is to support multiple platforms for EEH. Some platforms 84 * like pSeries do PCI emunation based on device tree. 85 * However, other platforms like powernv probe PCI devices 86 * from hardware. The flag is used to distinguish that. 87 * In addition, struct eeh_ops::probe would be invoked for 88 * particular OF node or PCI device so that the corresponding 89 * PE would be created there. 90 */ 91 int eeh_subsystem_flags; 92 EXPORT_SYMBOL(eeh_subsystem_flags); 93 94 /* 95 * EEH allowed maximal frozen times. If one particular PE's 96 * frozen count in last hour exceeds this limit, the PE will 97 * be forced to be offline permanently. 98 */ 99 u32 eeh_max_freezes = 5; 100 101 /* 102 * Controls whether a recovery event should be scheduled when an 103 * isolated device is discovered. This is only really useful for 104 * debugging problems with the EEH core. 105 */ 106 bool eeh_debugfs_no_recover; 107 108 /* Platform dependent EEH operations */ 109 struct eeh_ops *eeh_ops = NULL; 110 111 /* Lock to avoid races due to multiple reports of an error */ 112 DEFINE_RAW_SPINLOCK(confirm_error_lock); 113 EXPORT_SYMBOL_GPL(confirm_error_lock); 114 115 /* Lock to protect passed flags */ 116 static DEFINE_MUTEX(eeh_dev_mutex); 117 118 /* Buffer for reporting pci register dumps. Its here in BSS, and 119 * not dynamically alloced, so that it ends up in RMO where RTAS 120 * can access it. 121 */ 122 #define EEH_PCI_REGS_LOG_LEN 8192 123 static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN]; 124 125 /* 126 * The struct is used to maintain the EEH global statistic 127 * information. Besides, the EEH global statistics will be 128 * exported to user space through procfs 129 */ 130 struct eeh_stats { 131 u64 no_device; /* PCI device not found */ 132 u64 no_dn; /* OF node not found */ 133 u64 no_cfg_addr; /* Config address not found */ 134 u64 ignored_check; /* EEH check skipped */ 135 u64 total_mmio_ffs; /* Total EEH checks */ 136 u64 false_positives; /* Unnecessary EEH checks */ 137 u64 slot_resets; /* PE reset */ 138 }; 139 140 static struct eeh_stats eeh_stats; 141 142 static int __init eeh_setup(char *str) 143 { 144 if (!strcmp(str, "off")) 145 eeh_add_flag(EEH_FORCE_DISABLED); 146 else if (!strcmp(str, "early_log")) 147 eeh_add_flag(EEH_EARLY_DUMP_LOG); 148 149 return 1; 150 } 151 __setup("eeh=", eeh_setup); 152 153 void eeh_show_enabled(void) 154 { 155 if (eeh_has_flag(EEH_FORCE_DISABLED)) 156 pr_info("EEH: Recovery disabled by kernel parameter.\n"); 157 else if (eeh_has_flag(EEH_ENABLED)) 158 pr_info("EEH: Capable adapter found: recovery enabled.\n"); 159 else 160 pr_info("EEH: No capable adapters found: recovery disabled.\n"); 161 } 162 163 /* 164 * This routine captures assorted PCI configuration space data 165 * for the indicated PCI device, and puts them into a buffer 166 * for RTAS error logging. 167 */ 168 static size_t eeh_dump_dev_log(struct eeh_dev *edev, char *buf, size_t len) 169 { 170 u32 cfg; 171 int cap, i; 172 int n = 0, l = 0; 173 char buffer[128]; 174 175 n += scnprintf(buf+n, len-n, "%04x:%02x:%02x.%01x\n", 176 edev->pe->phb->global_number, edev->bdfn >> 8, 177 PCI_SLOT(edev->bdfn), PCI_FUNC(edev->bdfn)); 178 pr_warn("EEH: of node=%04x:%02x:%02x.%01x\n", 179 edev->pe->phb->global_number, edev->bdfn >> 8, 180 PCI_SLOT(edev->bdfn), PCI_FUNC(edev->bdfn)); 181 182 eeh_ops->read_config(edev, PCI_VENDOR_ID, 4, &cfg); 183 n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg); 184 pr_warn("EEH: PCI device/vendor: %08x\n", cfg); 185 186 eeh_ops->read_config(edev, PCI_COMMAND, 4, &cfg); 187 n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg); 188 pr_warn("EEH: PCI cmd/status register: %08x\n", cfg); 189 190 /* Gather bridge-specific registers */ 191 if (edev->mode & EEH_DEV_BRIDGE) { 192 eeh_ops->read_config(edev, PCI_SEC_STATUS, 2, &cfg); 193 n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg); 194 pr_warn("EEH: Bridge secondary status: %04x\n", cfg); 195 196 eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &cfg); 197 n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg); 198 pr_warn("EEH: Bridge control: %04x\n", cfg); 199 } 200 201 /* Dump out the PCI-X command and status regs */ 202 cap = edev->pcix_cap; 203 if (cap) { 204 eeh_ops->read_config(edev, cap, 4, &cfg); 205 n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg); 206 pr_warn("EEH: PCI-X cmd: %08x\n", cfg); 207 208 eeh_ops->read_config(edev, cap+4, 4, &cfg); 209 n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg); 210 pr_warn("EEH: PCI-X status: %08x\n", cfg); 211 } 212 213 /* If PCI-E capable, dump PCI-E cap 10 */ 214 cap = edev->pcie_cap; 215 if (cap) { 216 n += scnprintf(buf+n, len-n, "pci-e cap10:\n"); 217 pr_warn("EEH: PCI-E capabilities and status follow:\n"); 218 219 for (i=0; i<=8; i++) { 220 eeh_ops->read_config(edev, cap+4*i, 4, &cfg); 221 n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); 222 223 if ((i % 4) == 0) { 224 if (i != 0) 225 pr_warn("%s\n", buffer); 226 227 l = scnprintf(buffer, sizeof(buffer), 228 "EEH: PCI-E %02x: %08x ", 229 4*i, cfg); 230 } else { 231 l += scnprintf(buffer+l, sizeof(buffer)-l, 232 "%08x ", cfg); 233 } 234 235 } 236 237 pr_warn("%s\n", buffer); 238 } 239 240 /* If AER capable, dump it */ 241 cap = edev->aer_cap; 242 if (cap) { 243 n += scnprintf(buf+n, len-n, "pci-e AER:\n"); 244 pr_warn("EEH: PCI-E AER capability register set follows:\n"); 245 246 for (i=0; i<=13; i++) { 247 eeh_ops->read_config(edev, cap+4*i, 4, &cfg); 248 n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); 249 250 if ((i % 4) == 0) { 251 if (i != 0) 252 pr_warn("%s\n", buffer); 253 254 l = scnprintf(buffer, sizeof(buffer), 255 "EEH: PCI-E AER %02x: %08x ", 256 4*i, cfg); 257 } else { 258 l += scnprintf(buffer+l, sizeof(buffer)-l, 259 "%08x ", cfg); 260 } 261 } 262 263 pr_warn("%s\n", buffer); 264 } 265 266 return n; 267 } 268 269 static void *eeh_dump_pe_log(struct eeh_pe *pe, void *flag) 270 { 271 struct eeh_dev *edev, *tmp; 272 size_t *plen = flag; 273 274 eeh_pe_for_each_dev(pe, edev, tmp) 275 *plen += eeh_dump_dev_log(edev, pci_regs_buf + *plen, 276 EEH_PCI_REGS_LOG_LEN - *plen); 277 278 return NULL; 279 } 280 281 /** 282 * eeh_slot_error_detail - Generate combined log including driver log and error log 283 * @pe: EEH PE 284 * @severity: temporary or permanent error log 285 * 286 * This routine should be called to generate the combined log, which 287 * is comprised of driver log and error log. The driver log is figured 288 * out from the config space of the corresponding PCI device, while 289 * the error log is fetched through platform dependent function call. 290 */ 291 void eeh_slot_error_detail(struct eeh_pe *pe, int severity) 292 { 293 size_t loglen = 0; 294 295 /* 296 * When the PHB is fenced or dead, it's pointless to collect 297 * the data from PCI config space because it should return 298 * 0xFF's. For ER, we still retrieve the data from the PCI 299 * config space. 300 * 301 * For pHyp, we have to enable IO for log retrieval. Otherwise, 302 * 0xFF's is always returned from PCI config space. 303 * 304 * When the @severity is EEH_LOG_PERM, the PE is going to be 305 * removed. Prior to that, the drivers for devices included in 306 * the PE will be closed. The drivers rely on working IO path 307 * to bring the devices to quiet state. Otherwise, PCI traffic 308 * from those devices after they are removed is like to cause 309 * another unexpected EEH error. 310 */ 311 if (!(pe->type & EEH_PE_PHB)) { 312 if (eeh_has_flag(EEH_ENABLE_IO_FOR_LOG) || 313 severity == EEH_LOG_PERM) 314 eeh_pci_enable(pe, EEH_OPT_THAW_MMIO); 315 316 /* 317 * The config space of some PCI devices can't be accessed 318 * when their PEs are in frozen state. Otherwise, fenced 319 * PHB might be seen. Those PEs are identified with flag 320 * EEH_PE_CFG_RESTRICTED, indicating EEH_PE_CFG_BLOCKED 321 * is set automatically when the PE is put to EEH_PE_ISOLATED. 322 * 323 * Restoring BARs possibly triggers PCI config access in 324 * (OPAL) firmware and then causes fenced PHB. If the 325 * PCI config is blocked with flag EEH_PE_CFG_BLOCKED, it's 326 * pointless to restore BARs and dump config space. 327 */ 328 eeh_ops->configure_bridge(pe); 329 if (!(pe->state & EEH_PE_CFG_BLOCKED)) { 330 eeh_pe_restore_bars(pe); 331 332 pci_regs_buf[0] = 0; 333 eeh_pe_traverse(pe, eeh_dump_pe_log, &loglen); 334 } 335 } 336 337 eeh_ops->get_log(pe, severity, pci_regs_buf, loglen); 338 } 339 340 /** 341 * eeh_token_to_phys - Convert EEH address token to phys address 342 * @token: I/O token, should be address in the form 0xA.... 343 * 344 * This routine should be called to convert virtual I/O address 345 * to physical one. 346 */ 347 static inline unsigned long eeh_token_to_phys(unsigned long token) 348 { 349 pte_t *ptep; 350 unsigned long pa; 351 int hugepage_shift; 352 353 /* 354 * We won't find hugepages here(this is iomem). Hence we are not 355 * worried about _PAGE_SPLITTING/collapse. Also we will not hit 356 * page table free, because of init_mm. 357 */ 358 ptep = find_init_mm_pte(token, &hugepage_shift); 359 if (!ptep) 360 return token; 361 362 pa = pte_pfn(*ptep); 363 364 /* On radix we can do hugepage mappings for io, so handle that */ 365 if (hugepage_shift) { 366 pa <<= hugepage_shift; 367 pa |= token & ((1ul << hugepage_shift) - 1); 368 } else { 369 pa <<= PAGE_SHIFT; 370 pa |= token & (PAGE_SIZE - 1); 371 } 372 373 return pa; 374 } 375 376 /* 377 * On PowerNV platform, we might already have fenced PHB there. 378 * For that case, it's meaningless to recover frozen PE. Intead, 379 * We have to handle fenced PHB firstly. 380 */ 381 static int eeh_phb_check_failure(struct eeh_pe *pe) 382 { 383 struct eeh_pe *phb_pe; 384 unsigned long flags; 385 int ret; 386 387 if (!eeh_has_flag(EEH_PROBE_MODE_DEV)) 388 return -EPERM; 389 390 /* Find the PHB PE */ 391 phb_pe = eeh_phb_pe_get(pe->phb); 392 if (!phb_pe) { 393 pr_warn("%s Can't find PE for PHB#%x\n", 394 __func__, pe->phb->global_number); 395 return -EEXIST; 396 } 397 398 /* If the PHB has been in problematic state */ 399 eeh_serialize_lock(&flags); 400 if (phb_pe->state & EEH_PE_ISOLATED) { 401 ret = 0; 402 goto out; 403 } 404 405 /* Check PHB state */ 406 ret = eeh_ops->get_state(phb_pe, NULL); 407 if ((ret < 0) || 408 (ret == EEH_STATE_NOT_SUPPORT) || eeh_state_active(ret)) { 409 ret = 0; 410 goto out; 411 } 412 413 /* Isolate the PHB and send event */ 414 eeh_pe_mark_isolated(phb_pe); 415 eeh_serialize_unlock(flags); 416 417 pr_debug("EEH: PHB#%x failure detected, location: %s\n", 418 phb_pe->phb->global_number, eeh_pe_loc_get(phb_pe)); 419 eeh_send_failure_event(phb_pe); 420 return 1; 421 out: 422 eeh_serialize_unlock(flags); 423 return ret; 424 } 425 426 /** 427 * eeh_dev_check_failure - Check if all 1's data is due to EEH slot freeze 428 * @edev: eeh device 429 * 430 * Check for an EEH failure for the given device node. Call this 431 * routine if the result of a read was all 0xff's and you want to 432 * find out if this is due to an EEH slot freeze. This routine 433 * will query firmware for the EEH status. 434 * 435 * Returns 0 if there has not been an EEH error; otherwise returns 436 * a non-zero value and queues up a slot isolation event notification. 437 * 438 * It is safe to call this routine in an interrupt context. 439 */ 440 int eeh_dev_check_failure(struct eeh_dev *edev) 441 { 442 int ret; 443 unsigned long flags; 444 struct device_node *dn; 445 struct pci_dev *dev; 446 struct eeh_pe *pe, *parent_pe; 447 int rc = 0; 448 const char *location = NULL; 449 450 eeh_stats.total_mmio_ffs++; 451 452 if (!eeh_enabled()) 453 return 0; 454 455 if (!edev) { 456 eeh_stats.no_dn++; 457 return 0; 458 } 459 dev = eeh_dev_to_pci_dev(edev); 460 pe = eeh_dev_to_pe(edev); 461 462 /* Access to IO BARs might get this far and still not want checking. */ 463 if (!pe) { 464 eeh_stats.ignored_check++; 465 eeh_edev_dbg(edev, "Ignored check\n"); 466 return 0; 467 } 468 469 if (!pe->addr) { 470 eeh_stats.no_cfg_addr++; 471 return 0; 472 } 473 474 /* 475 * On PowerNV platform, we might already have fenced PHB 476 * there and we need take care of that firstly. 477 */ 478 ret = eeh_phb_check_failure(pe); 479 if (ret > 0) 480 return ret; 481 482 /* 483 * If the PE isn't owned by us, we shouldn't check the 484 * state. Instead, let the owner handle it if the PE has 485 * been frozen. 486 */ 487 if (eeh_pe_passed(pe)) 488 return 0; 489 490 /* If we already have a pending isolation event for this 491 * slot, we know it's bad already, we don't need to check. 492 * Do this checking under a lock; as multiple PCI devices 493 * in one slot might report errors simultaneously, and we 494 * only want one error recovery routine running. 495 */ 496 eeh_serialize_lock(&flags); 497 rc = 1; 498 if (pe->state & EEH_PE_ISOLATED) { 499 pe->check_count++; 500 if (pe->check_count == EEH_MAX_FAILS) { 501 dn = pci_device_to_OF_node(dev); 502 if (dn) 503 location = of_get_property(dn, "ibm,loc-code", 504 NULL); 505 eeh_edev_err(edev, "%d reads ignored for recovering device at location=%s driver=%s\n", 506 pe->check_count, 507 location ? location : "unknown", 508 eeh_driver_name(dev)); 509 eeh_edev_err(edev, "Might be infinite loop in %s driver\n", 510 eeh_driver_name(dev)); 511 dump_stack(); 512 } 513 goto dn_unlock; 514 } 515 516 /* 517 * Now test for an EEH failure. This is VERY expensive. 518 * Note that the eeh_config_addr may be a parent device 519 * in the case of a device behind a bridge, or it may be 520 * function zero of a multi-function device. 521 * In any case they must share a common PHB. 522 */ 523 ret = eeh_ops->get_state(pe, NULL); 524 525 /* Note that config-io to empty slots may fail; 526 * they are empty when they don't have children. 527 * We will punt with the following conditions: Failure to get 528 * PE's state, EEH not support and Permanently unavailable 529 * state, PE is in good state. 530 */ 531 if ((ret < 0) || 532 (ret == EEH_STATE_NOT_SUPPORT) || eeh_state_active(ret)) { 533 eeh_stats.false_positives++; 534 pe->false_positives++; 535 rc = 0; 536 goto dn_unlock; 537 } 538 539 /* 540 * It should be corner case that the parent PE has been 541 * put into frozen state as well. We should take care 542 * that at first. 543 */ 544 parent_pe = pe->parent; 545 while (parent_pe) { 546 /* Hit the ceiling ? */ 547 if (parent_pe->type & EEH_PE_PHB) 548 break; 549 550 /* Frozen parent PE ? */ 551 ret = eeh_ops->get_state(parent_pe, NULL); 552 if (ret > 0 && !eeh_state_active(ret)) { 553 pe = parent_pe; 554 pr_err("EEH: Failure of PHB#%x-PE#%x will be handled at parent PHB#%x-PE#%x.\n", 555 pe->phb->global_number, pe->addr, 556 pe->phb->global_number, parent_pe->addr); 557 } 558 559 /* Next parent level */ 560 parent_pe = parent_pe->parent; 561 } 562 563 eeh_stats.slot_resets++; 564 565 /* Avoid repeated reports of this failure, including problems 566 * with other functions on this device, and functions under 567 * bridges. 568 */ 569 eeh_pe_mark_isolated(pe); 570 eeh_serialize_unlock(flags); 571 572 /* Most EEH events are due to device driver bugs. Having 573 * a stack trace will help the device-driver authors figure 574 * out what happened. So print that out. 575 */ 576 pr_debug("EEH: %s: Frozen PHB#%x-PE#%x detected\n", 577 __func__, pe->phb->global_number, pe->addr); 578 eeh_send_failure_event(pe); 579 580 return 1; 581 582 dn_unlock: 583 eeh_serialize_unlock(flags); 584 return rc; 585 } 586 587 EXPORT_SYMBOL_GPL(eeh_dev_check_failure); 588 589 /** 590 * eeh_check_failure - Check if all 1's data is due to EEH slot freeze 591 * @token: I/O address 592 * 593 * Check for an EEH failure at the given I/O address. Call this 594 * routine if the result of a read was all 0xff's and you want to 595 * find out if this is due to an EEH slot freeze event. This routine 596 * will query firmware for the EEH status. 597 * 598 * Note this routine is safe to call in an interrupt context. 599 */ 600 int eeh_check_failure(const volatile void __iomem *token) 601 { 602 unsigned long addr; 603 struct eeh_dev *edev; 604 605 /* Finding the phys addr + pci device; this is pretty quick. */ 606 addr = eeh_token_to_phys((unsigned long __force) token); 607 edev = eeh_addr_cache_get_dev(addr); 608 if (!edev) { 609 eeh_stats.no_device++; 610 return 0; 611 } 612 613 return eeh_dev_check_failure(edev); 614 } 615 EXPORT_SYMBOL(eeh_check_failure); 616 617 618 /** 619 * eeh_pci_enable - Enable MMIO or DMA transfers for this slot 620 * @pe: EEH PE 621 * 622 * This routine should be called to reenable frozen MMIO or DMA 623 * so that it would work correctly again. It's useful while doing 624 * recovery or log collection on the indicated device. 625 */ 626 int eeh_pci_enable(struct eeh_pe *pe, int function) 627 { 628 int active_flag, rc; 629 630 /* 631 * pHyp doesn't allow to enable IO or DMA on unfrozen PE. 632 * Also, it's pointless to enable them on unfrozen PE. So 633 * we have to check before enabling IO or DMA. 634 */ 635 switch (function) { 636 case EEH_OPT_THAW_MMIO: 637 active_flag = EEH_STATE_MMIO_ACTIVE | EEH_STATE_MMIO_ENABLED; 638 break; 639 case EEH_OPT_THAW_DMA: 640 active_flag = EEH_STATE_DMA_ACTIVE; 641 break; 642 case EEH_OPT_DISABLE: 643 case EEH_OPT_ENABLE: 644 case EEH_OPT_FREEZE_PE: 645 active_flag = 0; 646 break; 647 default: 648 pr_warn("%s: Invalid function %d\n", 649 __func__, function); 650 return -EINVAL; 651 } 652 653 /* 654 * Check if IO or DMA has been enabled before 655 * enabling them. 656 */ 657 if (active_flag) { 658 rc = eeh_ops->get_state(pe, NULL); 659 if (rc < 0) 660 return rc; 661 662 /* Needn't enable it at all */ 663 if (rc == EEH_STATE_NOT_SUPPORT) 664 return 0; 665 666 /* It's already enabled */ 667 if (rc & active_flag) 668 return 0; 669 } 670 671 672 /* Issue the request */ 673 rc = eeh_ops->set_option(pe, function); 674 if (rc) 675 pr_warn("%s: Unexpected state change %d on " 676 "PHB#%x-PE#%x, err=%d\n", 677 __func__, function, pe->phb->global_number, 678 pe->addr, rc); 679 680 /* Check if the request is finished successfully */ 681 if (active_flag) { 682 rc = eeh_wait_state(pe, PCI_BUS_RESET_WAIT_MSEC); 683 if (rc < 0) 684 return rc; 685 686 if (rc & active_flag) 687 return 0; 688 689 return -EIO; 690 } 691 692 return rc; 693 } 694 695 static void eeh_disable_and_save_dev_state(struct eeh_dev *edev, 696 void *userdata) 697 { 698 struct pci_dev *pdev = eeh_dev_to_pci_dev(edev); 699 struct pci_dev *dev = userdata; 700 701 /* 702 * The caller should have disabled and saved the 703 * state for the specified device 704 */ 705 if (!pdev || pdev == dev) 706 return; 707 708 /* Ensure we have D0 power state */ 709 pci_set_power_state(pdev, PCI_D0); 710 711 /* Save device state */ 712 pci_save_state(pdev); 713 714 /* 715 * Disable device to avoid any DMA traffic and 716 * interrupt from the device 717 */ 718 pci_write_config_word(pdev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); 719 } 720 721 static void eeh_restore_dev_state(struct eeh_dev *edev, void *userdata) 722 { 723 struct pci_dev *pdev = eeh_dev_to_pci_dev(edev); 724 struct pci_dev *dev = userdata; 725 726 if (!pdev) 727 return; 728 729 /* Apply customization from firmware */ 730 if (eeh_ops->restore_config) 731 eeh_ops->restore_config(edev); 732 733 /* The caller should restore state for the specified device */ 734 if (pdev != dev) 735 pci_restore_state(pdev); 736 } 737 738 /** 739 * pcibios_set_pcie_reset_state - Set PCI-E reset state 740 * @dev: pci device struct 741 * @state: reset state to enter 742 * 743 * Return value: 744 * 0 if success 745 */ 746 int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) 747 { 748 struct eeh_dev *edev = pci_dev_to_eeh_dev(dev); 749 struct eeh_pe *pe = eeh_dev_to_pe(edev); 750 751 if (!pe) { 752 pr_err("%s: No PE found on PCI device %s\n", 753 __func__, pci_name(dev)); 754 return -EINVAL; 755 } 756 757 switch (state) { 758 case pcie_deassert_reset: 759 eeh_ops->reset(pe, EEH_RESET_DEACTIVATE); 760 eeh_unfreeze_pe(pe); 761 if (!(pe->type & EEH_PE_VF)) 762 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true); 763 eeh_pe_dev_traverse(pe, eeh_restore_dev_state, dev); 764 eeh_pe_state_clear(pe, EEH_PE_ISOLATED, true); 765 break; 766 case pcie_hot_reset: 767 eeh_pe_mark_isolated(pe); 768 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true); 769 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE); 770 eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev); 771 if (!(pe->type & EEH_PE_VF)) 772 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED); 773 eeh_ops->reset(pe, EEH_RESET_HOT); 774 break; 775 case pcie_warm_reset: 776 eeh_pe_mark_isolated(pe); 777 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true); 778 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE); 779 eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev); 780 if (!(pe->type & EEH_PE_VF)) 781 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED); 782 eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL); 783 break; 784 default: 785 eeh_pe_state_clear(pe, EEH_PE_ISOLATED | EEH_PE_CFG_BLOCKED, true); 786 return -EINVAL; 787 }; 788 789 return 0; 790 } 791 792 /** 793 * eeh_set_pe_freset - Check the required reset for the indicated device 794 * @data: EEH device 795 * @flag: return value 796 * 797 * Each device might have its preferred reset type: fundamental or 798 * hot reset. The routine is used to collected the information for 799 * the indicated device and its children so that the bunch of the 800 * devices could be reset properly. 801 */ 802 static void eeh_set_dev_freset(struct eeh_dev *edev, void *flag) 803 { 804 struct pci_dev *dev; 805 unsigned int *freset = (unsigned int *)flag; 806 807 dev = eeh_dev_to_pci_dev(edev); 808 if (dev) 809 *freset |= dev->needs_freset; 810 } 811 812 static void eeh_pe_refreeze_passed(struct eeh_pe *root) 813 { 814 struct eeh_pe *pe; 815 int state; 816 817 eeh_for_each_pe(root, pe) { 818 if (eeh_pe_passed(pe)) { 819 state = eeh_ops->get_state(pe, NULL); 820 if (state & 821 (EEH_STATE_MMIO_ACTIVE | EEH_STATE_MMIO_ENABLED)) { 822 pr_info("EEH: Passed-through PE PHB#%x-PE#%x was thawed by reset, re-freezing for safety.\n", 823 pe->phb->global_number, pe->addr); 824 eeh_pe_set_option(pe, EEH_OPT_FREEZE_PE); 825 } 826 } 827 } 828 } 829 830 /** 831 * eeh_pe_reset_full - Complete a full reset process on the indicated PE 832 * @pe: EEH PE 833 * 834 * This function executes a full reset procedure on a PE, including setting 835 * the appropriate flags, performing a fundamental or hot reset, and then 836 * deactivating the reset status. It is designed to be used within the EEH 837 * subsystem, as opposed to eeh_pe_reset which is exported to drivers and 838 * only performs a single operation at a time. 839 * 840 * This function will attempt to reset a PE three times before failing. 841 */ 842 int eeh_pe_reset_full(struct eeh_pe *pe, bool include_passed) 843 { 844 int reset_state = (EEH_PE_RESET | EEH_PE_CFG_BLOCKED); 845 int type = EEH_RESET_HOT; 846 unsigned int freset = 0; 847 int i, state = 0, ret; 848 849 /* 850 * Determine the type of reset to perform - hot or fundamental. 851 * Hot reset is the default operation, unless any device under the 852 * PE requires a fundamental reset. 853 */ 854 eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset); 855 856 if (freset) 857 type = EEH_RESET_FUNDAMENTAL; 858 859 /* Mark the PE as in reset state and block config space accesses */ 860 eeh_pe_state_mark(pe, reset_state); 861 862 /* Make three attempts at resetting the bus */ 863 for (i = 0; i < 3; i++) { 864 ret = eeh_pe_reset(pe, type, include_passed); 865 if (!ret) 866 ret = eeh_pe_reset(pe, EEH_RESET_DEACTIVATE, 867 include_passed); 868 if (ret) { 869 ret = -EIO; 870 pr_warn("EEH: Failure %d resetting PHB#%x-PE#%x (attempt %d)\n\n", 871 state, pe->phb->global_number, pe->addr, i + 1); 872 continue; 873 } 874 if (i) 875 pr_warn("EEH: PHB#%x-PE#%x: Successful reset (attempt %d)\n", 876 pe->phb->global_number, pe->addr, i + 1); 877 878 /* Wait until the PE is in a functioning state */ 879 state = eeh_wait_state(pe, PCI_BUS_RESET_WAIT_MSEC); 880 if (state < 0) { 881 pr_warn("EEH: Unrecoverable slot failure on PHB#%x-PE#%x", 882 pe->phb->global_number, pe->addr); 883 ret = -ENOTRECOVERABLE; 884 break; 885 } 886 if (eeh_state_active(state)) 887 break; 888 else 889 pr_warn("EEH: PHB#%x-PE#%x: Slot inactive after reset: 0x%x (attempt %d)\n", 890 pe->phb->global_number, pe->addr, state, i + 1); 891 } 892 893 /* Resetting the PE may have unfrozen child PEs. If those PEs have been 894 * (potentially) passed through to a guest, re-freeze them: 895 */ 896 if (!include_passed) 897 eeh_pe_refreeze_passed(pe); 898 899 eeh_pe_state_clear(pe, reset_state, true); 900 return ret; 901 } 902 903 /** 904 * eeh_save_bars - Save device bars 905 * @edev: PCI device associated EEH device 906 * 907 * Save the values of the device bars. Unlike the restore 908 * routine, this routine is *not* recursive. This is because 909 * PCI devices are added individually; but, for the restore, 910 * an entire slot is reset at a time. 911 */ 912 void eeh_save_bars(struct eeh_dev *edev) 913 { 914 int i; 915 916 if (!edev) 917 return; 918 919 for (i = 0; i < 16; i++) 920 eeh_ops->read_config(edev, i * 4, 4, &edev->config_space[i]); 921 922 /* 923 * For PCI bridges including root port, we need enable bus 924 * master explicitly. Otherwise, it can't fetch IODA table 925 * entries correctly. So we cache the bit in advance so that 926 * we can restore it after reset, either PHB range or PE range. 927 */ 928 if (edev->mode & EEH_DEV_BRIDGE) 929 edev->config_space[1] |= PCI_COMMAND_MASTER; 930 } 931 932 static int eeh_reboot_notifier(struct notifier_block *nb, 933 unsigned long action, void *unused) 934 { 935 eeh_clear_flag(EEH_ENABLED); 936 return NOTIFY_DONE; 937 } 938 939 static struct notifier_block eeh_reboot_nb = { 940 .notifier_call = eeh_reboot_notifier, 941 }; 942 943 static int eeh_device_notifier(struct notifier_block *nb, 944 unsigned long action, void *data) 945 { 946 struct device *dev = data; 947 948 switch (action) { 949 /* 950 * Note: It's not possible to perform EEH device addition (i.e. 951 * {pseries,pnv}_pcibios_bus_add_device()) here because it depends on 952 * the device's resources, which have not yet been set up. 953 */ 954 case BUS_NOTIFY_DEL_DEVICE: 955 eeh_remove_device(to_pci_dev(dev)); 956 break; 957 default: 958 break; 959 } 960 return NOTIFY_DONE; 961 } 962 963 static struct notifier_block eeh_device_nb = { 964 .notifier_call = eeh_device_notifier, 965 }; 966 967 /** 968 * eeh_init - System wide EEH initialization 969 * 970 * It's the platform's job to call this from an arch_initcall(). 971 */ 972 int eeh_init(struct eeh_ops *ops) 973 { 974 struct pci_controller *hose, *tmp; 975 int ret = 0; 976 977 /* the platform should only initialise EEH once */ 978 if (WARN_ON(eeh_ops)) 979 return -EEXIST; 980 if (WARN_ON(!ops)) 981 return -ENOENT; 982 eeh_ops = ops; 983 984 /* Register reboot notifier */ 985 ret = register_reboot_notifier(&eeh_reboot_nb); 986 if (ret) { 987 pr_warn("%s: Failed to register reboot notifier (%d)\n", 988 __func__, ret); 989 return ret; 990 } 991 992 ret = bus_register_notifier(&pci_bus_type, &eeh_device_nb); 993 if (ret) { 994 pr_warn("%s: Failed to register bus notifier (%d)\n", 995 __func__, ret); 996 return ret; 997 } 998 999 /* Initialize PHB PEs */ 1000 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 1001 eeh_phb_pe_create(hose); 1002 1003 eeh_addr_cache_init(); 1004 1005 /* Initialize EEH event */ 1006 return eeh_event_init(); 1007 } 1008 1009 /** 1010 * eeh_probe_device() - Perform EEH initialization for the indicated pci device 1011 * @dev: pci device for which to set up EEH 1012 * 1013 * This routine must be used to complete EEH initialization for PCI 1014 * devices that were added after system boot (e.g. hotplug, dlpar). 1015 */ 1016 void eeh_probe_device(struct pci_dev *dev) 1017 { 1018 struct eeh_dev *edev; 1019 1020 pr_debug("EEH: Adding device %s\n", pci_name(dev)); 1021 1022 /* 1023 * pci_dev_to_eeh_dev() can only work if eeh_probe_dev() was 1024 * already called for this device. 1025 */ 1026 if (WARN_ON_ONCE(pci_dev_to_eeh_dev(dev))) { 1027 pci_dbg(dev, "Already bound to an eeh_dev!\n"); 1028 return; 1029 } 1030 1031 edev = eeh_ops->probe(dev); 1032 if (!edev) { 1033 pr_debug("EEH: Adding device failed\n"); 1034 return; 1035 } 1036 1037 /* 1038 * FIXME: We rely on pcibios_release_device() to remove the 1039 * existing EEH state. The release function is only called if 1040 * the pci_dev's refcount drops to zero so if something is 1041 * keeping a ref to a device (e.g. a filesystem) we need to 1042 * remove the old EEH state. 1043 * 1044 * FIXME: HEY MA, LOOK AT ME, NO LOCKING! 1045 */ 1046 if (edev->pdev && edev->pdev != dev) { 1047 eeh_pe_tree_remove(edev); 1048 eeh_addr_cache_rmv_dev(edev->pdev); 1049 eeh_sysfs_remove_device(edev->pdev); 1050 1051 /* 1052 * We definitely should have the PCI device removed 1053 * though it wasn't correctly. So we needn't call 1054 * into error handler afterwards. 1055 */ 1056 edev->mode |= EEH_DEV_NO_HANDLER; 1057 } 1058 1059 /* bind the pdev and the edev together */ 1060 edev->pdev = dev; 1061 dev->dev.archdata.edev = edev; 1062 eeh_addr_cache_insert_dev(dev); 1063 eeh_sysfs_add_device(dev); 1064 } 1065 1066 /** 1067 * eeh_remove_device - Undo EEH setup for the indicated pci device 1068 * @dev: pci device to be removed 1069 * 1070 * This routine should be called when a device is removed from 1071 * a running system (e.g. by hotplug or dlpar). It unregisters 1072 * the PCI device from the EEH subsystem. I/O errors affecting 1073 * this device will no longer be detected after this call; thus, 1074 * i/o errors affecting this slot may leave this device unusable. 1075 */ 1076 void eeh_remove_device(struct pci_dev *dev) 1077 { 1078 struct eeh_dev *edev; 1079 1080 if (!dev || !eeh_enabled()) 1081 return; 1082 edev = pci_dev_to_eeh_dev(dev); 1083 1084 /* Unregister the device with the EEH/PCI address search system */ 1085 dev_dbg(&dev->dev, "EEH: Removing device\n"); 1086 1087 if (!edev || !edev->pdev || !edev->pe) { 1088 dev_dbg(&dev->dev, "EEH: Device not referenced!\n"); 1089 return; 1090 } 1091 1092 /* 1093 * During the hotplug for EEH error recovery, we need the EEH 1094 * device attached to the parent PE in order for BAR restore 1095 * a bit later. So we keep it for BAR restore and remove it 1096 * from the parent PE during the BAR resotre. 1097 */ 1098 edev->pdev = NULL; 1099 1100 /* 1101 * eeh_sysfs_remove_device() uses pci_dev_to_eeh_dev() so we need to 1102 * remove the sysfs files before clearing dev.archdata.edev 1103 */ 1104 if (edev->mode & EEH_DEV_SYSFS) 1105 eeh_sysfs_remove_device(dev); 1106 1107 /* 1108 * We're removing from the PCI subsystem, that means 1109 * the PCI device driver can't support EEH or not 1110 * well. So we rely on hotplug completely to do recovery 1111 * for the specific PCI device. 1112 */ 1113 edev->mode |= EEH_DEV_NO_HANDLER; 1114 1115 eeh_addr_cache_rmv_dev(dev); 1116 1117 /* 1118 * The flag "in_error" is used to trace EEH devices for VFs 1119 * in error state or not. It's set in eeh_report_error(). If 1120 * it's not set, eeh_report_{reset,resume}() won't be called 1121 * for the VF EEH device. 1122 */ 1123 edev->in_error = false; 1124 dev->dev.archdata.edev = NULL; 1125 if (!(edev->pe->state & EEH_PE_KEEP)) 1126 eeh_pe_tree_remove(edev); 1127 else 1128 edev->mode |= EEH_DEV_DISCONNECTED; 1129 } 1130 1131 int eeh_unfreeze_pe(struct eeh_pe *pe) 1132 { 1133 int ret; 1134 1135 ret = eeh_pci_enable(pe, EEH_OPT_THAW_MMIO); 1136 if (ret) { 1137 pr_warn("%s: Failure %d enabling IO on PHB#%x-PE#%x\n", 1138 __func__, ret, pe->phb->global_number, pe->addr); 1139 return ret; 1140 } 1141 1142 ret = eeh_pci_enable(pe, EEH_OPT_THAW_DMA); 1143 if (ret) { 1144 pr_warn("%s: Failure %d enabling DMA on PHB#%x-PE#%x\n", 1145 __func__, ret, pe->phb->global_number, pe->addr); 1146 return ret; 1147 } 1148 1149 return ret; 1150 } 1151 1152 1153 static struct pci_device_id eeh_reset_ids[] = { 1154 { PCI_DEVICE(0x19a2, 0x0710) }, /* Emulex, BE */ 1155 { PCI_DEVICE(0x10df, 0xe220) }, /* Emulex, Lancer */ 1156 { PCI_DEVICE(0x14e4, 0x1657) }, /* Broadcom BCM5719 */ 1157 { 0 } 1158 }; 1159 1160 static int eeh_pe_change_owner(struct eeh_pe *pe) 1161 { 1162 struct eeh_dev *edev, *tmp; 1163 struct pci_dev *pdev; 1164 struct pci_device_id *id; 1165 int ret; 1166 1167 /* Check PE state */ 1168 ret = eeh_ops->get_state(pe, NULL); 1169 if (ret < 0 || ret == EEH_STATE_NOT_SUPPORT) 1170 return 0; 1171 1172 /* Unfrozen PE, nothing to do */ 1173 if (eeh_state_active(ret)) 1174 return 0; 1175 1176 /* Frozen PE, check if it needs PE level reset */ 1177 eeh_pe_for_each_dev(pe, edev, tmp) { 1178 pdev = eeh_dev_to_pci_dev(edev); 1179 if (!pdev) 1180 continue; 1181 1182 for (id = &eeh_reset_ids[0]; id->vendor != 0; id++) { 1183 if (id->vendor != PCI_ANY_ID && 1184 id->vendor != pdev->vendor) 1185 continue; 1186 if (id->device != PCI_ANY_ID && 1187 id->device != pdev->device) 1188 continue; 1189 if (id->subvendor != PCI_ANY_ID && 1190 id->subvendor != pdev->subsystem_vendor) 1191 continue; 1192 if (id->subdevice != PCI_ANY_ID && 1193 id->subdevice != pdev->subsystem_device) 1194 continue; 1195 1196 return eeh_pe_reset_and_recover(pe); 1197 } 1198 } 1199 1200 ret = eeh_unfreeze_pe(pe); 1201 if (!ret) 1202 eeh_pe_state_clear(pe, EEH_PE_ISOLATED, true); 1203 return ret; 1204 } 1205 1206 /** 1207 * eeh_dev_open - Increase count of pass through devices for PE 1208 * @pdev: PCI device 1209 * 1210 * Increase count of passed through devices for the indicated 1211 * PE. In the result, the EEH errors detected on the PE won't be 1212 * reported. The PE owner will be responsible for detection 1213 * and recovery. 1214 */ 1215 int eeh_dev_open(struct pci_dev *pdev) 1216 { 1217 struct eeh_dev *edev; 1218 int ret = -ENODEV; 1219 1220 mutex_lock(&eeh_dev_mutex); 1221 1222 /* No PCI device ? */ 1223 if (!pdev) 1224 goto out; 1225 1226 /* No EEH device or PE ? */ 1227 edev = pci_dev_to_eeh_dev(pdev); 1228 if (!edev || !edev->pe) 1229 goto out; 1230 1231 /* 1232 * The PE might have been put into frozen state, but we 1233 * didn't detect that yet. The passed through PCI devices 1234 * in frozen PE won't work properly. Clear the frozen state 1235 * in advance. 1236 */ 1237 ret = eeh_pe_change_owner(edev->pe); 1238 if (ret) 1239 goto out; 1240 1241 /* Increase PE's pass through count */ 1242 atomic_inc(&edev->pe->pass_dev_cnt); 1243 mutex_unlock(&eeh_dev_mutex); 1244 1245 return 0; 1246 out: 1247 mutex_unlock(&eeh_dev_mutex); 1248 return ret; 1249 } 1250 EXPORT_SYMBOL_GPL(eeh_dev_open); 1251 1252 /** 1253 * eeh_dev_release - Decrease count of pass through devices for PE 1254 * @pdev: PCI device 1255 * 1256 * Decrease count of pass through devices for the indicated PE. If 1257 * there is no passed through device in PE, the EEH errors detected 1258 * on the PE will be reported and handled as usual. 1259 */ 1260 void eeh_dev_release(struct pci_dev *pdev) 1261 { 1262 struct eeh_dev *edev; 1263 1264 mutex_lock(&eeh_dev_mutex); 1265 1266 /* No PCI device ? */ 1267 if (!pdev) 1268 goto out; 1269 1270 /* No EEH device ? */ 1271 edev = pci_dev_to_eeh_dev(pdev); 1272 if (!edev || !edev->pe || !eeh_pe_passed(edev->pe)) 1273 goto out; 1274 1275 /* Decrease PE's pass through count */ 1276 WARN_ON(atomic_dec_if_positive(&edev->pe->pass_dev_cnt) < 0); 1277 eeh_pe_change_owner(edev->pe); 1278 out: 1279 mutex_unlock(&eeh_dev_mutex); 1280 } 1281 EXPORT_SYMBOL(eeh_dev_release); 1282 1283 #ifdef CONFIG_IOMMU_API 1284 1285 static int dev_has_iommu_table(struct device *dev, void *data) 1286 { 1287 struct pci_dev *pdev = to_pci_dev(dev); 1288 struct pci_dev **ppdev = data; 1289 1290 if (!dev) 1291 return 0; 1292 1293 if (device_iommu_mapped(dev)) { 1294 *ppdev = pdev; 1295 return 1; 1296 } 1297 1298 return 0; 1299 } 1300 1301 /** 1302 * eeh_iommu_group_to_pe - Convert IOMMU group to EEH PE 1303 * @group: IOMMU group 1304 * 1305 * The routine is called to convert IOMMU group to EEH PE. 1306 */ 1307 struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group) 1308 { 1309 struct pci_dev *pdev = NULL; 1310 struct eeh_dev *edev; 1311 int ret; 1312 1313 /* No IOMMU group ? */ 1314 if (!group) 1315 return NULL; 1316 1317 ret = iommu_group_for_each_dev(group, &pdev, dev_has_iommu_table); 1318 if (!ret || !pdev) 1319 return NULL; 1320 1321 /* No EEH device or PE ? */ 1322 edev = pci_dev_to_eeh_dev(pdev); 1323 if (!edev || !edev->pe) 1324 return NULL; 1325 1326 return edev->pe; 1327 } 1328 EXPORT_SYMBOL_GPL(eeh_iommu_group_to_pe); 1329 1330 #endif /* CONFIG_IOMMU_API */ 1331 1332 /** 1333 * eeh_pe_set_option - Set options for the indicated PE 1334 * @pe: EEH PE 1335 * @option: requested option 1336 * 1337 * The routine is called to enable or disable EEH functionality 1338 * on the indicated PE, to enable IO or DMA for the frozen PE. 1339 */ 1340 int eeh_pe_set_option(struct eeh_pe *pe, int option) 1341 { 1342 int ret = 0; 1343 1344 /* Invalid PE ? */ 1345 if (!pe) 1346 return -ENODEV; 1347 1348 /* 1349 * EEH functionality could possibly be disabled, just 1350 * return error for the case. And the EEH functinality 1351 * isn't expected to be disabled on one specific PE. 1352 */ 1353 switch (option) { 1354 case EEH_OPT_ENABLE: 1355 if (eeh_enabled()) { 1356 ret = eeh_pe_change_owner(pe); 1357 break; 1358 } 1359 ret = -EIO; 1360 break; 1361 case EEH_OPT_DISABLE: 1362 break; 1363 case EEH_OPT_THAW_MMIO: 1364 case EEH_OPT_THAW_DMA: 1365 case EEH_OPT_FREEZE_PE: 1366 if (!eeh_ops || !eeh_ops->set_option) { 1367 ret = -ENOENT; 1368 break; 1369 } 1370 1371 ret = eeh_pci_enable(pe, option); 1372 break; 1373 default: 1374 pr_debug("%s: Option %d out of range (%d, %d)\n", 1375 __func__, option, EEH_OPT_DISABLE, EEH_OPT_THAW_DMA); 1376 ret = -EINVAL; 1377 } 1378 1379 return ret; 1380 } 1381 EXPORT_SYMBOL_GPL(eeh_pe_set_option); 1382 1383 /** 1384 * eeh_pe_get_state - Retrieve PE's state 1385 * @pe: EEH PE 1386 * 1387 * Retrieve the PE's state, which includes 3 aspects: enabled 1388 * DMA, enabled IO and asserted reset. 1389 */ 1390 int eeh_pe_get_state(struct eeh_pe *pe) 1391 { 1392 int result, ret = 0; 1393 bool rst_active, dma_en, mmio_en; 1394 1395 /* Existing PE ? */ 1396 if (!pe) 1397 return -ENODEV; 1398 1399 if (!eeh_ops || !eeh_ops->get_state) 1400 return -ENOENT; 1401 1402 /* 1403 * If the parent PE is owned by the host kernel and is undergoing 1404 * error recovery, we should return the PE state as temporarily 1405 * unavailable so that the error recovery on the guest is suspended 1406 * until the recovery completes on the host. 1407 */ 1408 if (pe->parent && 1409 !(pe->state & EEH_PE_REMOVED) && 1410 (pe->parent->state & (EEH_PE_ISOLATED | EEH_PE_RECOVERING))) 1411 return EEH_PE_STATE_UNAVAIL; 1412 1413 result = eeh_ops->get_state(pe, NULL); 1414 rst_active = !!(result & EEH_STATE_RESET_ACTIVE); 1415 dma_en = !!(result & EEH_STATE_DMA_ENABLED); 1416 mmio_en = !!(result & EEH_STATE_MMIO_ENABLED); 1417 1418 if (rst_active) 1419 ret = EEH_PE_STATE_RESET; 1420 else if (dma_en && mmio_en) 1421 ret = EEH_PE_STATE_NORMAL; 1422 else if (!dma_en && !mmio_en) 1423 ret = EEH_PE_STATE_STOPPED_IO_DMA; 1424 else if (!dma_en && mmio_en) 1425 ret = EEH_PE_STATE_STOPPED_DMA; 1426 else 1427 ret = EEH_PE_STATE_UNAVAIL; 1428 1429 return ret; 1430 } 1431 EXPORT_SYMBOL_GPL(eeh_pe_get_state); 1432 1433 static int eeh_pe_reenable_devices(struct eeh_pe *pe, bool include_passed) 1434 { 1435 struct eeh_dev *edev, *tmp; 1436 struct pci_dev *pdev; 1437 int ret = 0; 1438 1439 eeh_pe_restore_bars(pe); 1440 1441 /* 1442 * Reenable PCI devices as the devices passed 1443 * through are always enabled before the reset. 1444 */ 1445 eeh_pe_for_each_dev(pe, edev, tmp) { 1446 pdev = eeh_dev_to_pci_dev(edev); 1447 if (!pdev) 1448 continue; 1449 1450 ret = pci_reenable_device(pdev); 1451 if (ret) { 1452 pr_warn("%s: Failure %d reenabling %s\n", 1453 __func__, ret, pci_name(pdev)); 1454 return ret; 1455 } 1456 } 1457 1458 /* The PE is still in frozen state */ 1459 if (include_passed || !eeh_pe_passed(pe)) { 1460 ret = eeh_unfreeze_pe(pe); 1461 } else 1462 pr_info("EEH: Note: Leaving passthrough PHB#%x-PE#%x frozen.\n", 1463 pe->phb->global_number, pe->addr); 1464 if (!ret) 1465 eeh_pe_state_clear(pe, EEH_PE_ISOLATED, include_passed); 1466 return ret; 1467 } 1468 1469 1470 /** 1471 * eeh_pe_reset - Issue PE reset according to specified type 1472 * @pe: EEH PE 1473 * @option: reset type 1474 * 1475 * The routine is called to reset the specified PE with the 1476 * indicated type, either fundamental reset or hot reset. 1477 * PE reset is the most important part for error recovery. 1478 */ 1479 int eeh_pe_reset(struct eeh_pe *pe, int option, bool include_passed) 1480 { 1481 int ret = 0; 1482 1483 /* Invalid PE ? */ 1484 if (!pe) 1485 return -ENODEV; 1486 1487 if (!eeh_ops || !eeh_ops->set_option || !eeh_ops->reset) 1488 return -ENOENT; 1489 1490 switch (option) { 1491 case EEH_RESET_DEACTIVATE: 1492 ret = eeh_ops->reset(pe, option); 1493 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, include_passed); 1494 if (ret) 1495 break; 1496 1497 ret = eeh_pe_reenable_devices(pe, include_passed); 1498 break; 1499 case EEH_RESET_HOT: 1500 case EEH_RESET_FUNDAMENTAL: 1501 /* 1502 * Proactively freeze the PE to drop all MMIO access 1503 * during reset, which should be banned as it's always 1504 * cause recursive EEH error. 1505 */ 1506 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE); 1507 1508 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED); 1509 ret = eeh_ops->reset(pe, option); 1510 break; 1511 default: 1512 pr_debug("%s: Unsupported option %d\n", 1513 __func__, option); 1514 ret = -EINVAL; 1515 } 1516 1517 return ret; 1518 } 1519 EXPORT_SYMBOL_GPL(eeh_pe_reset); 1520 1521 /** 1522 * eeh_pe_configure - Configure PCI bridges after PE reset 1523 * @pe: EEH PE 1524 * 1525 * The routine is called to restore the PCI config space for 1526 * those PCI devices, especially PCI bridges affected by PE 1527 * reset issued previously. 1528 */ 1529 int eeh_pe_configure(struct eeh_pe *pe) 1530 { 1531 int ret = 0; 1532 1533 /* Invalid PE ? */ 1534 if (!pe) 1535 return -ENODEV; 1536 1537 return ret; 1538 } 1539 EXPORT_SYMBOL_GPL(eeh_pe_configure); 1540 1541 /** 1542 * eeh_pe_inject_err - Injecting the specified PCI error to the indicated PE 1543 * @pe: the indicated PE 1544 * @type: error type 1545 * @function: error function 1546 * @addr: address 1547 * @mask: address mask 1548 * 1549 * The routine is called to inject the specified PCI error, which 1550 * is determined by @type and @function, to the indicated PE for 1551 * testing purpose. 1552 */ 1553 int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func, 1554 unsigned long addr, unsigned long mask) 1555 { 1556 /* Invalid PE ? */ 1557 if (!pe) 1558 return -ENODEV; 1559 1560 /* Unsupported operation ? */ 1561 if (!eeh_ops || !eeh_ops->err_inject) 1562 return -ENOENT; 1563 1564 /* Check on PCI error type */ 1565 if (type != EEH_ERR_TYPE_32 && type != EEH_ERR_TYPE_64) 1566 return -EINVAL; 1567 1568 /* Check on PCI error function */ 1569 if (func < EEH_ERR_FUNC_MIN || func > EEH_ERR_FUNC_MAX) 1570 return -EINVAL; 1571 1572 return eeh_ops->err_inject(pe, type, func, addr, mask); 1573 } 1574 EXPORT_SYMBOL_GPL(eeh_pe_inject_err); 1575 1576 static int proc_eeh_show(struct seq_file *m, void *v) 1577 { 1578 if (!eeh_enabled()) { 1579 seq_printf(m, "EEH Subsystem is globally disabled\n"); 1580 seq_printf(m, "eeh_total_mmio_ffs=%llu\n", eeh_stats.total_mmio_ffs); 1581 } else { 1582 seq_printf(m, "EEH Subsystem is enabled\n"); 1583 seq_printf(m, 1584 "no device=%llu\n" 1585 "no device node=%llu\n" 1586 "no config address=%llu\n" 1587 "check not wanted=%llu\n" 1588 "eeh_total_mmio_ffs=%llu\n" 1589 "eeh_false_positives=%llu\n" 1590 "eeh_slot_resets=%llu\n", 1591 eeh_stats.no_device, 1592 eeh_stats.no_dn, 1593 eeh_stats.no_cfg_addr, 1594 eeh_stats.ignored_check, 1595 eeh_stats.total_mmio_ffs, 1596 eeh_stats.false_positives, 1597 eeh_stats.slot_resets); 1598 } 1599 1600 return 0; 1601 } 1602 1603 #ifdef CONFIG_DEBUG_FS 1604 static int eeh_enable_dbgfs_set(void *data, u64 val) 1605 { 1606 if (val) 1607 eeh_clear_flag(EEH_FORCE_DISABLED); 1608 else 1609 eeh_add_flag(EEH_FORCE_DISABLED); 1610 1611 return 0; 1612 } 1613 1614 static int eeh_enable_dbgfs_get(void *data, u64 *val) 1615 { 1616 if (eeh_enabled()) 1617 *val = 0x1ul; 1618 else 1619 *val = 0x0ul; 1620 return 0; 1621 } 1622 1623 DEFINE_DEBUGFS_ATTRIBUTE(eeh_enable_dbgfs_ops, eeh_enable_dbgfs_get, 1624 eeh_enable_dbgfs_set, "0x%llx\n"); 1625 1626 static ssize_t eeh_force_recover_write(struct file *filp, 1627 const char __user *user_buf, 1628 size_t count, loff_t *ppos) 1629 { 1630 struct pci_controller *hose; 1631 uint32_t phbid, pe_no; 1632 struct eeh_pe *pe; 1633 char buf[20]; 1634 int ret; 1635 1636 ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count); 1637 if (!ret) 1638 return -EFAULT; 1639 1640 /* 1641 * When PE is NULL the event is a "special" event. Rather than 1642 * recovering a specific PE it forces the EEH core to scan for failed 1643 * PHBs and recovers each. This needs to be done before any device 1644 * recoveries can occur. 1645 */ 1646 if (!strncmp(buf, "hwcheck", 7)) { 1647 __eeh_send_failure_event(NULL); 1648 return count; 1649 } 1650 1651 ret = sscanf(buf, "%x:%x", &phbid, &pe_no); 1652 if (ret != 2) 1653 return -EINVAL; 1654 1655 hose = pci_find_controller_for_domain(phbid); 1656 if (!hose) 1657 return -ENODEV; 1658 1659 /* Retrieve PE */ 1660 pe = eeh_pe_get(hose, pe_no); 1661 if (!pe) 1662 return -ENODEV; 1663 1664 /* 1665 * We don't do any state checking here since the detection 1666 * process is async to the recovery process. The recovery 1667 * thread *should* not break even if we schedule a recovery 1668 * from an odd state (e.g. PE removed, or recovery of a 1669 * non-isolated PE) 1670 */ 1671 __eeh_send_failure_event(pe); 1672 1673 return ret < 0 ? ret : count; 1674 } 1675 1676 static const struct file_operations eeh_force_recover_fops = { 1677 .open = simple_open, 1678 .llseek = no_llseek, 1679 .write = eeh_force_recover_write, 1680 }; 1681 1682 static ssize_t eeh_debugfs_dev_usage(struct file *filp, 1683 char __user *user_buf, 1684 size_t count, loff_t *ppos) 1685 { 1686 static const char usage[] = "input format: <domain>:<bus>:<dev>.<fn>\n"; 1687 1688 return simple_read_from_buffer(user_buf, count, ppos, 1689 usage, sizeof(usage) - 1); 1690 } 1691 1692 static ssize_t eeh_dev_check_write(struct file *filp, 1693 const char __user *user_buf, 1694 size_t count, loff_t *ppos) 1695 { 1696 uint32_t domain, bus, dev, fn; 1697 struct pci_dev *pdev; 1698 struct eeh_dev *edev; 1699 char buf[20]; 1700 int ret; 1701 1702 memset(buf, 0, sizeof(buf)); 1703 ret = simple_write_to_buffer(buf, sizeof(buf)-1, ppos, user_buf, count); 1704 if (!ret) 1705 return -EFAULT; 1706 1707 ret = sscanf(buf, "%x:%x:%x.%x", &domain, &bus, &dev, &fn); 1708 if (ret != 4) { 1709 pr_err("%s: expected 4 args, got %d\n", __func__, ret); 1710 return -EINVAL; 1711 } 1712 1713 pdev = pci_get_domain_bus_and_slot(domain, bus, (dev << 3) | fn); 1714 if (!pdev) 1715 return -ENODEV; 1716 1717 edev = pci_dev_to_eeh_dev(pdev); 1718 if (!edev) { 1719 pci_err(pdev, "No eeh_dev for this device!\n"); 1720 pci_dev_put(pdev); 1721 return -ENODEV; 1722 } 1723 1724 ret = eeh_dev_check_failure(edev); 1725 pci_info(pdev, "eeh_dev_check_failure(%04x:%02x:%02x.%01x) = %d\n", 1726 domain, bus, dev, fn, ret); 1727 1728 pci_dev_put(pdev); 1729 1730 return count; 1731 } 1732 1733 static const struct file_operations eeh_dev_check_fops = { 1734 .open = simple_open, 1735 .llseek = no_llseek, 1736 .write = eeh_dev_check_write, 1737 .read = eeh_debugfs_dev_usage, 1738 }; 1739 1740 static int eeh_debugfs_break_device(struct pci_dev *pdev) 1741 { 1742 struct resource *bar = NULL; 1743 void __iomem *mapped; 1744 u16 old, bit; 1745 int i, pos; 1746 1747 /* Do we have an MMIO BAR to disable? */ 1748 for (i = 0; i <= PCI_STD_RESOURCE_END; i++) { 1749 struct resource *r = &pdev->resource[i]; 1750 1751 if (!r->flags || !r->start) 1752 continue; 1753 if (r->flags & IORESOURCE_IO) 1754 continue; 1755 if (r->flags & IORESOURCE_UNSET) 1756 continue; 1757 1758 bar = r; 1759 break; 1760 } 1761 1762 if (!bar) { 1763 pci_err(pdev, "Unable to find Memory BAR to cause EEH with\n"); 1764 return -ENXIO; 1765 } 1766 1767 pci_err(pdev, "Going to break: %pR\n", bar); 1768 1769 if (pdev->is_virtfn) { 1770 #ifndef CONFIG_PCI_IOV 1771 return -ENXIO; 1772 #else 1773 /* 1774 * VFs don't have a per-function COMMAND register, so the best 1775 * we can do is clear the Memory Space Enable bit in the PF's 1776 * SRIOV control reg. 1777 * 1778 * Unfortunately, this requires that we have a PF (i.e doesn't 1779 * work for a passed-through VF) and it has the potential side 1780 * effect of also causing an EEH on every other VF under the 1781 * PF. Oh well. 1782 */ 1783 pdev = pdev->physfn; 1784 if (!pdev) 1785 return -ENXIO; /* passed through VFs have no PF */ 1786 1787 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); 1788 pos += PCI_SRIOV_CTRL; 1789 bit = PCI_SRIOV_CTRL_MSE; 1790 #endif /* !CONFIG_PCI_IOV */ 1791 } else { 1792 bit = PCI_COMMAND_MEMORY; 1793 pos = PCI_COMMAND; 1794 } 1795 1796 /* 1797 * Process here is: 1798 * 1799 * 1. Disable Memory space. 1800 * 1801 * 2. Perform an MMIO to the device. This should result in an error 1802 * (CA / UR) being raised by the device which results in an EEH 1803 * PE freeze. Using the in_8() accessor skips the eeh detection hook 1804 * so the freeze hook so the EEH Detection machinery won't be 1805 * triggered here. This is to match the usual behaviour of EEH 1806 * where the HW will asyncronously freeze a PE and it's up to 1807 * the kernel to notice and deal with it. 1808 * 1809 * 3. Turn Memory space back on. This is more important for VFs 1810 * since recovery will probably fail if we don't. For normal 1811 * the COMMAND register is reset as a part of re-initialising 1812 * the device. 1813 * 1814 * Breaking stuff is the point so who cares if it's racy ;) 1815 */ 1816 pci_read_config_word(pdev, pos, &old); 1817 1818 mapped = ioremap(bar->start, PAGE_SIZE); 1819 if (!mapped) { 1820 pci_err(pdev, "Unable to map MMIO BAR %pR\n", bar); 1821 return -ENXIO; 1822 } 1823 1824 pci_write_config_word(pdev, pos, old & ~bit); 1825 in_8(mapped); 1826 pci_write_config_word(pdev, pos, old); 1827 1828 iounmap(mapped); 1829 1830 return 0; 1831 } 1832 1833 static ssize_t eeh_dev_break_write(struct file *filp, 1834 const char __user *user_buf, 1835 size_t count, loff_t *ppos) 1836 { 1837 uint32_t domain, bus, dev, fn; 1838 struct pci_dev *pdev; 1839 char buf[20]; 1840 int ret; 1841 1842 memset(buf, 0, sizeof(buf)); 1843 ret = simple_write_to_buffer(buf, sizeof(buf)-1, ppos, user_buf, count); 1844 if (!ret) 1845 return -EFAULT; 1846 1847 ret = sscanf(buf, "%x:%x:%x.%x", &domain, &bus, &dev, &fn); 1848 if (ret != 4) { 1849 pr_err("%s: expected 4 args, got %d\n", __func__, ret); 1850 return -EINVAL; 1851 } 1852 1853 pdev = pci_get_domain_bus_and_slot(domain, bus, (dev << 3) | fn); 1854 if (!pdev) 1855 return -ENODEV; 1856 1857 ret = eeh_debugfs_break_device(pdev); 1858 pci_dev_put(pdev); 1859 1860 if (ret < 0) 1861 return ret; 1862 1863 return count; 1864 } 1865 1866 static const struct file_operations eeh_dev_break_fops = { 1867 .open = simple_open, 1868 .llseek = no_llseek, 1869 .write = eeh_dev_break_write, 1870 .read = eeh_debugfs_dev_usage, 1871 }; 1872 1873 #endif 1874 1875 static int __init eeh_init_proc(void) 1876 { 1877 if (machine_is(pseries) || machine_is(powernv)) { 1878 proc_create_single("powerpc/eeh", 0, NULL, proc_eeh_show); 1879 #ifdef CONFIG_DEBUG_FS 1880 debugfs_create_file_unsafe("eeh_enable", 0600, 1881 powerpc_debugfs_root, NULL, 1882 &eeh_enable_dbgfs_ops); 1883 debugfs_create_u32("eeh_max_freezes", 0600, 1884 powerpc_debugfs_root, &eeh_max_freezes); 1885 debugfs_create_bool("eeh_disable_recovery", 0600, 1886 powerpc_debugfs_root, 1887 &eeh_debugfs_no_recover); 1888 debugfs_create_file_unsafe("eeh_dev_check", 0600, 1889 powerpc_debugfs_root, NULL, 1890 &eeh_dev_check_fops); 1891 debugfs_create_file_unsafe("eeh_dev_break", 0600, 1892 powerpc_debugfs_root, NULL, 1893 &eeh_dev_break_fops); 1894 debugfs_create_file_unsafe("eeh_force_recover", 0600, 1895 powerpc_debugfs_root, NULL, 1896 &eeh_force_recover_fops); 1897 eeh_cache_debugfs_init(); 1898 #endif 1899 } 1900 1901 return 0; 1902 } 1903 __initcall(eeh_init_proc); 1904