1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright 2017, Nicholas Piggin, IBM Corporation 4 */ 5 6 #define pr_fmt(fmt) "dt-cpu-ftrs: " fmt 7 8 #include <linux/export.h> 9 #include <linux/init.h> 10 #include <linux/jump_label.h> 11 #include <linux/libfdt.h> 12 #include <linux/memblock.h> 13 #include <linux/printk.h> 14 #include <linux/sched.h> 15 #include <linux/string.h> 16 #include <linux/threads.h> 17 18 #include <asm/cputable.h> 19 #include <asm/dt_cpu_ftrs.h> 20 #include <asm/mmu.h> 21 #include <asm/oprofile_impl.h> 22 #include <asm/prom.h> 23 #include <asm/setup.h> 24 25 26 /* Device-tree visible constants follow */ 27 #define ISA_V2_07B 2070 28 #define ISA_V3_0B 3000 29 #define ISA_V3_1 3100 30 31 #define USABLE_PR (1U << 0) 32 #define USABLE_OS (1U << 1) 33 #define USABLE_HV (1U << 2) 34 35 #define HV_SUPPORT_HFSCR (1U << 0) 36 #define OS_SUPPORT_FSCR (1U << 0) 37 38 /* For parsing, we define all bits set as "NONE" case */ 39 #define HV_SUPPORT_NONE 0xffffffffU 40 #define OS_SUPPORT_NONE 0xffffffffU 41 42 struct dt_cpu_feature { 43 const char *name; 44 uint32_t isa; 45 uint32_t usable_privilege; 46 uint32_t hv_support; 47 uint32_t os_support; 48 uint32_t hfscr_bit_nr; 49 uint32_t fscr_bit_nr; 50 uint32_t hwcap_bit_nr; 51 /* fdt parsing */ 52 unsigned long node; 53 int enabled; 54 int disabled; 55 }; 56 57 #define MMU_FTRS_HASH_BASE (MMU_FTRS_POWER8) 58 59 #define COMMON_USER_BASE (PPC_FEATURE_32 | PPC_FEATURE_64 | \ 60 PPC_FEATURE_ARCH_2_06 |\ 61 PPC_FEATURE_ICACHE_SNOOP) 62 #define COMMON_USER2_BASE (PPC_FEATURE2_ARCH_2_07 | \ 63 PPC_FEATURE2_ISEL) 64 /* 65 * Set up the base CPU 66 */ 67 68 extern long __machine_check_early_realmode_p8(struct pt_regs *regs); 69 extern long __machine_check_early_realmode_p9(struct pt_regs *regs); 70 71 static int hv_mode; 72 73 static struct { 74 u64 lpcr; 75 u64 lpcr_clear; 76 u64 hfscr; 77 u64 fscr; 78 u64 pcr; 79 } system_registers; 80 81 static void (*init_pmu_registers)(void); 82 83 static void __restore_cpu_cpufeatures(void) 84 { 85 u64 lpcr; 86 87 /* 88 * LPCR is restored by the power on engine already. It can be changed 89 * after early init e.g., by radix enable, and we have no unified API 90 * for saving and restoring such SPRs. 91 * 92 * This ->restore hook should really be removed from idle and register 93 * restore moved directly into the idle restore code, because this code 94 * doesn't know how idle is implemented or what it needs restored here. 95 * 96 * The best we can do to accommodate secondary boot and idle restore 97 * for now is "or" LPCR with existing. 98 */ 99 lpcr = mfspr(SPRN_LPCR); 100 lpcr |= system_registers.lpcr; 101 lpcr &= ~system_registers.lpcr_clear; 102 mtspr(SPRN_LPCR, lpcr); 103 if (hv_mode) { 104 mtspr(SPRN_LPID, 0); 105 mtspr(SPRN_HFSCR, system_registers.hfscr); 106 mtspr(SPRN_PCR, system_registers.pcr); 107 } 108 mtspr(SPRN_FSCR, system_registers.fscr); 109 110 if (init_pmu_registers) 111 init_pmu_registers(); 112 } 113 114 static char dt_cpu_name[64]; 115 116 static struct cpu_spec __initdata base_cpu_spec = { 117 .cpu_name = NULL, 118 .cpu_features = CPU_FTRS_DT_CPU_BASE, 119 .cpu_user_features = COMMON_USER_BASE, 120 .cpu_user_features2 = COMMON_USER2_BASE, 121 .mmu_features = 0, 122 .icache_bsize = 32, /* minimum block size, fixed by */ 123 .dcache_bsize = 32, /* cache info init. */ 124 .num_pmcs = 0, 125 .pmc_type = PPC_PMC_DEFAULT, 126 .oprofile_cpu_type = NULL, 127 .oprofile_type = PPC_OPROFILE_INVALID, 128 .cpu_setup = NULL, 129 .cpu_restore = __restore_cpu_cpufeatures, 130 .machine_check_early = NULL, 131 .platform = NULL, 132 }; 133 134 static void __init cpufeatures_setup_cpu(void) 135 { 136 set_cur_cpu_spec(&base_cpu_spec); 137 138 cur_cpu_spec->pvr_mask = -1; 139 cur_cpu_spec->pvr_value = mfspr(SPRN_PVR); 140 141 /* Initialize the base environment -- clear FSCR/HFSCR. */ 142 hv_mode = !!(mfmsr() & MSR_HV); 143 if (hv_mode) { 144 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE; 145 mtspr(SPRN_HFSCR, 0); 146 } 147 mtspr(SPRN_FSCR, 0); 148 mtspr(SPRN_PCR, PCR_MASK); 149 150 /* 151 * LPCR does not get cleared, to match behaviour with secondaries 152 * in __restore_cpu_cpufeatures. Once the idle code is fixed, this 153 * could clear LPCR too. 154 */ 155 } 156 157 static int __init feat_try_enable_unknown(struct dt_cpu_feature *f) 158 { 159 if (f->hv_support == HV_SUPPORT_NONE) { 160 } else if (f->hv_support & HV_SUPPORT_HFSCR) { 161 u64 hfscr = mfspr(SPRN_HFSCR); 162 hfscr |= 1UL << f->hfscr_bit_nr; 163 mtspr(SPRN_HFSCR, hfscr); 164 } else { 165 /* Does not have a known recipe */ 166 return 0; 167 } 168 169 if (f->os_support == OS_SUPPORT_NONE) { 170 } else if (f->os_support & OS_SUPPORT_FSCR) { 171 u64 fscr = mfspr(SPRN_FSCR); 172 fscr |= 1UL << f->fscr_bit_nr; 173 mtspr(SPRN_FSCR, fscr); 174 } else { 175 /* Does not have a known recipe */ 176 return 0; 177 } 178 179 if ((f->usable_privilege & USABLE_PR) && (f->hwcap_bit_nr != -1)) { 180 uint32_t word = f->hwcap_bit_nr / 32; 181 uint32_t bit = f->hwcap_bit_nr % 32; 182 183 if (word == 0) 184 cur_cpu_spec->cpu_user_features |= 1U << bit; 185 else if (word == 1) 186 cur_cpu_spec->cpu_user_features2 |= 1U << bit; 187 else 188 pr_err("%s could not advertise to user (no hwcap bits)\n", f->name); 189 } 190 191 return 1; 192 } 193 194 static int __init feat_enable(struct dt_cpu_feature *f) 195 { 196 if (f->hv_support != HV_SUPPORT_NONE) { 197 if (f->hfscr_bit_nr != -1) { 198 u64 hfscr = mfspr(SPRN_HFSCR); 199 hfscr |= 1UL << f->hfscr_bit_nr; 200 mtspr(SPRN_HFSCR, hfscr); 201 } 202 } 203 204 if (f->os_support != OS_SUPPORT_NONE) { 205 if (f->fscr_bit_nr != -1) { 206 u64 fscr = mfspr(SPRN_FSCR); 207 fscr |= 1UL << f->fscr_bit_nr; 208 mtspr(SPRN_FSCR, fscr); 209 } 210 } 211 212 if ((f->usable_privilege & USABLE_PR) && (f->hwcap_bit_nr != -1)) { 213 uint32_t word = f->hwcap_bit_nr / 32; 214 uint32_t bit = f->hwcap_bit_nr % 32; 215 216 if (word == 0) 217 cur_cpu_spec->cpu_user_features |= 1U << bit; 218 else if (word == 1) 219 cur_cpu_spec->cpu_user_features2 |= 1U << bit; 220 else 221 pr_err("CPU feature: %s could not advertise to user (no hwcap bits)\n", f->name); 222 } 223 224 return 1; 225 } 226 227 static int __init feat_disable(struct dt_cpu_feature *f) 228 { 229 return 0; 230 } 231 232 static int __init feat_enable_hv(struct dt_cpu_feature *f) 233 { 234 u64 lpcr; 235 236 if (!hv_mode) { 237 pr_err("CPU feature hypervisor present in device tree but HV mode not enabled in the CPU. Ignoring.\n"); 238 return 0; 239 } 240 241 mtspr(SPRN_LPID, 0); 242 243 lpcr = mfspr(SPRN_LPCR); 244 lpcr &= ~LPCR_LPES0; /* HV external interrupts */ 245 mtspr(SPRN_LPCR, lpcr); 246 247 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE; 248 249 return 1; 250 } 251 252 static int __init feat_enable_le(struct dt_cpu_feature *f) 253 { 254 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_TRUE_LE; 255 return 1; 256 } 257 258 static int __init feat_enable_smt(struct dt_cpu_feature *f) 259 { 260 cur_cpu_spec->cpu_features |= CPU_FTR_SMT; 261 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_SMT; 262 return 1; 263 } 264 265 static int __init feat_enable_idle_nap(struct dt_cpu_feature *f) 266 { 267 u64 lpcr; 268 269 /* Set PECE wakeup modes for ISA 207 */ 270 lpcr = mfspr(SPRN_LPCR); 271 lpcr |= LPCR_PECE0; 272 lpcr |= LPCR_PECE1; 273 lpcr |= LPCR_PECE2; 274 mtspr(SPRN_LPCR, lpcr); 275 276 return 1; 277 } 278 279 static int __init feat_enable_align_dsisr(struct dt_cpu_feature *f) 280 { 281 cur_cpu_spec->cpu_features &= ~CPU_FTR_NODSISRALIGN; 282 283 return 1; 284 } 285 286 static int __init feat_enable_idle_stop(struct dt_cpu_feature *f) 287 { 288 u64 lpcr; 289 290 /* Set PECE wakeup modes for ISAv3.0B */ 291 lpcr = mfspr(SPRN_LPCR); 292 lpcr |= LPCR_PECE0; 293 lpcr |= LPCR_PECE1; 294 lpcr |= LPCR_PECE2; 295 mtspr(SPRN_LPCR, lpcr); 296 297 return 1; 298 } 299 300 static int __init feat_enable_mmu_hash(struct dt_cpu_feature *f) 301 { 302 u64 lpcr; 303 304 lpcr = mfspr(SPRN_LPCR); 305 lpcr &= ~LPCR_ISL; 306 307 /* VRMASD */ 308 lpcr |= LPCR_VPM0; 309 lpcr &= ~LPCR_VPM1; 310 lpcr |= 0x10UL << LPCR_VRMASD_SH; /* L=1 LP=00 */ 311 mtspr(SPRN_LPCR, lpcr); 312 313 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE; 314 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU; 315 316 return 1; 317 } 318 319 static int __init feat_enable_mmu_hash_v3(struct dt_cpu_feature *f) 320 { 321 u64 lpcr; 322 323 system_registers.lpcr_clear |= (LPCR_ISL | LPCR_UPRT | LPCR_HR); 324 lpcr = mfspr(SPRN_LPCR); 325 lpcr &= ~(LPCR_ISL | LPCR_UPRT | LPCR_HR); 326 mtspr(SPRN_LPCR, lpcr); 327 328 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE; 329 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU; 330 331 return 1; 332 } 333 334 335 static int __init feat_enable_mmu_radix(struct dt_cpu_feature *f) 336 { 337 #ifdef CONFIG_PPC_RADIX_MMU 338 cur_cpu_spec->mmu_features |= MMU_FTR_TYPE_RADIX; 339 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE; 340 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU; 341 342 return 1; 343 #endif 344 return 0; 345 } 346 347 static int __init feat_enable_dscr(struct dt_cpu_feature *f) 348 { 349 u64 lpcr; 350 351 /* 352 * Linux relies on FSCR[DSCR] being clear, so that we can take the 353 * facility unavailable interrupt and track the task's usage of DSCR. 354 * See facility_unavailable_exception(). 355 * Clear the bit here so that feat_enable() doesn't set it. 356 */ 357 f->fscr_bit_nr = -1; 358 359 feat_enable(f); 360 361 lpcr = mfspr(SPRN_LPCR); 362 lpcr &= ~LPCR_DPFD; 363 lpcr |= (4UL << LPCR_DPFD_SH); 364 mtspr(SPRN_LPCR, lpcr); 365 366 return 1; 367 } 368 369 static void hfscr_pmu_enable(void) 370 { 371 u64 hfscr = mfspr(SPRN_HFSCR); 372 hfscr |= PPC_BIT(60); 373 mtspr(SPRN_HFSCR, hfscr); 374 } 375 376 static void init_pmu_power8(void) 377 { 378 if (hv_mode) { 379 mtspr(SPRN_MMCRC, 0); 380 mtspr(SPRN_MMCRH, 0); 381 } 382 383 mtspr(SPRN_MMCRA, 0); 384 mtspr(SPRN_MMCR0, 0); 385 mtspr(SPRN_MMCR1, 0); 386 mtspr(SPRN_MMCR2, 0); 387 mtspr(SPRN_MMCRS, 0); 388 } 389 390 static int __init feat_enable_mce_power8(struct dt_cpu_feature *f) 391 { 392 cur_cpu_spec->platform = "power8"; 393 cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p8; 394 395 return 1; 396 } 397 398 static int __init feat_enable_pmu_power8(struct dt_cpu_feature *f) 399 { 400 hfscr_pmu_enable(); 401 402 init_pmu_power8(); 403 init_pmu_registers = init_pmu_power8; 404 405 cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA; 406 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT; 407 if (pvr_version_is(PVR_POWER8E)) 408 cur_cpu_spec->cpu_features |= CPU_FTR_PMAO_BUG; 409 410 cur_cpu_spec->num_pmcs = 6; 411 cur_cpu_spec->pmc_type = PPC_PMC_IBM; 412 cur_cpu_spec->oprofile_cpu_type = "ppc64/power8"; 413 414 return 1; 415 } 416 417 static void init_pmu_power9(void) 418 { 419 if (hv_mode) 420 mtspr(SPRN_MMCRC, 0); 421 422 mtspr(SPRN_MMCRA, 0); 423 mtspr(SPRN_MMCR0, 0); 424 mtspr(SPRN_MMCR1, 0); 425 mtspr(SPRN_MMCR2, 0); 426 } 427 428 static int __init feat_enable_mce_power9(struct dt_cpu_feature *f) 429 { 430 cur_cpu_spec->platform = "power9"; 431 cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p9; 432 433 return 1; 434 } 435 436 static int __init feat_enable_pmu_power9(struct dt_cpu_feature *f) 437 { 438 hfscr_pmu_enable(); 439 440 init_pmu_power9(); 441 init_pmu_registers = init_pmu_power9; 442 443 cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA; 444 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT; 445 446 cur_cpu_spec->num_pmcs = 6; 447 cur_cpu_spec->pmc_type = PPC_PMC_IBM; 448 cur_cpu_spec->oprofile_cpu_type = "ppc64/power9"; 449 450 return 1; 451 } 452 453 static int __init feat_enable_tm(struct dt_cpu_feature *f) 454 { 455 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 456 feat_enable(f); 457 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NOSC; 458 return 1; 459 #endif 460 return 0; 461 } 462 463 static int __init feat_enable_fp(struct dt_cpu_feature *f) 464 { 465 feat_enable(f); 466 cur_cpu_spec->cpu_features &= ~CPU_FTR_FPU_UNAVAILABLE; 467 468 return 1; 469 } 470 471 static int __init feat_enable_vector(struct dt_cpu_feature *f) 472 { 473 #ifdef CONFIG_ALTIVEC 474 feat_enable(f); 475 cur_cpu_spec->cpu_features |= CPU_FTR_ALTIVEC; 476 cur_cpu_spec->cpu_features |= CPU_FTR_VMX_COPY; 477 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_ALTIVEC; 478 479 return 1; 480 #endif 481 return 0; 482 } 483 484 static int __init feat_enable_vsx(struct dt_cpu_feature *f) 485 { 486 #ifdef CONFIG_VSX 487 feat_enable(f); 488 cur_cpu_spec->cpu_features |= CPU_FTR_VSX; 489 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_VSX; 490 491 return 1; 492 #endif 493 return 0; 494 } 495 496 static int __init feat_enable_purr(struct dt_cpu_feature *f) 497 { 498 cur_cpu_spec->cpu_features |= CPU_FTR_PURR | CPU_FTR_SPURR; 499 500 return 1; 501 } 502 503 static int __init feat_enable_ebb(struct dt_cpu_feature *f) 504 { 505 /* 506 * PPC_FEATURE2_EBB is enabled in PMU init code because it has 507 * historically been related to the PMU facility. This may have 508 * to be decoupled if EBB becomes more generic. For now, follow 509 * existing convention. 510 */ 511 f->hwcap_bit_nr = -1; 512 feat_enable(f); 513 514 return 1; 515 } 516 517 static int __init feat_enable_dbell(struct dt_cpu_feature *f) 518 { 519 u64 lpcr; 520 521 /* P9 has an HFSCR for privileged state */ 522 feat_enable(f); 523 524 cur_cpu_spec->cpu_features |= CPU_FTR_DBELL; 525 526 lpcr = mfspr(SPRN_LPCR); 527 lpcr |= LPCR_PECEDH; /* hyp doorbell wakeup */ 528 mtspr(SPRN_LPCR, lpcr); 529 530 return 1; 531 } 532 533 static int __init feat_enable_hvi(struct dt_cpu_feature *f) 534 { 535 u64 lpcr; 536 537 /* 538 * POWER9 XIVE interrupts including in OPAL XICS compatibility 539 * are always delivered as hypervisor virtualization interrupts (HVI) 540 * rather than EE. 541 * 542 * However LPES0 is not set here, in the chance that an EE does get 543 * delivered to the host somehow, the EE handler would not expect it 544 * to be delivered in LPES0 mode (e.g., using SRR[01]). This could 545 * happen if there is a bug in interrupt controller code, or IC is 546 * misconfigured in systemsim. 547 */ 548 549 lpcr = mfspr(SPRN_LPCR); 550 lpcr |= LPCR_HVICE; /* enable hvi interrupts */ 551 lpcr |= LPCR_HEIC; /* disable ee interrupts when MSR_HV */ 552 lpcr |= LPCR_PECE_HVEE; /* hvi can wake from stop */ 553 mtspr(SPRN_LPCR, lpcr); 554 555 return 1; 556 } 557 558 static int __init feat_enable_large_ci(struct dt_cpu_feature *f) 559 { 560 cur_cpu_spec->mmu_features |= MMU_FTR_CI_LARGE_PAGE; 561 562 return 1; 563 } 564 565 static int __init feat_enable_mma(struct dt_cpu_feature *f) 566 { 567 u64 pcr; 568 569 feat_enable(f); 570 pcr = mfspr(SPRN_PCR); 571 pcr &= ~PCR_MMA_DIS; 572 mtspr(SPRN_PCR, pcr); 573 574 return 1; 575 } 576 577 struct dt_cpu_feature_match { 578 const char *name; 579 int (*enable)(struct dt_cpu_feature *f); 580 u64 cpu_ftr_bit_mask; 581 }; 582 583 static struct dt_cpu_feature_match __initdata 584 dt_cpu_feature_match_table[] = { 585 {"hypervisor", feat_enable_hv, 0}, 586 {"big-endian", feat_enable, 0}, 587 {"little-endian", feat_enable_le, CPU_FTR_REAL_LE}, 588 {"smt", feat_enable_smt, 0}, 589 {"interrupt-facilities", feat_enable, 0}, 590 {"timer-facilities", feat_enable, 0}, 591 {"timer-facilities-v3", feat_enable, 0}, 592 {"debug-facilities", feat_enable, 0}, 593 {"come-from-address-register", feat_enable, CPU_FTR_CFAR}, 594 {"branch-tracing", feat_enable, 0}, 595 {"floating-point", feat_enable_fp, 0}, 596 {"vector", feat_enable_vector, 0}, 597 {"vector-scalar", feat_enable_vsx, 0}, 598 {"vector-scalar-v3", feat_enable, 0}, 599 {"decimal-floating-point", feat_enable, 0}, 600 {"decimal-integer", feat_enable, 0}, 601 {"quadword-load-store", feat_enable, 0}, 602 {"vector-crypto", feat_enable, 0}, 603 {"mmu-hash", feat_enable_mmu_hash, 0}, 604 {"mmu-radix", feat_enable_mmu_radix, 0}, 605 {"mmu-hash-v3", feat_enable_mmu_hash_v3, 0}, 606 {"virtual-page-class-key-protection", feat_enable, 0}, 607 {"transactional-memory", feat_enable_tm, CPU_FTR_TM}, 608 {"transactional-memory-v3", feat_enable_tm, 0}, 609 {"tm-suspend-hypervisor-assist", feat_enable, CPU_FTR_P9_TM_HV_ASSIST}, 610 {"tm-suspend-xer-so-bug", feat_enable, CPU_FTR_P9_TM_XER_SO_BUG}, 611 {"idle-nap", feat_enable_idle_nap, 0}, 612 {"alignment-interrupt-dsisr", feat_enable_align_dsisr, 0}, 613 {"idle-stop", feat_enable_idle_stop, 0}, 614 {"machine-check-power8", feat_enable_mce_power8, 0}, 615 {"performance-monitor-power8", feat_enable_pmu_power8, 0}, 616 {"data-stream-control-register", feat_enable_dscr, CPU_FTR_DSCR}, 617 {"event-based-branch", feat_enable_ebb, 0}, 618 {"target-address-register", feat_enable, 0}, 619 {"branch-history-rolling-buffer", feat_enable, 0}, 620 {"control-register", feat_enable, CPU_FTR_CTRL}, 621 {"processor-control-facility", feat_enable_dbell, CPU_FTR_DBELL}, 622 {"processor-control-facility-v3", feat_enable_dbell, CPU_FTR_DBELL}, 623 {"processor-utilization-of-resources-register", feat_enable_purr, 0}, 624 {"no-execute", feat_enable, 0}, 625 {"strong-access-ordering", feat_enable, CPU_FTR_SAO}, 626 {"cache-inhibited-large-page", feat_enable_large_ci, 0}, 627 {"coprocessor-icswx", feat_enable, 0}, 628 {"hypervisor-virtualization-interrupt", feat_enable_hvi, 0}, 629 {"program-priority-register", feat_enable, CPU_FTR_HAS_PPR}, 630 {"wait", feat_enable, 0}, 631 {"atomic-memory-operations", feat_enable, 0}, 632 {"branch-v3", feat_enable, 0}, 633 {"copy-paste", feat_enable, 0}, 634 {"decimal-floating-point-v3", feat_enable, 0}, 635 {"decimal-integer-v3", feat_enable, 0}, 636 {"fixed-point-v3", feat_enable, 0}, 637 {"floating-point-v3", feat_enable, 0}, 638 {"group-start-register", feat_enable, 0}, 639 {"pc-relative-addressing", feat_enable, 0}, 640 {"machine-check-power9", feat_enable_mce_power9, 0}, 641 {"performance-monitor-power9", feat_enable_pmu_power9, 0}, 642 {"event-based-branch-v3", feat_enable, 0}, 643 {"random-number-generator", feat_enable, 0}, 644 {"system-call-vectored", feat_disable, 0}, 645 {"trace-interrupt-v3", feat_enable, 0}, 646 {"vector-v3", feat_enable, 0}, 647 {"vector-binary128", feat_enable, 0}, 648 {"vector-binary16", feat_enable, 0}, 649 {"wait-v3", feat_enable, 0}, 650 {"prefix-instructions", feat_enable, 0}, 651 {"matrix-multiply-assist", feat_enable_mma, 0}, 652 }; 653 654 static bool __initdata using_dt_cpu_ftrs; 655 static bool __initdata enable_unknown = true; 656 657 static int __init dt_cpu_ftrs_parse(char *str) 658 { 659 if (!str) 660 return 0; 661 662 if (!strcmp(str, "off")) 663 using_dt_cpu_ftrs = false; 664 else if (!strcmp(str, "known")) 665 enable_unknown = false; 666 else 667 return 1; 668 669 return 0; 670 } 671 early_param("dt_cpu_ftrs", dt_cpu_ftrs_parse); 672 673 static void __init cpufeatures_setup_start(u32 isa) 674 { 675 pr_info("setup for ISA %d\n", isa); 676 677 if (isa >= 3000) { 678 cur_cpu_spec->cpu_features |= CPU_FTR_ARCH_300; 679 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_ARCH_3_00; 680 } 681 682 if (isa >= 3100) { 683 cur_cpu_spec->cpu_features |= CPU_FTR_ARCH_31; 684 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_ARCH_3_1; 685 } 686 } 687 688 static bool __init cpufeatures_process_feature(struct dt_cpu_feature *f) 689 { 690 const struct dt_cpu_feature_match *m; 691 bool known = false; 692 int i; 693 694 for (i = 0; i < ARRAY_SIZE(dt_cpu_feature_match_table); i++) { 695 m = &dt_cpu_feature_match_table[i]; 696 if (!strcmp(f->name, m->name)) { 697 known = true; 698 if (m->enable(f)) { 699 cur_cpu_spec->cpu_features |= m->cpu_ftr_bit_mask; 700 break; 701 } 702 703 pr_info("not enabling: %s (disabled or unsupported by kernel)\n", 704 f->name); 705 return false; 706 } 707 } 708 709 if (!known && (!enable_unknown || !feat_try_enable_unknown(f))) { 710 pr_info("not enabling: %s (unknown and unsupported by kernel)\n", 711 f->name); 712 return false; 713 } 714 715 if (known) 716 pr_debug("enabling: %s\n", f->name); 717 else 718 pr_debug("enabling: %s (unknown)\n", f->name); 719 720 return true; 721 } 722 723 /* 724 * Handle POWER9 broadcast tlbie invalidation issue using 725 * cpu feature flag. 726 */ 727 static __init void update_tlbie_feature_flag(unsigned long pvr) 728 { 729 if (PVR_VER(pvr) == PVR_POWER9) { 730 /* 731 * Set the tlbie feature flag for anything below 732 * Nimbus DD 2.3 and Cumulus DD 1.3 733 */ 734 if ((pvr & 0xe000) == 0) { 735 /* Nimbus */ 736 if ((pvr & 0xfff) < 0x203) 737 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_STQ_BUG; 738 } else if ((pvr & 0xc000) == 0) { 739 /* Cumulus */ 740 if ((pvr & 0xfff) < 0x103) 741 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_STQ_BUG; 742 } else { 743 WARN_ONCE(1, "Unknown PVR"); 744 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_STQ_BUG; 745 } 746 747 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_ERAT_BUG; 748 } 749 } 750 751 static __init void cpufeatures_cpu_quirks(void) 752 { 753 unsigned long version = mfspr(SPRN_PVR); 754 755 /* 756 * Not all quirks can be derived from the cpufeatures device tree. 757 */ 758 if ((version & 0xffffefff) == 0x004e0200) { 759 /* DD2.0 has no feature flag */ 760 cur_cpu_spec->cpu_features |= CPU_FTR_P9_RADIX_PREFETCH_BUG; 761 } else if ((version & 0xffffefff) == 0x004e0201) { 762 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1; 763 cur_cpu_spec->cpu_features |= CPU_FTR_P9_RADIX_PREFETCH_BUG; 764 } else if ((version & 0xffffefff) == 0x004e0202) { 765 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TM_HV_ASSIST; 766 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TM_XER_SO_BUG; 767 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1; 768 } else if ((version & 0xffff0000) == 0x004e0000) { 769 /* DD2.1 and up have DD2_1 */ 770 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1; 771 } 772 773 if ((version & 0xffff0000) == 0x004e0000) { 774 cur_cpu_spec->cpu_features &= ~(CPU_FTR_DAWR); 775 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TIDR; 776 } 777 778 update_tlbie_feature_flag(version); 779 /* 780 * PKEY was not in the initial base or feature node 781 * specification, but it should become optional in the next 782 * cpu feature version sequence. 783 */ 784 cur_cpu_spec->cpu_features |= CPU_FTR_PKEY; 785 } 786 787 static void __init cpufeatures_setup_finished(void) 788 { 789 cpufeatures_cpu_quirks(); 790 791 if (hv_mode && !(cur_cpu_spec->cpu_features & CPU_FTR_HVMODE)) { 792 pr_err("hypervisor not present in device tree but HV mode is enabled in the CPU. Enabling.\n"); 793 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE; 794 } 795 796 /* Make sure powerpc_base_platform is non-NULL */ 797 powerpc_base_platform = cur_cpu_spec->platform; 798 799 system_registers.lpcr = mfspr(SPRN_LPCR); 800 system_registers.hfscr = mfspr(SPRN_HFSCR); 801 system_registers.fscr = mfspr(SPRN_FSCR); 802 system_registers.pcr = mfspr(SPRN_PCR); 803 804 pr_info("final cpu/mmu features = 0x%016lx 0x%08x\n", 805 cur_cpu_spec->cpu_features, cur_cpu_spec->mmu_features); 806 } 807 808 static int __init disabled_on_cmdline(void) 809 { 810 unsigned long root, chosen; 811 const char *p; 812 813 root = of_get_flat_dt_root(); 814 chosen = of_get_flat_dt_subnode_by_name(root, "chosen"); 815 if (chosen == -FDT_ERR_NOTFOUND) 816 return false; 817 818 p = of_get_flat_dt_prop(chosen, "bootargs", NULL); 819 if (!p) 820 return false; 821 822 if (strstr(p, "dt_cpu_ftrs=off")) 823 return true; 824 825 return false; 826 } 827 828 static int __init fdt_find_cpu_features(unsigned long node, const char *uname, 829 int depth, void *data) 830 { 831 if (of_flat_dt_is_compatible(node, "ibm,powerpc-cpu-features") 832 && of_get_flat_dt_prop(node, "isa", NULL)) 833 return 1; 834 835 return 0; 836 } 837 838 bool __init dt_cpu_ftrs_in_use(void) 839 { 840 return using_dt_cpu_ftrs; 841 } 842 843 bool __init dt_cpu_ftrs_init(void *fdt) 844 { 845 using_dt_cpu_ftrs = false; 846 847 /* Setup and verify the FDT, if it fails we just bail */ 848 if (!early_init_dt_verify(fdt)) 849 return false; 850 851 if (!of_scan_flat_dt(fdt_find_cpu_features, NULL)) 852 return false; 853 854 if (disabled_on_cmdline()) 855 return false; 856 857 cpufeatures_setup_cpu(); 858 859 using_dt_cpu_ftrs = true; 860 return true; 861 } 862 863 static int nr_dt_cpu_features; 864 static struct dt_cpu_feature *dt_cpu_features; 865 866 static int __init process_cpufeatures_node(unsigned long node, 867 const char *uname, int i) 868 { 869 const __be32 *prop; 870 struct dt_cpu_feature *f; 871 int len; 872 873 f = &dt_cpu_features[i]; 874 875 f->node = node; 876 877 f->name = uname; 878 879 prop = of_get_flat_dt_prop(node, "isa", &len); 880 if (!prop) { 881 pr_warn("%s: missing isa property\n", uname); 882 return 0; 883 } 884 f->isa = be32_to_cpup(prop); 885 886 prop = of_get_flat_dt_prop(node, "usable-privilege", &len); 887 if (!prop) { 888 pr_warn("%s: missing usable-privilege property", uname); 889 return 0; 890 } 891 f->usable_privilege = be32_to_cpup(prop); 892 893 prop = of_get_flat_dt_prop(node, "hv-support", &len); 894 if (prop) 895 f->hv_support = be32_to_cpup(prop); 896 else 897 f->hv_support = HV_SUPPORT_NONE; 898 899 prop = of_get_flat_dt_prop(node, "os-support", &len); 900 if (prop) 901 f->os_support = be32_to_cpup(prop); 902 else 903 f->os_support = OS_SUPPORT_NONE; 904 905 prop = of_get_flat_dt_prop(node, "hfscr-bit-nr", &len); 906 if (prop) 907 f->hfscr_bit_nr = be32_to_cpup(prop); 908 else 909 f->hfscr_bit_nr = -1; 910 prop = of_get_flat_dt_prop(node, "fscr-bit-nr", &len); 911 if (prop) 912 f->fscr_bit_nr = be32_to_cpup(prop); 913 else 914 f->fscr_bit_nr = -1; 915 prop = of_get_flat_dt_prop(node, "hwcap-bit-nr", &len); 916 if (prop) 917 f->hwcap_bit_nr = be32_to_cpup(prop); 918 else 919 f->hwcap_bit_nr = -1; 920 921 if (f->usable_privilege & USABLE_HV) { 922 if (!(mfmsr() & MSR_HV)) { 923 pr_warn("%s: HV feature passed to guest\n", uname); 924 return 0; 925 } 926 927 if (f->hv_support == HV_SUPPORT_NONE && f->hfscr_bit_nr != -1) { 928 pr_warn("%s: unwanted hfscr_bit_nr\n", uname); 929 return 0; 930 } 931 932 if (f->hv_support == HV_SUPPORT_HFSCR) { 933 if (f->hfscr_bit_nr == -1) { 934 pr_warn("%s: missing hfscr_bit_nr\n", uname); 935 return 0; 936 } 937 } 938 } else { 939 if (f->hv_support != HV_SUPPORT_NONE || f->hfscr_bit_nr != -1) { 940 pr_warn("%s: unwanted hv_support/hfscr_bit_nr\n", uname); 941 return 0; 942 } 943 } 944 945 if (f->usable_privilege & USABLE_OS) { 946 if (f->os_support == OS_SUPPORT_NONE && f->fscr_bit_nr != -1) { 947 pr_warn("%s: unwanted fscr_bit_nr\n", uname); 948 return 0; 949 } 950 951 if (f->os_support == OS_SUPPORT_FSCR) { 952 if (f->fscr_bit_nr == -1) { 953 pr_warn("%s: missing fscr_bit_nr\n", uname); 954 return 0; 955 } 956 } 957 } else { 958 if (f->os_support != OS_SUPPORT_NONE || f->fscr_bit_nr != -1) { 959 pr_warn("%s: unwanted os_support/fscr_bit_nr\n", uname); 960 return 0; 961 } 962 } 963 964 if (!(f->usable_privilege & USABLE_PR)) { 965 if (f->hwcap_bit_nr != -1) { 966 pr_warn("%s: unwanted hwcap_bit_nr\n", uname); 967 return 0; 968 } 969 } 970 971 /* Do all the independent features in the first pass */ 972 if (!of_get_flat_dt_prop(node, "dependencies", &len)) { 973 if (cpufeatures_process_feature(f)) 974 f->enabled = 1; 975 else 976 f->disabled = 1; 977 } 978 979 return 0; 980 } 981 982 static void __init cpufeatures_deps_enable(struct dt_cpu_feature *f) 983 { 984 const __be32 *prop; 985 int len; 986 int nr_deps; 987 int i; 988 989 if (f->enabled || f->disabled) 990 return; 991 992 prop = of_get_flat_dt_prop(f->node, "dependencies", &len); 993 if (!prop) { 994 pr_warn("%s: missing dependencies property", f->name); 995 return; 996 } 997 998 nr_deps = len / sizeof(int); 999 1000 for (i = 0; i < nr_deps; i++) { 1001 unsigned long phandle = be32_to_cpu(prop[i]); 1002 int j; 1003 1004 for (j = 0; j < nr_dt_cpu_features; j++) { 1005 struct dt_cpu_feature *d = &dt_cpu_features[j]; 1006 1007 if (of_get_flat_dt_phandle(d->node) == phandle) { 1008 cpufeatures_deps_enable(d); 1009 if (d->disabled) { 1010 f->disabled = 1; 1011 return; 1012 } 1013 } 1014 } 1015 } 1016 1017 if (cpufeatures_process_feature(f)) 1018 f->enabled = 1; 1019 else 1020 f->disabled = 1; 1021 } 1022 1023 static int __init scan_cpufeatures_subnodes(unsigned long node, 1024 const char *uname, 1025 void *data) 1026 { 1027 int *count = data; 1028 1029 process_cpufeatures_node(node, uname, *count); 1030 1031 (*count)++; 1032 1033 return 0; 1034 } 1035 1036 static int __init count_cpufeatures_subnodes(unsigned long node, 1037 const char *uname, 1038 void *data) 1039 { 1040 int *count = data; 1041 1042 (*count)++; 1043 1044 return 0; 1045 } 1046 1047 static int __init dt_cpu_ftrs_scan_callback(unsigned long node, const char 1048 *uname, int depth, void *data) 1049 { 1050 const __be32 *prop; 1051 int count, i; 1052 u32 isa; 1053 1054 /* We are scanning "ibm,powerpc-cpu-features" nodes only */ 1055 if (!of_flat_dt_is_compatible(node, "ibm,powerpc-cpu-features")) 1056 return 0; 1057 1058 prop = of_get_flat_dt_prop(node, "isa", NULL); 1059 if (!prop) 1060 /* We checked before, "can't happen" */ 1061 return 0; 1062 1063 isa = be32_to_cpup(prop); 1064 1065 /* Count and allocate space for cpu features */ 1066 of_scan_flat_dt_subnodes(node, count_cpufeatures_subnodes, 1067 &nr_dt_cpu_features); 1068 dt_cpu_features = memblock_alloc(sizeof(struct dt_cpu_feature) * nr_dt_cpu_features, PAGE_SIZE); 1069 if (!dt_cpu_features) 1070 panic("%s: Failed to allocate %zu bytes align=0x%lx\n", 1071 __func__, 1072 sizeof(struct dt_cpu_feature) * nr_dt_cpu_features, 1073 PAGE_SIZE); 1074 1075 cpufeatures_setup_start(isa); 1076 1077 /* Scan nodes into dt_cpu_features and enable those without deps */ 1078 count = 0; 1079 of_scan_flat_dt_subnodes(node, scan_cpufeatures_subnodes, &count); 1080 1081 /* Recursive enable remaining features with dependencies */ 1082 for (i = 0; i < nr_dt_cpu_features; i++) { 1083 struct dt_cpu_feature *f = &dt_cpu_features[i]; 1084 1085 cpufeatures_deps_enable(f); 1086 } 1087 1088 prop = of_get_flat_dt_prop(node, "display-name", NULL); 1089 if (prop && strlen((char *)prop) != 0) { 1090 strlcpy(dt_cpu_name, (char *)prop, sizeof(dt_cpu_name)); 1091 cur_cpu_spec->cpu_name = dt_cpu_name; 1092 } 1093 1094 cpufeatures_setup_finished(); 1095 1096 memblock_free(__pa(dt_cpu_features), 1097 sizeof(struct dt_cpu_feature)*nr_dt_cpu_features); 1098 1099 return 0; 1100 } 1101 1102 void __init dt_cpu_ftrs_scan(void) 1103 { 1104 if (!using_dt_cpu_ftrs) 1105 return; 1106 1107 of_scan_flat_dt(dt_cpu_ftrs_scan_callback, NULL); 1108 } 1109