1 /* 2 * Copyright 2017, Nicholas Piggin, IBM Corporation 3 * Licensed under GPLv2. 4 */ 5 6 #define pr_fmt(fmt) "dt-cpu-ftrs: " fmt 7 8 #include <linux/export.h> 9 #include <linux/init.h> 10 #include <linux/jump_label.h> 11 #include <linux/libfdt.h> 12 #include <linux/memblock.h> 13 #include <linux/printk.h> 14 #include <linux/sched.h> 15 #include <linux/string.h> 16 #include <linux/threads.h> 17 18 #include <asm/cputable.h> 19 #include <asm/dt_cpu_ftrs.h> 20 #include <asm/mmu.h> 21 #include <asm/oprofile_impl.h> 22 #include <asm/prom.h> 23 #include <asm/setup.h> 24 25 26 /* Device-tree visible constants follow */ 27 #define ISA_V2_07B 2070 28 #define ISA_V3_0B 3000 29 30 #define USABLE_PR (1U << 0) 31 #define USABLE_OS (1U << 1) 32 #define USABLE_HV (1U << 2) 33 34 #define HV_SUPPORT_HFSCR (1U << 0) 35 #define OS_SUPPORT_FSCR (1U << 0) 36 37 /* For parsing, we define all bits set as "NONE" case */ 38 #define HV_SUPPORT_NONE 0xffffffffU 39 #define OS_SUPPORT_NONE 0xffffffffU 40 41 struct dt_cpu_feature { 42 const char *name; 43 uint32_t isa; 44 uint32_t usable_privilege; 45 uint32_t hv_support; 46 uint32_t os_support; 47 uint32_t hfscr_bit_nr; 48 uint32_t fscr_bit_nr; 49 uint32_t hwcap_bit_nr; 50 /* fdt parsing */ 51 unsigned long node; 52 int enabled; 53 int disabled; 54 }; 55 56 #define CPU_FTRS_BASE \ 57 (CPU_FTR_USE_TB | \ 58 CPU_FTR_LWSYNC | \ 59 CPU_FTR_FPU_UNAVAILABLE |\ 60 CPU_FTR_NODSISRALIGN |\ 61 CPU_FTR_NOEXECUTE |\ 62 CPU_FTR_COHERENT_ICACHE | \ 63 CPU_FTR_STCX_CHECKS_ADDRESS |\ 64 CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 65 CPU_FTR_DAWR | \ 66 CPU_FTR_ARCH_206 |\ 67 CPU_FTR_ARCH_207S) 68 69 #define MMU_FTRS_HASH_BASE (MMU_FTRS_POWER8) 70 71 #define COMMON_USER_BASE (PPC_FEATURE_32 | PPC_FEATURE_64 | \ 72 PPC_FEATURE_ARCH_2_06 |\ 73 PPC_FEATURE_ICACHE_SNOOP) 74 #define COMMON_USER2_BASE (PPC_FEATURE2_ARCH_2_07 | \ 75 PPC_FEATURE2_ISEL) 76 /* 77 * Set up the base CPU 78 */ 79 80 extern void __flush_tlb_power8(unsigned int action); 81 extern void __flush_tlb_power9(unsigned int action); 82 extern long __machine_check_early_realmode_p8(struct pt_regs *regs); 83 extern long __machine_check_early_realmode_p9(struct pt_regs *regs); 84 85 static int hv_mode; 86 87 static struct { 88 u64 lpcr; 89 u64 hfscr; 90 u64 fscr; 91 } system_registers; 92 93 static void (*init_pmu_registers)(void); 94 95 static void cpufeatures_flush_tlb(void) 96 { 97 /* 98 * This is a temporary measure to keep equivalent TLB flush as the 99 * cputable based setup code. 100 */ 101 switch (PVR_VER(mfspr(SPRN_PVR))) { 102 case PVR_POWER8: 103 case PVR_POWER8E: 104 case PVR_POWER8NVL: 105 __flush_tlb_power8(TLB_INVAL_SCOPE_GLOBAL); 106 break; 107 case PVR_POWER9: 108 __flush_tlb_power9(TLB_INVAL_SCOPE_GLOBAL); 109 break; 110 default: 111 pr_err("unknown CPU version for boot TLB flush\n"); 112 break; 113 } 114 } 115 116 static void __restore_cpu_cpufeatures(void) 117 { 118 /* 119 * LPCR is restored by the power on engine already. It can be changed 120 * after early init e.g., by radix enable, and we have no unified API 121 * for saving and restoring such SPRs. 122 * 123 * This ->restore hook should really be removed from idle and register 124 * restore moved directly into the idle restore code, because this code 125 * doesn't know how idle is implemented or what it needs restored here. 126 * 127 * The best we can do to accommodate secondary boot and idle restore 128 * for now is "or" LPCR with existing. 129 */ 130 131 mtspr(SPRN_LPCR, system_registers.lpcr | mfspr(SPRN_LPCR)); 132 if (hv_mode) { 133 mtspr(SPRN_LPID, 0); 134 mtspr(SPRN_HFSCR, system_registers.hfscr); 135 } 136 mtspr(SPRN_FSCR, system_registers.fscr); 137 138 if (init_pmu_registers) 139 init_pmu_registers(); 140 141 cpufeatures_flush_tlb(); 142 } 143 144 static char dt_cpu_name[64]; 145 146 static struct cpu_spec __initdata base_cpu_spec = { 147 .cpu_name = NULL, 148 .cpu_features = CPU_FTRS_BASE, 149 .cpu_user_features = COMMON_USER_BASE, 150 .cpu_user_features2 = COMMON_USER2_BASE, 151 .mmu_features = 0, 152 .icache_bsize = 32, /* minimum block size, fixed by */ 153 .dcache_bsize = 32, /* cache info init. */ 154 .num_pmcs = 0, 155 .pmc_type = PPC_PMC_DEFAULT, 156 .oprofile_cpu_type = NULL, 157 .oprofile_type = PPC_OPROFILE_INVALID, 158 .cpu_setup = NULL, 159 .cpu_restore = __restore_cpu_cpufeatures, 160 .flush_tlb = NULL, 161 .machine_check_early = NULL, 162 .platform = NULL, 163 }; 164 165 static void __init cpufeatures_setup_cpu(void) 166 { 167 set_cur_cpu_spec(&base_cpu_spec); 168 169 cur_cpu_spec->pvr_mask = -1; 170 cur_cpu_spec->pvr_value = mfspr(SPRN_PVR); 171 172 /* Initialize the base environment -- clear FSCR/HFSCR. */ 173 hv_mode = !!(mfmsr() & MSR_HV); 174 if (hv_mode) { 175 /* CPU_FTR_HVMODE is used early in PACA setup */ 176 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE; 177 mtspr(SPRN_HFSCR, 0); 178 } 179 mtspr(SPRN_FSCR, 0); 180 181 /* 182 * LPCR does not get cleared, to match behaviour with secondaries 183 * in __restore_cpu_cpufeatures. Once the idle code is fixed, this 184 * could clear LPCR too. 185 */ 186 } 187 188 static int __init feat_try_enable_unknown(struct dt_cpu_feature *f) 189 { 190 if (f->hv_support == HV_SUPPORT_NONE) { 191 } else if (f->hv_support & HV_SUPPORT_HFSCR) { 192 u64 hfscr = mfspr(SPRN_HFSCR); 193 hfscr |= 1UL << f->hfscr_bit_nr; 194 mtspr(SPRN_HFSCR, hfscr); 195 } else { 196 /* Does not have a known recipe */ 197 return 0; 198 } 199 200 if (f->os_support == OS_SUPPORT_NONE) { 201 } else if (f->os_support & OS_SUPPORT_FSCR) { 202 u64 fscr = mfspr(SPRN_FSCR); 203 fscr |= 1UL << f->fscr_bit_nr; 204 mtspr(SPRN_FSCR, fscr); 205 } else { 206 /* Does not have a known recipe */ 207 return 0; 208 } 209 210 if ((f->usable_privilege & USABLE_PR) && (f->hwcap_bit_nr != -1)) { 211 uint32_t word = f->hwcap_bit_nr / 32; 212 uint32_t bit = f->hwcap_bit_nr % 32; 213 214 if (word == 0) 215 cur_cpu_spec->cpu_user_features |= 1U << bit; 216 else if (word == 1) 217 cur_cpu_spec->cpu_user_features2 |= 1U << bit; 218 else 219 pr_err("%s could not advertise to user (no hwcap bits)\n", f->name); 220 } 221 222 return 1; 223 } 224 225 static int __init feat_enable(struct dt_cpu_feature *f) 226 { 227 if (f->hv_support != HV_SUPPORT_NONE) { 228 if (f->hfscr_bit_nr != -1) { 229 u64 hfscr = mfspr(SPRN_HFSCR); 230 hfscr |= 1UL << f->hfscr_bit_nr; 231 mtspr(SPRN_HFSCR, hfscr); 232 } 233 } 234 235 if (f->os_support != OS_SUPPORT_NONE) { 236 if (f->fscr_bit_nr != -1) { 237 u64 fscr = mfspr(SPRN_FSCR); 238 fscr |= 1UL << f->fscr_bit_nr; 239 mtspr(SPRN_FSCR, fscr); 240 } 241 } 242 243 if ((f->usable_privilege & USABLE_PR) && (f->hwcap_bit_nr != -1)) { 244 uint32_t word = f->hwcap_bit_nr / 32; 245 uint32_t bit = f->hwcap_bit_nr % 32; 246 247 if (word == 0) 248 cur_cpu_spec->cpu_user_features |= 1U << bit; 249 else if (word == 1) 250 cur_cpu_spec->cpu_user_features2 |= 1U << bit; 251 else 252 pr_err("CPU feature: %s could not advertise to user (no hwcap bits)\n", f->name); 253 } 254 255 return 1; 256 } 257 258 static int __init feat_disable(struct dt_cpu_feature *f) 259 { 260 return 0; 261 } 262 263 static int __init feat_enable_hv(struct dt_cpu_feature *f) 264 { 265 u64 lpcr; 266 267 if (!hv_mode) { 268 pr_err("CPU feature hypervisor present in device tree but HV mode not enabled in the CPU. Ignoring.\n"); 269 return 0; 270 } 271 272 mtspr(SPRN_LPID, 0); 273 274 lpcr = mfspr(SPRN_LPCR); 275 lpcr &= ~LPCR_LPES0; /* HV external interrupts */ 276 mtspr(SPRN_LPCR, lpcr); 277 278 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE; 279 280 return 1; 281 } 282 283 static int __init feat_enable_le(struct dt_cpu_feature *f) 284 { 285 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_TRUE_LE; 286 return 1; 287 } 288 289 static int __init feat_enable_smt(struct dt_cpu_feature *f) 290 { 291 cur_cpu_spec->cpu_features |= CPU_FTR_SMT; 292 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_SMT; 293 return 1; 294 } 295 296 static int __init feat_enable_idle_nap(struct dt_cpu_feature *f) 297 { 298 u64 lpcr; 299 300 /* Set PECE wakeup modes for ISA 207 */ 301 lpcr = mfspr(SPRN_LPCR); 302 lpcr |= LPCR_PECE0; 303 lpcr |= LPCR_PECE1; 304 lpcr |= LPCR_PECE2; 305 mtspr(SPRN_LPCR, lpcr); 306 307 return 1; 308 } 309 310 static int __init feat_enable_align_dsisr(struct dt_cpu_feature *f) 311 { 312 cur_cpu_spec->cpu_features &= ~CPU_FTR_NODSISRALIGN; 313 314 return 1; 315 } 316 317 static int __init feat_enable_idle_stop(struct dt_cpu_feature *f) 318 { 319 u64 lpcr; 320 321 /* Set PECE wakeup modes for ISAv3.0B */ 322 lpcr = mfspr(SPRN_LPCR); 323 lpcr |= LPCR_PECE0; 324 lpcr |= LPCR_PECE1; 325 lpcr |= LPCR_PECE2; 326 mtspr(SPRN_LPCR, lpcr); 327 328 return 1; 329 } 330 331 static int __init feat_enable_mmu_hash(struct dt_cpu_feature *f) 332 { 333 u64 lpcr; 334 335 lpcr = mfspr(SPRN_LPCR); 336 lpcr &= ~LPCR_ISL; 337 338 /* VRMASD */ 339 lpcr |= LPCR_VPM0; 340 lpcr &= ~LPCR_VPM1; 341 lpcr |= 0x10UL << LPCR_VRMASD_SH; /* L=1 LP=00 */ 342 mtspr(SPRN_LPCR, lpcr); 343 344 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE; 345 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU; 346 347 return 1; 348 } 349 350 static int __init feat_enable_mmu_hash_v3(struct dt_cpu_feature *f) 351 { 352 u64 lpcr; 353 354 lpcr = mfspr(SPRN_LPCR); 355 lpcr &= ~LPCR_ISL; 356 mtspr(SPRN_LPCR, lpcr); 357 358 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE; 359 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU; 360 361 return 1; 362 } 363 364 365 static int __init feat_enable_mmu_radix(struct dt_cpu_feature *f) 366 { 367 #ifdef CONFIG_PPC_RADIX_MMU 368 cur_cpu_spec->mmu_features |= MMU_FTR_TYPE_RADIX; 369 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE; 370 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU; 371 372 return 1; 373 #endif 374 return 0; 375 } 376 377 static int __init feat_enable_dscr(struct dt_cpu_feature *f) 378 { 379 u64 lpcr; 380 381 feat_enable(f); 382 383 lpcr = mfspr(SPRN_LPCR); 384 lpcr &= ~LPCR_DPFD; 385 lpcr |= (4UL << LPCR_DPFD_SH); 386 mtspr(SPRN_LPCR, lpcr); 387 388 return 1; 389 } 390 391 static void hfscr_pmu_enable(void) 392 { 393 u64 hfscr = mfspr(SPRN_HFSCR); 394 hfscr |= PPC_BIT(60); 395 mtspr(SPRN_HFSCR, hfscr); 396 } 397 398 static void init_pmu_power8(void) 399 { 400 if (hv_mode) { 401 mtspr(SPRN_MMCRC, 0); 402 mtspr(SPRN_MMCRH, 0); 403 } 404 405 mtspr(SPRN_MMCRA, 0); 406 mtspr(SPRN_MMCR0, 0); 407 mtspr(SPRN_MMCR1, 0); 408 mtspr(SPRN_MMCR2, 0); 409 mtspr(SPRN_MMCRS, 0); 410 } 411 412 static int __init feat_enable_mce_power8(struct dt_cpu_feature *f) 413 { 414 cur_cpu_spec->platform = "power8"; 415 cur_cpu_spec->flush_tlb = __flush_tlb_power8; 416 cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p8; 417 418 return 1; 419 } 420 421 static int __init feat_enable_pmu_power8(struct dt_cpu_feature *f) 422 { 423 hfscr_pmu_enable(); 424 425 init_pmu_power8(); 426 init_pmu_registers = init_pmu_power8; 427 428 cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA; 429 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT; 430 if (pvr_version_is(PVR_POWER8E)) 431 cur_cpu_spec->cpu_features |= CPU_FTR_PMAO_BUG; 432 433 cur_cpu_spec->num_pmcs = 6; 434 cur_cpu_spec->pmc_type = PPC_PMC_IBM; 435 cur_cpu_spec->oprofile_cpu_type = "ppc64/power8"; 436 437 return 1; 438 } 439 440 static void init_pmu_power9(void) 441 { 442 if (hv_mode) 443 mtspr(SPRN_MMCRC, 0); 444 445 mtspr(SPRN_MMCRA, 0); 446 mtspr(SPRN_MMCR0, 0); 447 mtspr(SPRN_MMCR1, 0); 448 mtspr(SPRN_MMCR2, 0); 449 } 450 451 static int __init feat_enable_mce_power9(struct dt_cpu_feature *f) 452 { 453 cur_cpu_spec->platform = "power9"; 454 cur_cpu_spec->flush_tlb = __flush_tlb_power9; 455 cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p9; 456 457 return 1; 458 } 459 460 static int __init feat_enable_pmu_power9(struct dt_cpu_feature *f) 461 { 462 hfscr_pmu_enable(); 463 464 init_pmu_power9(); 465 init_pmu_registers = init_pmu_power9; 466 467 cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA; 468 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT; 469 470 cur_cpu_spec->num_pmcs = 6; 471 cur_cpu_spec->pmc_type = PPC_PMC_IBM; 472 cur_cpu_spec->oprofile_cpu_type = "ppc64/power9"; 473 474 return 1; 475 } 476 477 static int __init feat_enable_tm(struct dt_cpu_feature *f) 478 { 479 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 480 feat_enable(f); 481 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NOSC; 482 return 1; 483 #endif 484 return 0; 485 } 486 487 static int __init feat_enable_fp(struct dt_cpu_feature *f) 488 { 489 feat_enable(f); 490 cur_cpu_spec->cpu_features &= ~CPU_FTR_FPU_UNAVAILABLE; 491 492 return 1; 493 } 494 495 static int __init feat_enable_vector(struct dt_cpu_feature *f) 496 { 497 #ifdef CONFIG_ALTIVEC 498 feat_enable(f); 499 cur_cpu_spec->cpu_features |= CPU_FTR_ALTIVEC; 500 cur_cpu_spec->cpu_features |= CPU_FTR_VMX_COPY; 501 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_ALTIVEC; 502 503 return 1; 504 #endif 505 return 0; 506 } 507 508 static int __init feat_enable_vsx(struct dt_cpu_feature *f) 509 { 510 #ifdef CONFIG_VSX 511 feat_enable(f); 512 cur_cpu_spec->cpu_features |= CPU_FTR_VSX; 513 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_VSX; 514 515 return 1; 516 #endif 517 return 0; 518 } 519 520 static int __init feat_enable_purr(struct dt_cpu_feature *f) 521 { 522 cur_cpu_spec->cpu_features |= CPU_FTR_PURR | CPU_FTR_SPURR; 523 524 return 1; 525 } 526 527 static int __init feat_enable_ebb(struct dt_cpu_feature *f) 528 { 529 /* 530 * PPC_FEATURE2_EBB is enabled in PMU init code because it has 531 * historically been related to the PMU facility. This may have 532 * to be decoupled if EBB becomes more generic. For now, follow 533 * existing convention. 534 */ 535 f->hwcap_bit_nr = -1; 536 feat_enable(f); 537 538 return 1; 539 } 540 541 static int __init feat_enable_dbell(struct dt_cpu_feature *f) 542 { 543 u64 lpcr; 544 545 /* P9 has an HFSCR for privileged state */ 546 feat_enable(f); 547 548 cur_cpu_spec->cpu_features |= CPU_FTR_DBELL; 549 550 lpcr = mfspr(SPRN_LPCR); 551 lpcr |= LPCR_PECEDH; /* hyp doorbell wakeup */ 552 mtspr(SPRN_LPCR, lpcr); 553 554 return 1; 555 } 556 557 static int __init feat_enable_hvi(struct dt_cpu_feature *f) 558 { 559 u64 lpcr; 560 561 /* 562 * POWER9 XIVE interrupts including in OPAL XICS compatibility 563 * are always delivered as hypervisor virtualization interrupts (HVI) 564 * rather than EE. 565 * 566 * However LPES0 is not set here, in the chance that an EE does get 567 * delivered to the host somehow, the EE handler would not expect it 568 * to be delivered in LPES0 mode (e.g., using SRR[01]). This could 569 * happen if there is a bug in interrupt controller code, or IC is 570 * misconfigured in systemsim. 571 */ 572 573 lpcr = mfspr(SPRN_LPCR); 574 lpcr |= LPCR_HVICE; /* enable hvi interrupts */ 575 lpcr |= LPCR_HEIC; /* disable ee interrupts when MSR_HV */ 576 lpcr |= LPCR_PECE_HVEE; /* hvi can wake from stop */ 577 mtspr(SPRN_LPCR, lpcr); 578 579 return 1; 580 } 581 582 static int __init feat_enable_large_ci(struct dt_cpu_feature *f) 583 { 584 cur_cpu_spec->mmu_features |= MMU_FTR_CI_LARGE_PAGE; 585 586 return 1; 587 } 588 589 struct dt_cpu_feature_match { 590 const char *name; 591 int (*enable)(struct dt_cpu_feature *f); 592 u64 cpu_ftr_bit_mask; 593 }; 594 595 static struct dt_cpu_feature_match __initdata 596 dt_cpu_feature_match_table[] = { 597 {"hypervisor", feat_enable_hv, 0}, 598 {"big-endian", feat_enable, 0}, 599 {"little-endian", feat_enable_le, CPU_FTR_REAL_LE}, 600 {"smt", feat_enable_smt, 0}, 601 {"interrupt-facilities", feat_enable, 0}, 602 {"timer-facilities", feat_enable, 0}, 603 {"timer-facilities-v3", feat_enable, 0}, 604 {"debug-facilities", feat_enable, 0}, 605 {"come-from-address-register", feat_enable, CPU_FTR_CFAR}, 606 {"branch-tracing", feat_enable, 0}, 607 {"floating-point", feat_enable_fp, 0}, 608 {"vector", feat_enable_vector, 0}, 609 {"vector-scalar", feat_enable_vsx, 0}, 610 {"vector-scalar-v3", feat_enable, 0}, 611 {"decimal-floating-point", feat_enable, 0}, 612 {"decimal-integer", feat_enable, 0}, 613 {"quadword-load-store", feat_enable, 0}, 614 {"vector-crypto", feat_enable, 0}, 615 {"mmu-hash", feat_enable_mmu_hash, 0}, 616 {"mmu-radix", feat_enable_mmu_radix, 0}, 617 {"mmu-hash-v3", feat_enable_mmu_hash_v3, 0}, 618 {"virtual-page-class-key-protection", feat_enable, 0}, 619 {"transactional-memory", feat_enable_tm, CPU_FTR_TM}, 620 {"transactional-memory-v3", feat_enable_tm, 0}, 621 {"idle-nap", feat_enable_idle_nap, 0}, 622 {"alignment-interrupt-dsisr", feat_enable_align_dsisr, 0}, 623 {"idle-stop", feat_enable_idle_stop, 0}, 624 {"machine-check-power8", feat_enable_mce_power8, 0}, 625 {"performance-monitor-power8", feat_enable_pmu_power8, 0}, 626 {"data-stream-control-register", feat_enable_dscr, CPU_FTR_DSCR}, 627 {"event-based-branch", feat_enable_ebb, 0}, 628 {"target-address-register", feat_enable, 0}, 629 {"branch-history-rolling-buffer", feat_enable, 0}, 630 {"control-register", feat_enable, CPU_FTR_CTRL}, 631 {"processor-control-facility", feat_enable_dbell, CPU_FTR_DBELL}, 632 {"processor-control-facility-v3", feat_enable_dbell, CPU_FTR_DBELL}, 633 {"processor-utilization-of-resources-register", feat_enable_purr, 0}, 634 {"no-execute", feat_enable, 0}, 635 {"strong-access-ordering", feat_enable, CPU_FTR_SAO}, 636 {"cache-inhibited-large-page", feat_enable_large_ci, 0}, 637 {"coprocessor-icswx", feat_enable, CPU_FTR_ICSWX}, 638 {"hypervisor-virtualization-interrupt", feat_enable_hvi, 0}, 639 {"program-priority-register", feat_enable, CPU_FTR_HAS_PPR}, 640 {"wait", feat_enable, 0}, 641 {"atomic-memory-operations", feat_enable, 0}, 642 {"branch-v3", feat_enable, 0}, 643 {"copy-paste", feat_enable, 0}, 644 {"decimal-floating-point-v3", feat_enable, 0}, 645 {"decimal-integer-v3", feat_enable, 0}, 646 {"fixed-point-v3", feat_enable, 0}, 647 {"floating-point-v3", feat_enable, 0}, 648 {"group-start-register", feat_enable, 0}, 649 {"pc-relative-addressing", feat_enable, 0}, 650 {"machine-check-power9", feat_enable_mce_power9, 0}, 651 {"performance-monitor-power9", feat_enable_pmu_power9, 0}, 652 {"event-based-branch-v3", feat_enable, 0}, 653 {"random-number-generator", feat_enable, 0}, 654 {"system-call-vectored", feat_disable, 0}, 655 {"trace-interrupt-v3", feat_enable, 0}, 656 {"vector-v3", feat_enable, 0}, 657 {"vector-binary128", feat_enable, 0}, 658 {"vector-binary16", feat_enable, 0}, 659 {"wait-v3", feat_enable, 0}, 660 }; 661 662 static bool __initdata using_dt_cpu_ftrs; 663 static bool __initdata enable_unknown = true; 664 665 static int __init dt_cpu_ftrs_parse(char *str) 666 { 667 if (!str) 668 return 0; 669 670 if (!strcmp(str, "off")) 671 using_dt_cpu_ftrs = false; 672 else if (!strcmp(str, "known")) 673 enable_unknown = false; 674 else 675 return 1; 676 677 return 0; 678 } 679 early_param("dt_cpu_ftrs", dt_cpu_ftrs_parse); 680 681 static void __init cpufeatures_setup_start(u32 isa) 682 { 683 pr_info("setup for ISA %d\n", isa); 684 685 if (isa >= 3000) { 686 cur_cpu_spec->cpu_features |= CPU_FTR_ARCH_300; 687 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_ARCH_3_00; 688 } 689 } 690 691 static bool __init cpufeatures_process_feature(struct dt_cpu_feature *f) 692 { 693 const struct dt_cpu_feature_match *m; 694 bool known = false; 695 int i; 696 697 for (i = 0; i < ARRAY_SIZE(dt_cpu_feature_match_table); i++) { 698 m = &dt_cpu_feature_match_table[i]; 699 if (!strcmp(f->name, m->name)) { 700 known = true; 701 if (m->enable(f)) 702 break; 703 704 pr_info("not enabling: %s (disabled or unsupported by kernel)\n", 705 f->name); 706 return false; 707 } 708 } 709 710 if (!known && enable_unknown) { 711 if (!feat_try_enable_unknown(f)) { 712 pr_info("not enabling: %s (unknown and unsupported by kernel)\n", 713 f->name); 714 return false; 715 } 716 } 717 718 if (m->cpu_ftr_bit_mask) 719 cur_cpu_spec->cpu_features |= m->cpu_ftr_bit_mask; 720 721 if (known) 722 pr_debug("enabling: %s\n", f->name); 723 else 724 pr_debug("enabling: %s (unknown)\n", f->name); 725 726 return true; 727 } 728 729 static __init void cpufeatures_cpu_quirks(void) 730 { 731 int version = mfspr(SPRN_PVR); 732 733 /* 734 * Not all quirks can be derived from the cpufeatures device tree. 735 */ 736 if ((version & 0xffffff00) == 0x004e0100) 737 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD1; 738 } 739 740 static void __init cpufeatures_setup_finished(void) 741 { 742 cpufeatures_cpu_quirks(); 743 744 if (hv_mode && !(cur_cpu_spec->cpu_features & CPU_FTR_HVMODE)) { 745 pr_err("hypervisor not present in device tree but HV mode is enabled in the CPU. Enabling.\n"); 746 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE; 747 } 748 749 system_registers.lpcr = mfspr(SPRN_LPCR); 750 system_registers.hfscr = mfspr(SPRN_HFSCR); 751 system_registers.fscr = mfspr(SPRN_FSCR); 752 753 cpufeatures_flush_tlb(); 754 755 pr_info("final cpu/mmu features = 0x%016lx 0x%08x\n", 756 cur_cpu_spec->cpu_features, cur_cpu_spec->mmu_features); 757 } 758 759 static int __init disabled_on_cmdline(void) 760 { 761 unsigned long root, chosen; 762 const char *p; 763 764 root = of_get_flat_dt_root(); 765 chosen = of_get_flat_dt_subnode_by_name(root, "chosen"); 766 if (chosen == -FDT_ERR_NOTFOUND) 767 return false; 768 769 p = of_get_flat_dt_prop(chosen, "bootargs", NULL); 770 if (!p) 771 return false; 772 773 if (strstr(p, "dt_cpu_ftrs=off")) 774 return true; 775 776 return false; 777 } 778 779 static int __init fdt_find_cpu_features(unsigned long node, const char *uname, 780 int depth, void *data) 781 { 782 if (of_flat_dt_is_compatible(node, "ibm,powerpc-cpu-features") 783 && of_get_flat_dt_prop(node, "isa", NULL)) 784 return 1; 785 786 return 0; 787 } 788 789 bool __init dt_cpu_ftrs_in_use(void) 790 { 791 return using_dt_cpu_ftrs; 792 } 793 794 bool __init dt_cpu_ftrs_init(void *fdt) 795 { 796 using_dt_cpu_ftrs = false; 797 798 /* Setup and verify the FDT, if it fails we just bail */ 799 if (!early_init_dt_verify(fdt)) 800 return false; 801 802 if (!of_scan_flat_dt(fdt_find_cpu_features, NULL)) 803 return false; 804 805 if (disabled_on_cmdline()) 806 return false; 807 808 cpufeatures_setup_cpu(); 809 810 using_dt_cpu_ftrs = true; 811 return true; 812 } 813 814 static int nr_dt_cpu_features; 815 static struct dt_cpu_feature *dt_cpu_features; 816 817 static int __init process_cpufeatures_node(unsigned long node, 818 const char *uname, int i) 819 { 820 const __be32 *prop; 821 struct dt_cpu_feature *f; 822 int len; 823 824 f = &dt_cpu_features[i]; 825 memset(f, 0, sizeof(struct dt_cpu_feature)); 826 827 f->node = node; 828 829 f->name = uname; 830 831 prop = of_get_flat_dt_prop(node, "isa", &len); 832 if (!prop) { 833 pr_warn("%s: missing isa property\n", uname); 834 return 0; 835 } 836 f->isa = be32_to_cpup(prop); 837 838 prop = of_get_flat_dt_prop(node, "usable-privilege", &len); 839 if (!prop) { 840 pr_warn("%s: missing usable-privilege property", uname); 841 return 0; 842 } 843 f->usable_privilege = be32_to_cpup(prop); 844 845 prop = of_get_flat_dt_prop(node, "hv-support", &len); 846 if (prop) 847 f->hv_support = be32_to_cpup(prop); 848 else 849 f->hv_support = HV_SUPPORT_NONE; 850 851 prop = of_get_flat_dt_prop(node, "os-support", &len); 852 if (prop) 853 f->os_support = be32_to_cpup(prop); 854 else 855 f->os_support = OS_SUPPORT_NONE; 856 857 prop = of_get_flat_dt_prop(node, "hfscr-bit-nr", &len); 858 if (prop) 859 f->hfscr_bit_nr = be32_to_cpup(prop); 860 else 861 f->hfscr_bit_nr = -1; 862 prop = of_get_flat_dt_prop(node, "fscr-bit-nr", &len); 863 if (prop) 864 f->fscr_bit_nr = be32_to_cpup(prop); 865 else 866 f->fscr_bit_nr = -1; 867 prop = of_get_flat_dt_prop(node, "hwcap-bit-nr", &len); 868 if (prop) 869 f->hwcap_bit_nr = be32_to_cpup(prop); 870 else 871 f->hwcap_bit_nr = -1; 872 873 if (f->usable_privilege & USABLE_HV) { 874 if (!(mfmsr() & MSR_HV)) { 875 pr_warn("%s: HV feature passed to guest\n", uname); 876 return 0; 877 } 878 879 if (f->hv_support == HV_SUPPORT_NONE && f->hfscr_bit_nr != -1) { 880 pr_warn("%s: unwanted hfscr_bit_nr\n", uname); 881 return 0; 882 } 883 884 if (f->hv_support == HV_SUPPORT_HFSCR) { 885 if (f->hfscr_bit_nr == -1) { 886 pr_warn("%s: missing hfscr_bit_nr\n", uname); 887 return 0; 888 } 889 } 890 } else { 891 if (f->hv_support != HV_SUPPORT_NONE || f->hfscr_bit_nr != -1) { 892 pr_warn("%s: unwanted hv_support/hfscr_bit_nr\n", uname); 893 return 0; 894 } 895 } 896 897 if (f->usable_privilege & USABLE_OS) { 898 if (f->os_support == OS_SUPPORT_NONE && f->fscr_bit_nr != -1) { 899 pr_warn("%s: unwanted fscr_bit_nr\n", uname); 900 return 0; 901 } 902 903 if (f->os_support == OS_SUPPORT_FSCR) { 904 if (f->fscr_bit_nr == -1) { 905 pr_warn("%s: missing fscr_bit_nr\n", uname); 906 return 0; 907 } 908 } 909 } else { 910 if (f->os_support != OS_SUPPORT_NONE || f->fscr_bit_nr != -1) { 911 pr_warn("%s: unwanted os_support/fscr_bit_nr\n", uname); 912 return 0; 913 } 914 } 915 916 if (!(f->usable_privilege & USABLE_PR)) { 917 if (f->hwcap_bit_nr != -1) { 918 pr_warn("%s: unwanted hwcap_bit_nr\n", uname); 919 return 0; 920 } 921 } 922 923 /* Do all the independent features in the first pass */ 924 if (!of_get_flat_dt_prop(node, "dependencies", &len)) { 925 if (cpufeatures_process_feature(f)) 926 f->enabled = 1; 927 else 928 f->disabled = 1; 929 } 930 931 return 0; 932 } 933 934 static void __init cpufeatures_deps_enable(struct dt_cpu_feature *f) 935 { 936 const __be32 *prop; 937 int len; 938 int nr_deps; 939 int i; 940 941 if (f->enabled || f->disabled) 942 return; 943 944 prop = of_get_flat_dt_prop(f->node, "dependencies", &len); 945 if (!prop) { 946 pr_warn("%s: missing dependencies property", f->name); 947 return; 948 } 949 950 nr_deps = len / sizeof(int); 951 952 for (i = 0; i < nr_deps; i++) { 953 unsigned long phandle = be32_to_cpu(prop[i]); 954 int j; 955 956 for (j = 0; j < nr_dt_cpu_features; j++) { 957 struct dt_cpu_feature *d = &dt_cpu_features[j]; 958 959 if (of_get_flat_dt_phandle(d->node) == phandle) { 960 cpufeatures_deps_enable(d); 961 if (d->disabled) { 962 f->disabled = 1; 963 return; 964 } 965 } 966 } 967 } 968 969 if (cpufeatures_process_feature(f)) 970 f->enabled = 1; 971 else 972 f->disabled = 1; 973 } 974 975 static int __init scan_cpufeatures_subnodes(unsigned long node, 976 const char *uname, 977 void *data) 978 { 979 int *count = data; 980 981 process_cpufeatures_node(node, uname, *count); 982 983 (*count)++; 984 985 return 0; 986 } 987 988 static int __init count_cpufeatures_subnodes(unsigned long node, 989 const char *uname, 990 void *data) 991 { 992 int *count = data; 993 994 (*count)++; 995 996 return 0; 997 } 998 999 static int __init dt_cpu_ftrs_scan_callback(unsigned long node, const char 1000 *uname, int depth, void *data) 1001 { 1002 const __be32 *prop; 1003 int count, i; 1004 u32 isa; 1005 1006 /* We are scanning "ibm,powerpc-cpu-features" nodes only */ 1007 if (!of_flat_dt_is_compatible(node, "ibm,powerpc-cpu-features")) 1008 return 0; 1009 1010 prop = of_get_flat_dt_prop(node, "isa", NULL); 1011 if (!prop) 1012 /* We checked before, "can't happen" */ 1013 return 0; 1014 1015 isa = be32_to_cpup(prop); 1016 1017 /* Count and allocate space for cpu features */ 1018 of_scan_flat_dt_subnodes(node, count_cpufeatures_subnodes, 1019 &nr_dt_cpu_features); 1020 dt_cpu_features = __va( 1021 memblock_alloc(sizeof(struct dt_cpu_feature)* 1022 nr_dt_cpu_features, PAGE_SIZE)); 1023 1024 cpufeatures_setup_start(isa); 1025 1026 /* Scan nodes into dt_cpu_features and enable those without deps */ 1027 count = 0; 1028 of_scan_flat_dt_subnodes(node, scan_cpufeatures_subnodes, &count); 1029 1030 /* Recursive enable remaining features with dependencies */ 1031 for (i = 0; i < nr_dt_cpu_features; i++) { 1032 struct dt_cpu_feature *f = &dt_cpu_features[i]; 1033 1034 cpufeatures_deps_enable(f); 1035 } 1036 1037 prop = of_get_flat_dt_prop(node, "display-name", NULL); 1038 if (prop && strlen((char *)prop) != 0) { 1039 strlcpy(dt_cpu_name, (char *)prop, sizeof(dt_cpu_name)); 1040 cur_cpu_spec->cpu_name = dt_cpu_name; 1041 } 1042 1043 cpufeatures_setup_finished(); 1044 1045 memblock_free(__pa(dt_cpu_features), 1046 sizeof(struct dt_cpu_feature)*nr_dt_cpu_features); 1047 1048 return 0; 1049 } 1050 1051 void __init dt_cpu_ftrs_scan(void) 1052 { 1053 if (!using_dt_cpu_ftrs) 1054 return; 1055 1056 of_scan_flat_dt(dt_cpu_ftrs_scan_callback, NULL); 1057 } 1058