1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright 2017, Nicholas Piggin, IBM Corporation 4 */ 5 6 #define pr_fmt(fmt) "dt-cpu-ftrs: " fmt 7 8 #include <linux/export.h> 9 #include <linux/init.h> 10 #include <linux/jump_label.h> 11 #include <linux/libfdt.h> 12 #include <linux/memblock.h> 13 #include <linux/printk.h> 14 #include <linux/sched.h> 15 #include <linux/string.h> 16 #include <linux/threads.h> 17 18 #include <asm/cputable.h> 19 #include <asm/dt_cpu_ftrs.h> 20 #include <asm/mmu.h> 21 #include <asm/oprofile_impl.h> 22 #include <asm/prom.h> 23 #include <asm/setup.h> 24 25 26 /* Device-tree visible constants follow */ 27 #define ISA_V2_07B 2070 28 #define ISA_V3_0B 3000 29 30 #define USABLE_PR (1U << 0) 31 #define USABLE_OS (1U << 1) 32 #define USABLE_HV (1U << 2) 33 34 #define HV_SUPPORT_HFSCR (1U << 0) 35 #define OS_SUPPORT_FSCR (1U << 0) 36 37 /* For parsing, we define all bits set as "NONE" case */ 38 #define HV_SUPPORT_NONE 0xffffffffU 39 #define OS_SUPPORT_NONE 0xffffffffU 40 41 struct dt_cpu_feature { 42 const char *name; 43 uint32_t isa; 44 uint32_t usable_privilege; 45 uint32_t hv_support; 46 uint32_t os_support; 47 uint32_t hfscr_bit_nr; 48 uint32_t fscr_bit_nr; 49 uint32_t hwcap_bit_nr; 50 /* fdt parsing */ 51 unsigned long node; 52 int enabled; 53 int disabled; 54 }; 55 56 #define MMU_FTRS_HASH_BASE (MMU_FTRS_POWER8) 57 58 #define COMMON_USER_BASE (PPC_FEATURE_32 | PPC_FEATURE_64 | \ 59 PPC_FEATURE_ARCH_2_06 |\ 60 PPC_FEATURE_ICACHE_SNOOP) 61 #define COMMON_USER2_BASE (PPC_FEATURE2_ARCH_2_07 | \ 62 PPC_FEATURE2_ISEL) 63 /* 64 * Set up the base CPU 65 */ 66 67 extern long __machine_check_early_realmode_p8(struct pt_regs *regs); 68 extern long __machine_check_early_realmode_p9(struct pt_regs *regs); 69 70 static int hv_mode; 71 72 static struct { 73 u64 lpcr; 74 u64 lpcr_clear; 75 u64 hfscr; 76 u64 fscr; 77 } system_registers; 78 79 static void (*init_pmu_registers)(void); 80 81 static void __restore_cpu_cpufeatures(void) 82 { 83 u64 lpcr; 84 85 /* 86 * LPCR is restored by the power on engine already. It can be changed 87 * after early init e.g., by radix enable, and we have no unified API 88 * for saving and restoring such SPRs. 89 * 90 * This ->restore hook should really be removed from idle and register 91 * restore moved directly into the idle restore code, because this code 92 * doesn't know how idle is implemented or what it needs restored here. 93 * 94 * The best we can do to accommodate secondary boot and idle restore 95 * for now is "or" LPCR with existing. 96 */ 97 lpcr = mfspr(SPRN_LPCR); 98 lpcr |= system_registers.lpcr; 99 lpcr &= ~system_registers.lpcr_clear; 100 mtspr(SPRN_LPCR, lpcr); 101 if (hv_mode) { 102 mtspr(SPRN_LPID, 0); 103 mtspr(SPRN_HFSCR, system_registers.hfscr); 104 mtspr(SPRN_PCR, PCR_MASK); 105 } 106 mtspr(SPRN_FSCR, system_registers.fscr); 107 108 if (init_pmu_registers) 109 init_pmu_registers(); 110 } 111 112 static char dt_cpu_name[64]; 113 114 static struct cpu_spec __initdata base_cpu_spec = { 115 .cpu_name = NULL, 116 .cpu_features = CPU_FTRS_DT_CPU_BASE, 117 .cpu_user_features = COMMON_USER_BASE, 118 .cpu_user_features2 = COMMON_USER2_BASE, 119 .mmu_features = 0, 120 .icache_bsize = 32, /* minimum block size, fixed by */ 121 .dcache_bsize = 32, /* cache info init. */ 122 .num_pmcs = 0, 123 .pmc_type = PPC_PMC_DEFAULT, 124 .oprofile_cpu_type = NULL, 125 .oprofile_type = PPC_OPROFILE_INVALID, 126 .cpu_setup = NULL, 127 .cpu_restore = __restore_cpu_cpufeatures, 128 .machine_check_early = NULL, 129 .platform = NULL, 130 }; 131 132 static void __init cpufeatures_setup_cpu(void) 133 { 134 set_cur_cpu_spec(&base_cpu_spec); 135 136 cur_cpu_spec->pvr_mask = -1; 137 cur_cpu_spec->pvr_value = mfspr(SPRN_PVR); 138 139 /* Initialize the base environment -- clear FSCR/HFSCR. */ 140 hv_mode = !!(mfmsr() & MSR_HV); 141 if (hv_mode) { 142 /* CPU_FTR_HVMODE is used early in PACA setup */ 143 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE; 144 mtspr(SPRN_HFSCR, 0); 145 } 146 mtspr(SPRN_FSCR, 0); 147 mtspr(SPRN_PCR, PCR_MASK); 148 149 /* 150 * LPCR does not get cleared, to match behaviour with secondaries 151 * in __restore_cpu_cpufeatures. Once the idle code is fixed, this 152 * could clear LPCR too. 153 */ 154 } 155 156 static int __init feat_try_enable_unknown(struct dt_cpu_feature *f) 157 { 158 if (f->hv_support == HV_SUPPORT_NONE) { 159 } else if (f->hv_support & HV_SUPPORT_HFSCR) { 160 u64 hfscr = mfspr(SPRN_HFSCR); 161 hfscr |= 1UL << f->hfscr_bit_nr; 162 mtspr(SPRN_HFSCR, hfscr); 163 } else { 164 /* Does not have a known recipe */ 165 return 0; 166 } 167 168 if (f->os_support == OS_SUPPORT_NONE) { 169 } else if (f->os_support & OS_SUPPORT_FSCR) { 170 u64 fscr = mfspr(SPRN_FSCR); 171 fscr |= 1UL << f->fscr_bit_nr; 172 mtspr(SPRN_FSCR, fscr); 173 } else { 174 /* Does not have a known recipe */ 175 return 0; 176 } 177 178 if ((f->usable_privilege & USABLE_PR) && (f->hwcap_bit_nr != -1)) { 179 uint32_t word = f->hwcap_bit_nr / 32; 180 uint32_t bit = f->hwcap_bit_nr % 32; 181 182 if (word == 0) 183 cur_cpu_spec->cpu_user_features |= 1U << bit; 184 else if (word == 1) 185 cur_cpu_spec->cpu_user_features2 |= 1U << bit; 186 else 187 pr_err("%s could not advertise to user (no hwcap bits)\n", f->name); 188 } 189 190 return 1; 191 } 192 193 static int __init feat_enable(struct dt_cpu_feature *f) 194 { 195 if (f->hv_support != HV_SUPPORT_NONE) { 196 if (f->hfscr_bit_nr != -1) { 197 u64 hfscr = mfspr(SPRN_HFSCR); 198 hfscr |= 1UL << f->hfscr_bit_nr; 199 mtspr(SPRN_HFSCR, hfscr); 200 } 201 } 202 203 if (f->os_support != OS_SUPPORT_NONE) { 204 if (f->fscr_bit_nr != -1) { 205 u64 fscr = mfspr(SPRN_FSCR); 206 fscr |= 1UL << f->fscr_bit_nr; 207 mtspr(SPRN_FSCR, fscr); 208 } 209 } 210 211 if ((f->usable_privilege & USABLE_PR) && (f->hwcap_bit_nr != -1)) { 212 uint32_t word = f->hwcap_bit_nr / 32; 213 uint32_t bit = f->hwcap_bit_nr % 32; 214 215 if (word == 0) 216 cur_cpu_spec->cpu_user_features |= 1U << bit; 217 else if (word == 1) 218 cur_cpu_spec->cpu_user_features2 |= 1U << bit; 219 else 220 pr_err("CPU feature: %s could not advertise to user (no hwcap bits)\n", f->name); 221 } 222 223 return 1; 224 } 225 226 static int __init feat_disable(struct dt_cpu_feature *f) 227 { 228 return 0; 229 } 230 231 static int __init feat_enable_hv(struct dt_cpu_feature *f) 232 { 233 u64 lpcr; 234 235 if (!hv_mode) { 236 pr_err("CPU feature hypervisor present in device tree but HV mode not enabled in the CPU. Ignoring.\n"); 237 return 0; 238 } 239 240 mtspr(SPRN_LPID, 0); 241 242 lpcr = mfspr(SPRN_LPCR); 243 lpcr &= ~LPCR_LPES0; /* HV external interrupts */ 244 mtspr(SPRN_LPCR, lpcr); 245 246 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE; 247 248 return 1; 249 } 250 251 static int __init feat_enable_le(struct dt_cpu_feature *f) 252 { 253 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_TRUE_LE; 254 return 1; 255 } 256 257 static int __init feat_enable_smt(struct dt_cpu_feature *f) 258 { 259 cur_cpu_spec->cpu_features |= CPU_FTR_SMT; 260 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_SMT; 261 return 1; 262 } 263 264 static int __init feat_enable_idle_nap(struct dt_cpu_feature *f) 265 { 266 u64 lpcr; 267 268 /* Set PECE wakeup modes for ISA 207 */ 269 lpcr = mfspr(SPRN_LPCR); 270 lpcr |= LPCR_PECE0; 271 lpcr |= LPCR_PECE1; 272 lpcr |= LPCR_PECE2; 273 mtspr(SPRN_LPCR, lpcr); 274 275 return 1; 276 } 277 278 static int __init feat_enable_align_dsisr(struct dt_cpu_feature *f) 279 { 280 cur_cpu_spec->cpu_features &= ~CPU_FTR_NODSISRALIGN; 281 282 return 1; 283 } 284 285 static int __init feat_enable_idle_stop(struct dt_cpu_feature *f) 286 { 287 u64 lpcr; 288 289 /* Set PECE wakeup modes for ISAv3.0B */ 290 lpcr = mfspr(SPRN_LPCR); 291 lpcr |= LPCR_PECE0; 292 lpcr |= LPCR_PECE1; 293 lpcr |= LPCR_PECE2; 294 mtspr(SPRN_LPCR, lpcr); 295 296 return 1; 297 } 298 299 static int __init feat_enable_mmu_hash(struct dt_cpu_feature *f) 300 { 301 u64 lpcr; 302 303 lpcr = mfspr(SPRN_LPCR); 304 lpcr &= ~LPCR_ISL; 305 306 /* VRMASD */ 307 lpcr |= LPCR_VPM0; 308 lpcr &= ~LPCR_VPM1; 309 lpcr |= 0x10UL << LPCR_VRMASD_SH; /* L=1 LP=00 */ 310 mtspr(SPRN_LPCR, lpcr); 311 312 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE; 313 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU; 314 315 return 1; 316 } 317 318 static int __init feat_enable_mmu_hash_v3(struct dt_cpu_feature *f) 319 { 320 u64 lpcr; 321 322 system_registers.lpcr_clear |= (LPCR_ISL | LPCR_UPRT | LPCR_HR); 323 lpcr = mfspr(SPRN_LPCR); 324 lpcr &= ~(LPCR_ISL | LPCR_UPRT | LPCR_HR); 325 mtspr(SPRN_LPCR, lpcr); 326 327 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE; 328 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU; 329 330 return 1; 331 } 332 333 334 static int __init feat_enable_mmu_radix(struct dt_cpu_feature *f) 335 { 336 #ifdef CONFIG_PPC_RADIX_MMU 337 cur_cpu_spec->mmu_features |= MMU_FTR_TYPE_RADIX; 338 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE; 339 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU; 340 341 return 1; 342 #endif 343 return 0; 344 } 345 346 static int __init feat_enable_dscr(struct dt_cpu_feature *f) 347 { 348 u64 lpcr; 349 350 feat_enable(f); 351 352 lpcr = mfspr(SPRN_LPCR); 353 lpcr &= ~LPCR_DPFD; 354 lpcr |= (4UL << LPCR_DPFD_SH); 355 mtspr(SPRN_LPCR, lpcr); 356 357 return 1; 358 } 359 360 static void hfscr_pmu_enable(void) 361 { 362 u64 hfscr = mfspr(SPRN_HFSCR); 363 hfscr |= PPC_BIT(60); 364 mtspr(SPRN_HFSCR, hfscr); 365 } 366 367 static void init_pmu_power8(void) 368 { 369 if (hv_mode) { 370 mtspr(SPRN_MMCRC, 0); 371 mtspr(SPRN_MMCRH, 0); 372 } 373 374 mtspr(SPRN_MMCRA, 0); 375 mtspr(SPRN_MMCR0, 0); 376 mtspr(SPRN_MMCR1, 0); 377 mtspr(SPRN_MMCR2, 0); 378 mtspr(SPRN_MMCRS, 0); 379 } 380 381 static int __init feat_enable_mce_power8(struct dt_cpu_feature *f) 382 { 383 cur_cpu_spec->platform = "power8"; 384 cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p8; 385 386 return 1; 387 } 388 389 static int __init feat_enable_pmu_power8(struct dt_cpu_feature *f) 390 { 391 hfscr_pmu_enable(); 392 393 init_pmu_power8(); 394 init_pmu_registers = init_pmu_power8; 395 396 cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA; 397 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT; 398 if (pvr_version_is(PVR_POWER8E)) 399 cur_cpu_spec->cpu_features |= CPU_FTR_PMAO_BUG; 400 401 cur_cpu_spec->num_pmcs = 6; 402 cur_cpu_spec->pmc_type = PPC_PMC_IBM; 403 cur_cpu_spec->oprofile_cpu_type = "ppc64/power8"; 404 405 return 1; 406 } 407 408 static void init_pmu_power9(void) 409 { 410 if (hv_mode) 411 mtspr(SPRN_MMCRC, 0); 412 413 mtspr(SPRN_MMCRA, 0); 414 mtspr(SPRN_MMCR0, 0); 415 mtspr(SPRN_MMCR1, 0); 416 mtspr(SPRN_MMCR2, 0); 417 } 418 419 static int __init feat_enable_mce_power9(struct dt_cpu_feature *f) 420 { 421 cur_cpu_spec->platform = "power9"; 422 cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p9; 423 424 return 1; 425 } 426 427 static int __init feat_enable_pmu_power9(struct dt_cpu_feature *f) 428 { 429 hfscr_pmu_enable(); 430 431 init_pmu_power9(); 432 init_pmu_registers = init_pmu_power9; 433 434 cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA; 435 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT; 436 437 cur_cpu_spec->num_pmcs = 6; 438 cur_cpu_spec->pmc_type = PPC_PMC_IBM; 439 cur_cpu_spec->oprofile_cpu_type = "ppc64/power9"; 440 441 return 1; 442 } 443 444 static int __init feat_enable_tm(struct dt_cpu_feature *f) 445 { 446 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 447 feat_enable(f); 448 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NOSC; 449 return 1; 450 #endif 451 return 0; 452 } 453 454 static int __init feat_enable_fp(struct dt_cpu_feature *f) 455 { 456 feat_enable(f); 457 cur_cpu_spec->cpu_features &= ~CPU_FTR_FPU_UNAVAILABLE; 458 459 return 1; 460 } 461 462 static int __init feat_enable_vector(struct dt_cpu_feature *f) 463 { 464 #ifdef CONFIG_ALTIVEC 465 feat_enable(f); 466 cur_cpu_spec->cpu_features |= CPU_FTR_ALTIVEC; 467 cur_cpu_spec->cpu_features |= CPU_FTR_VMX_COPY; 468 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_ALTIVEC; 469 470 return 1; 471 #endif 472 return 0; 473 } 474 475 static int __init feat_enable_vsx(struct dt_cpu_feature *f) 476 { 477 #ifdef CONFIG_VSX 478 feat_enable(f); 479 cur_cpu_spec->cpu_features |= CPU_FTR_VSX; 480 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_VSX; 481 482 return 1; 483 #endif 484 return 0; 485 } 486 487 static int __init feat_enable_purr(struct dt_cpu_feature *f) 488 { 489 cur_cpu_spec->cpu_features |= CPU_FTR_PURR | CPU_FTR_SPURR; 490 491 return 1; 492 } 493 494 static int __init feat_enable_ebb(struct dt_cpu_feature *f) 495 { 496 /* 497 * PPC_FEATURE2_EBB is enabled in PMU init code because it has 498 * historically been related to the PMU facility. This may have 499 * to be decoupled if EBB becomes more generic. For now, follow 500 * existing convention. 501 */ 502 f->hwcap_bit_nr = -1; 503 feat_enable(f); 504 505 return 1; 506 } 507 508 static int __init feat_enable_dbell(struct dt_cpu_feature *f) 509 { 510 u64 lpcr; 511 512 /* P9 has an HFSCR for privileged state */ 513 feat_enable(f); 514 515 cur_cpu_spec->cpu_features |= CPU_FTR_DBELL; 516 517 lpcr = mfspr(SPRN_LPCR); 518 lpcr |= LPCR_PECEDH; /* hyp doorbell wakeup */ 519 mtspr(SPRN_LPCR, lpcr); 520 521 return 1; 522 } 523 524 static int __init feat_enable_hvi(struct dt_cpu_feature *f) 525 { 526 u64 lpcr; 527 528 /* 529 * POWER9 XIVE interrupts including in OPAL XICS compatibility 530 * are always delivered as hypervisor virtualization interrupts (HVI) 531 * rather than EE. 532 * 533 * However LPES0 is not set here, in the chance that an EE does get 534 * delivered to the host somehow, the EE handler would not expect it 535 * to be delivered in LPES0 mode (e.g., using SRR[01]). This could 536 * happen if there is a bug in interrupt controller code, or IC is 537 * misconfigured in systemsim. 538 */ 539 540 lpcr = mfspr(SPRN_LPCR); 541 lpcr |= LPCR_HVICE; /* enable hvi interrupts */ 542 lpcr |= LPCR_HEIC; /* disable ee interrupts when MSR_HV */ 543 lpcr |= LPCR_PECE_HVEE; /* hvi can wake from stop */ 544 mtspr(SPRN_LPCR, lpcr); 545 546 return 1; 547 } 548 549 static int __init feat_enable_large_ci(struct dt_cpu_feature *f) 550 { 551 cur_cpu_spec->mmu_features |= MMU_FTR_CI_LARGE_PAGE; 552 553 return 1; 554 } 555 556 struct dt_cpu_feature_match { 557 const char *name; 558 int (*enable)(struct dt_cpu_feature *f); 559 u64 cpu_ftr_bit_mask; 560 }; 561 562 static struct dt_cpu_feature_match __initdata 563 dt_cpu_feature_match_table[] = { 564 {"hypervisor", feat_enable_hv, 0}, 565 {"big-endian", feat_enable, 0}, 566 {"little-endian", feat_enable_le, CPU_FTR_REAL_LE}, 567 {"smt", feat_enable_smt, 0}, 568 {"interrupt-facilities", feat_enable, 0}, 569 {"timer-facilities", feat_enable, 0}, 570 {"timer-facilities-v3", feat_enable, 0}, 571 {"debug-facilities", feat_enable, 0}, 572 {"come-from-address-register", feat_enable, CPU_FTR_CFAR}, 573 {"branch-tracing", feat_enable, 0}, 574 {"floating-point", feat_enable_fp, 0}, 575 {"vector", feat_enable_vector, 0}, 576 {"vector-scalar", feat_enable_vsx, 0}, 577 {"vector-scalar-v3", feat_enable, 0}, 578 {"decimal-floating-point", feat_enable, 0}, 579 {"decimal-integer", feat_enable, 0}, 580 {"quadword-load-store", feat_enable, 0}, 581 {"vector-crypto", feat_enable, 0}, 582 {"mmu-hash", feat_enable_mmu_hash, 0}, 583 {"mmu-radix", feat_enable_mmu_radix, 0}, 584 {"mmu-hash-v3", feat_enable_mmu_hash_v3, 0}, 585 {"virtual-page-class-key-protection", feat_enable, 0}, 586 {"transactional-memory", feat_enable_tm, CPU_FTR_TM}, 587 {"transactional-memory-v3", feat_enable_tm, 0}, 588 {"tm-suspend-hypervisor-assist", feat_enable, CPU_FTR_P9_TM_HV_ASSIST}, 589 {"tm-suspend-xer-so-bug", feat_enable, CPU_FTR_P9_TM_XER_SO_BUG}, 590 {"idle-nap", feat_enable_idle_nap, 0}, 591 {"alignment-interrupt-dsisr", feat_enable_align_dsisr, 0}, 592 {"idle-stop", feat_enable_idle_stop, 0}, 593 {"machine-check-power8", feat_enable_mce_power8, 0}, 594 {"performance-monitor-power8", feat_enable_pmu_power8, 0}, 595 {"data-stream-control-register", feat_enable_dscr, CPU_FTR_DSCR}, 596 {"event-based-branch", feat_enable_ebb, 0}, 597 {"target-address-register", feat_enable, 0}, 598 {"branch-history-rolling-buffer", feat_enable, 0}, 599 {"control-register", feat_enable, CPU_FTR_CTRL}, 600 {"processor-control-facility", feat_enable_dbell, CPU_FTR_DBELL}, 601 {"processor-control-facility-v3", feat_enable_dbell, CPU_FTR_DBELL}, 602 {"processor-utilization-of-resources-register", feat_enable_purr, 0}, 603 {"no-execute", feat_enable, 0}, 604 {"strong-access-ordering", feat_enable, CPU_FTR_SAO}, 605 {"cache-inhibited-large-page", feat_enable_large_ci, 0}, 606 {"coprocessor-icswx", feat_enable, 0}, 607 {"hypervisor-virtualization-interrupt", feat_enable_hvi, 0}, 608 {"program-priority-register", feat_enable, CPU_FTR_HAS_PPR}, 609 {"wait", feat_enable, 0}, 610 {"atomic-memory-operations", feat_enable, 0}, 611 {"branch-v3", feat_enable, 0}, 612 {"copy-paste", feat_enable, 0}, 613 {"decimal-floating-point-v3", feat_enable, 0}, 614 {"decimal-integer-v3", feat_enable, 0}, 615 {"fixed-point-v3", feat_enable, 0}, 616 {"floating-point-v3", feat_enable, 0}, 617 {"group-start-register", feat_enable, 0}, 618 {"pc-relative-addressing", feat_enable, 0}, 619 {"machine-check-power9", feat_enable_mce_power9, 0}, 620 {"performance-monitor-power9", feat_enable_pmu_power9, 0}, 621 {"event-based-branch-v3", feat_enable, 0}, 622 {"random-number-generator", feat_enable, 0}, 623 {"system-call-vectored", feat_disable, 0}, 624 {"trace-interrupt-v3", feat_enable, 0}, 625 {"vector-v3", feat_enable, 0}, 626 {"vector-binary128", feat_enable, 0}, 627 {"vector-binary16", feat_enable, 0}, 628 {"wait-v3", feat_enable, 0}, 629 }; 630 631 static bool __initdata using_dt_cpu_ftrs; 632 static bool __initdata enable_unknown = true; 633 634 static int __init dt_cpu_ftrs_parse(char *str) 635 { 636 if (!str) 637 return 0; 638 639 if (!strcmp(str, "off")) 640 using_dt_cpu_ftrs = false; 641 else if (!strcmp(str, "known")) 642 enable_unknown = false; 643 else 644 return 1; 645 646 return 0; 647 } 648 early_param("dt_cpu_ftrs", dt_cpu_ftrs_parse); 649 650 static void __init cpufeatures_setup_start(u32 isa) 651 { 652 pr_info("setup for ISA %d\n", isa); 653 654 if (isa >= 3000) { 655 cur_cpu_spec->cpu_features |= CPU_FTR_ARCH_300; 656 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_ARCH_3_00; 657 } 658 } 659 660 static bool __init cpufeatures_process_feature(struct dt_cpu_feature *f) 661 { 662 const struct dt_cpu_feature_match *m; 663 bool known = false; 664 int i; 665 666 for (i = 0; i < ARRAY_SIZE(dt_cpu_feature_match_table); i++) { 667 m = &dt_cpu_feature_match_table[i]; 668 if (!strcmp(f->name, m->name)) { 669 known = true; 670 if (m->enable(f)) { 671 cur_cpu_spec->cpu_features |= m->cpu_ftr_bit_mask; 672 break; 673 } 674 675 pr_info("not enabling: %s (disabled or unsupported by kernel)\n", 676 f->name); 677 return false; 678 } 679 } 680 681 if (!known && (!enable_unknown || !feat_try_enable_unknown(f))) { 682 pr_info("not enabling: %s (unknown and unsupported by kernel)\n", 683 f->name); 684 return false; 685 } 686 687 if (known) 688 pr_debug("enabling: %s\n", f->name); 689 else 690 pr_debug("enabling: %s (unknown)\n", f->name); 691 692 return true; 693 } 694 695 /* 696 * Handle POWER9 broadcast tlbie invalidation issue using 697 * cpu feature flag. 698 */ 699 static __init void update_tlbie_feature_flag(unsigned long pvr) 700 { 701 if (PVR_VER(pvr) == PVR_POWER9) { 702 /* 703 * Set the tlbie feature flag for anything below 704 * Nimbus DD 2.3 and Cumulus DD 1.3 705 */ 706 if ((pvr & 0xe000) == 0) { 707 /* Nimbus */ 708 if ((pvr & 0xfff) < 0x203) 709 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_STQ_BUG; 710 } else if ((pvr & 0xc000) == 0) { 711 /* Cumulus */ 712 if ((pvr & 0xfff) < 0x103) 713 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_STQ_BUG; 714 } else { 715 WARN_ONCE(1, "Unknown PVR"); 716 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_STQ_BUG; 717 } 718 719 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_ERAT_BUG; 720 } 721 } 722 723 static __init void cpufeatures_cpu_quirks(void) 724 { 725 unsigned long version = mfspr(SPRN_PVR); 726 727 /* 728 * Not all quirks can be derived from the cpufeatures device tree. 729 */ 730 if ((version & 0xffffefff) == 0x004e0200) 731 ; /* DD2.0 has no feature flag */ 732 else if ((version & 0xffffefff) == 0x004e0201) 733 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1; 734 else if ((version & 0xffffefff) == 0x004e0202) { 735 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TM_HV_ASSIST; 736 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TM_XER_SO_BUG; 737 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1; 738 } else if ((version & 0xffff0000) == 0x004e0000) 739 /* DD2.1 and up have DD2_1 */ 740 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1; 741 742 if ((version & 0xffff0000) == 0x004e0000) { 743 cur_cpu_spec->cpu_features &= ~(CPU_FTR_DAWR); 744 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TIDR; 745 } 746 747 update_tlbie_feature_flag(version); 748 /* 749 * PKEY was not in the initial base or feature node 750 * specification, but it should become optional in the next 751 * cpu feature version sequence. 752 */ 753 cur_cpu_spec->cpu_features |= CPU_FTR_PKEY; 754 } 755 756 static void __init cpufeatures_setup_finished(void) 757 { 758 cpufeatures_cpu_quirks(); 759 760 if (hv_mode && !(cur_cpu_spec->cpu_features & CPU_FTR_HVMODE)) { 761 pr_err("hypervisor not present in device tree but HV mode is enabled in the CPU. Enabling.\n"); 762 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE; 763 } 764 765 /* Make sure powerpc_base_platform is non-NULL */ 766 powerpc_base_platform = cur_cpu_spec->platform; 767 768 system_registers.lpcr = mfspr(SPRN_LPCR); 769 system_registers.hfscr = mfspr(SPRN_HFSCR); 770 system_registers.fscr = mfspr(SPRN_FSCR); 771 772 pr_info("final cpu/mmu features = 0x%016lx 0x%08x\n", 773 cur_cpu_spec->cpu_features, cur_cpu_spec->mmu_features); 774 } 775 776 static int __init disabled_on_cmdline(void) 777 { 778 unsigned long root, chosen; 779 const char *p; 780 781 root = of_get_flat_dt_root(); 782 chosen = of_get_flat_dt_subnode_by_name(root, "chosen"); 783 if (chosen == -FDT_ERR_NOTFOUND) 784 return false; 785 786 p = of_get_flat_dt_prop(chosen, "bootargs", NULL); 787 if (!p) 788 return false; 789 790 if (strstr(p, "dt_cpu_ftrs=off")) 791 return true; 792 793 return false; 794 } 795 796 static int __init fdt_find_cpu_features(unsigned long node, const char *uname, 797 int depth, void *data) 798 { 799 if (of_flat_dt_is_compatible(node, "ibm,powerpc-cpu-features") 800 && of_get_flat_dt_prop(node, "isa", NULL)) 801 return 1; 802 803 return 0; 804 } 805 806 bool __init dt_cpu_ftrs_in_use(void) 807 { 808 return using_dt_cpu_ftrs; 809 } 810 811 bool __init dt_cpu_ftrs_init(void *fdt) 812 { 813 using_dt_cpu_ftrs = false; 814 815 /* Setup and verify the FDT, if it fails we just bail */ 816 if (!early_init_dt_verify(fdt)) 817 return false; 818 819 if (!of_scan_flat_dt(fdt_find_cpu_features, NULL)) 820 return false; 821 822 if (disabled_on_cmdline()) 823 return false; 824 825 cpufeatures_setup_cpu(); 826 827 using_dt_cpu_ftrs = true; 828 return true; 829 } 830 831 static int nr_dt_cpu_features; 832 static struct dt_cpu_feature *dt_cpu_features; 833 834 static int __init process_cpufeatures_node(unsigned long node, 835 const char *uname, int i) 836 { 837 const __be32 *prop; 838 struct dt_cpu_feature *f; 839 int len; 840 841 f = &dt_cpu_features[i]; 842 843 f->node = node; 844 845 f->name = uname; 846 847 prop = of_get_flat_dt_prop(node, "isa", &len); 848 if (!prop) { 849 pr_warn("%s: missing isa property\n", uname); 850 return 0; 851 } 852 f->isa = be32_to_cpup(prop); 853 854 prop = of_get_flat_dt_prop(node, "usable-privilege", &len); 855 if (!prop) { 856 pr_warn("%s: missing usable-privilege property", uname); 857 return 0; 858 } 859 f->usable_privilege = be32_to_cpup(prop); 860 861 prop = of_get_flat_dt_prop(node, "hv-support", &len); 862 if (prop) 863 f->hv_support = be32_to_cpup(prop); 864 else 865 f->hv_support = HV_SUPPORT_NONE; 866 867 prop = of_get_flat_dt_prop(node, "os-support", &len); 868 if (prop) 869 f->os_support = be32_to_cpup(prop); 870 else 871 f->os_support = OS_SUPPORT_NONE; 872 873 prop = of_get_flat_dt_prop(node, "hfscr-bit-nr", &len); 874 if (prop) 875 f->hfscr_bit_nr = be32_to_cpup(prop); 876 else 877 f->hfscr_bit_nr = -1; 878 prop = of_get_flat_dt_prop(node, "fscr-bit-nr", &len); 879 if (prop) 880 f->fscr_bit_nr = be32_to_cpup(prop); 881 else 882 f->fscr_bit_nr = -1; 883 prop = of_get_flat_dt_prop(node, "hwcap-bit-nr", &len); 884 if (prop) 885 f->hwcap_bit_nr = be32_to_cpup(prop); 886 else 887 f->hwcap_bit_nr = -1; 888 889 if (f->usable_privilege & USABLE_HV) { 890 if (!(mfmsr() & MSR_HV)) { 891 pr_warn("%s: HV feature passed to guest\n", uname); 892 return 0; 893 } 894 895 if (f->hv_support == HV_SUPPORT_NONE && f->hfscr_bit_nr != -1) { 896 pr_warn("%s: unwanted hfscr_bit_nr\n", uname); 897 return 0; 898 } 899 900 if (f->hv_support == HV_SUPPORT_HFSCR) { 901 if (f->hfscr_bit_nr == -1) { 902 pr_warn("%s: missing hfscr_bit_nr\n", uname); 903 return 0; 904 } 905 } 906 } else { 907 if (f->hv_support != HV_SUPPORT_NONE || f->hfscr_bit_nr != -1) { 908 pr_warn("%s: unwanted hv_support/hfscr_bit_nr\n", uname); 909 return 0; 910 } 911 } 912 913 if (f->usable_privilege & USABLE_OS) { 914 if (f->os_support == OS_SUPPORT_NONE && f->fscr_bit_nr != -1) { 915 pr_warn("%s: unwanted fscr_bit_nr\n", uname); 916 return 0; 917 } 918 919 if (f->os_support == OS_SUPPORT_FSCR) { 920 if (f->fscr_bit_nr == -1) { 921 pr_warn("%s: missing fscr_bit_nr\n", uname); 922 return 0; 923 } 924 } 925 } else { 926 if (f->os_support != OS_SUPPORT_NONE || f->fscr_bit_nr != -1) { 927 pr_warn("%s: unwanted os_support/fscr_bit_nr\n", uname); 928 return 0; 929 } 930 } 931 932 if (!(f->usable_privilege & USABLE_PR)) { 933 if (f->hwcap_bit_nr != -1) { 934 pr_warn("%s: unwanted hwcap_bit_nr\n", uname); 935 return 0; 936 } 937 } 938 939 /* Do all the independent features in the first pass */ 940 if (!of_get_flat_dt_prop(node, "dependencies", &len)) { 941 if (cpufeatures_process_feature(f)) 942 f->enabled = 1; 943 else 944 f->disabled = 1; 945 } 946 947 return 0; 948 } 949 950 static void __init cpufeatures_deps_enable(struct dt_cpu_feature *f) 951 { 952 const __be32 *prop; 953 int len; 954 int nr_deps; 955 int i; 956 957 if (f->enabled || f->disabled) 958 return; 959 960 prop = of_get_flat_dt_prop(f->node, "dependencies", &len); 961 if (!prop) { 962 pr_warn("%s: missing dependencies property", f->name); 963 return; 964 } 965 966 nr_deps = len / sizeof(int); 967 968 for (i = 0; i < nr_deps; i++) { 969 unsigned long phandle = be32_to_cpu(prop[i]); 970 int j; 971 972 for (j = 0; j < nr_dt_cpu_features; j++) { 973 struct dt_cpu_feature *d = &dt_cpu_features[j]; 974 975 if (of_get_flat_dt_phandle(d->node) == phandle) { 976 cpufeatures_deps_enable(d); 977 if (d->disabled) { 978 f->disabled = 1; 979 return; 980 } 981 } 982 } 983 } 984 985 if (cpufeatures_process_feature(f)) 986 f->enabled = 1; 987 else 988 f->disabled = 1; 989 } 990 991 static int __init scan_cpufeatures_subnodes(unsigned long node, 992 const char *uname, 993 void *data) 994 { 995 int *count = data; 996 997 process_cpufeatures_node(node, uname, *count); 998 999 (*count)++; 1000 1001 return 0; 1002 } 1003 1004 static int __init count_cpufeatures_subnodes(unsigned long node, 1005 const char *uname, 1006 void *data) 1007 { 1008 int *count = data; 1009 1010 (*count)++; 1011 1012 return 0; 1013 } 1014 1015 static int __init dt_cpu_ftrs_scan_callback(unsigned long node, const char 1016 *uname, int depth, void *data) 1017 { 1018 const __be32 *prop; 1019 int count, i; 1020 u32 isa; 1021 1022 /* We are scanning "ibm,powerpc-cpu-features" nodes only */ 1023 if (!of_flat_dt_is_compatible(node, "ibm,powerpc-cpu-features")) 1024 return 0; 1025 1026 prop = of_get_flat_dt_prop(node, "isa", NULL); 1027 if (!prop) 1028 /* We checked before, "can't happen" */ 1029 return 0; 1030 1031 isa = be32_to_cpup(prop); 1032 1033 /* Count and allocate space for cpu features */ 1034 of_scan_flat_dt_subnodes(node, count_cpufeatures_subnodes, 1035 &nr_dt_cpu_features); 1036 dt_cpu_features = memblock_alloc(sizeof(struct dt_cpu_feature) * nr_dt_cpu_features, PAGE_SIZE); 1037 if (!dt_cpu_features) 1038 panic("%s: Failed to allocate %zu bytes align=0x%lx\n", 1039 __func__, 1040 sizeof(struct dt_cpu_feature) * nr_dt_cpu_features, 1041 PAGE_SIZE); 1042 1043 cpufeatures_setup_start(isa); 1044 1045 /* Scan nodes into dt_cpu_features and enable those without deps */ 1046 count = 0; 1047 of_scan_flat_dt_subnodes(node, scan_cpufeatures_subnodes, &count); 1048 1049 /* Recursive enable remaining features with dependencies */ 1050 for (i = 0; i < nr_dt_cpu_features; i++) { 1051 struct dt_cpu_feature *f = &dt_cpu_features[i]; 1052 1053 cpufeatures_deps_enable(f); 1054 } 1055 1056 prop = of_get_flat_dt_prop(node, "display-name", NULL); 1057 if (prop && strlen((char *)prop) != 0) { 1058 strlcpy(dt_cpu_name, (char *)prop, sizeof(dt_cpu_name)); 1059 cur_cpu_spec->cpu_name = dt_cpu_name; 1060 } 1061 1062 cpufeatures_setup_finished(); 1063 1064 memblock_free(__pa(dt_cpu_features), 1065 sizeof(struct dt_cpu_feature)*nr_dt_cpu_features); 1066 1067 return 0; 1068 } 1069 1070 void __init dt_cpu_ftrs_scan(void) 1071 { 1072 if (!using_dt_cpu_ftrs) 1073 return; 1074 1075 of_scan_flat_dt(dt_cpu_ftrs_scan_callback, NULL); 1076 } 1077