1 /* 2 * Copyright 2017, Nicholas Piggin, IBM Corporation 3 * Licensed under GPLv2. 4 */ 5 6 #define pr_fmt(fmt) "dt-cpu-ftrs: " fmt 7 8 #include <linux/export.h> 9 #include <linux/init.h> 10 #include <linux/jump_label.h> 11 #include <linux/libfdt.h> 12 #include <linux/memblock.h> 13 #include <linux/printk.h> 14 #include <linux/sched.h> 15 #include <linux/string.h> 16 #include <linux/threads.h> 17 18 #include <asm/cputable.h> 19 #include <asm/dt_cpu_ftrs.h> 20 #include <asm/mmu.h> 21 #include <asm/oprofile_impl.h> 22 #include <asm/prom.h> 23 #include <asm/setup.h> 24 25 26 /* Device-tree visible constants follow */ 27 #define ISA_V2_07B 2070 28 #define ISA_V3_0B 3000 29 30 #define USABLE_PR (1U << 0) 31 #define USABLE_OS (1U << 1) 32 #define USABLE_HV (1U << 2) 33 34 #define HV_SUPPORT_HFSCR (1U << 0) 35 #define OS_SUPPORT_FSCR (1U << 0) 36 37 /* For parsing, we define all bits set as "NONE" case */ 38 #define HV_SUPPORT_NONE 0xffffffffU 39 #define OS_SUPPORT_NONE 0xffffffffU 40 41 struct dt_cpu_feature { 42 const char *name; 43 uint32_t isa; 44 uint32_t usable_privilege; 45 uint32_t hv_support; 46 uint32_t os_support; 47 uint32_t hfscr_bit_nr; 48 uint32_t fscr_bit_nr; 49 uint32_t hwcap_bit_nr; 50 /* fdt parsing */ 51 unsigned long node; 52 int enabled; 53 int disabled; 54 }; 55 56 #define CPU_FTRS_BASE \ 57 (CPU_FTR_LWSYNC | \ 58 CPU_FTR_FPU_UNAVAILABLE |\ 59 CPU_FTR_NODSISRALIGN |\ 60 CPU_FTR_NOEXECUTE |\ 61 CPU_FTR_COHERENT_ICACHE | \ 62 CPU_FTR_STCX_CHECKS_ADDRESS |\ 63 CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 64 CPU_FTR_DAWR | \ 65 CPU_FTR_ARCH_206 |\ 66 CPU_FTR_ARCH_207S) 67 68 #define MMU_FTRS_HASH_BASE (MMU_FTRS_POWER8) 69 70 #define COMMON_USER_BASE (PPC_FEATURE_32 | PPC_FEATURE_64 | \ 71 PPC_FEATURE_ARCH_2_06 |\ 72 PPC_FEATURE_ICACHE_SNOOP) 73 #define COMMON_USER2_BASE (PPC_FEATURE2_ARCH_2_07 | \ 74 PPC_FEATURE2_ISEL) 75 /* 76 * Set up the base CPU 77 */ 78 79 extern long __machine_check_early_realmode_p8(struct pt_regs *regs); 80 extern long __machine_check_early_realmode_p9(struct pt_regs *regs); 81 82 static int hv_mode; 83 84 static struct { 85 u64 lpcr; 86 u64 lpcr_clear; 87 u64 hfscr; 88 u64 fscr; 89 } system_registers; 90 91 static void (*init_pmu_registers)(void); 92 93 static void __restore_cpu_cpufeatures(void) 94 { 95 u64 lpcr; 96 97 /* 98 * LPCR is restored by the power on engine already. It can be changed 99 * after early init e.g., by radix enable, and we have no unified API 100 * for saving and restoring such SPRs. 101 * 102 * This ->restore hook should really be removed from idle and register 103 * restore moved directly into the idle restore code, because this code 104 * doesn't know how idle is implemented or what it needs restored here. 105 * 106 * The best we can do to accommodate secondary boot and idle restore 107 * for now is "or" LPCR with existing. 108 */ 109 lpcr = mfspr(SPRN_LPCR); 110 lpcr |= system_registers.lpcr; 111 lpcr &= ~system_registers.lpcr_clear; 112 mtspr(SPRN_LPCR, lpcr); 113 if (hv_mode) { 114 mtspr(SPRN_LPID, 0); 115 mtspr(SPRN_HFSCR, system_registers.hfscr); 116 } 117 mtspr(SPRN_FSCR, system_registers.fscr); 118 119 if (init_pmu_registers) 120 init_pmu_registers(); 121 } 122 123 static char dt_cpu_name[64]; 124 125 static struct cpu_spec __initdata base_cpu_spec = { 126 .cpu_name = NULL, 127 .cpu_features = CPU_FTRS_BASE, 128 .cpu_user_features = COMMON_USER_BASE, 129 .cpu_user_features2 = COMMON_USER2_BASE, 130 .mmu_features = 0, 131 .icache_bsize = 32, /* minimum block size, fixed by */ 132 .dcache_bsize = 32, /* cache info init. */ 133 .num_pmcs = 0, 134 .pmc_type = PPC_PMC_DEFAULT, 135 .oprofile_cpu_type = NULL, 136 .oprofile_type = PPC_OPROFILE_INVALID, 137 .cpu_setup = NULL, 138 .cpu_restore = __restore_cpu_cpufeatures, 139 .machine_check_early = NULL, 140 .platform = NULL, 141 }; 142 143 static void __init cpufeatures_setup_cpu(void) 144 { 145 set_cur_cpu_spec(&base_cpu_spec); 146 147 cur_cpu_spec->pvr_mask = -1; 148 cur_cpu_spec->pvr_value = mfspr(SPRN_PVR); 149 150 /* Initialize the base environment -- clear FSCR/HFSCR. */ 151 hv_mode = !!(mfmsr() & MSR_HV); 152 if (hv_mode) { 153 /* CPU_FTR_HVMODE is used early in PACA setup */ 154 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE; 155 mtspr(SPRN_HFSCR, 0); 156 } 157 mtspr(SPRN_FSCR, 0); 158 159 /* 160 * LPCR does not get cleared, to match behaviour with secondaries 161 * in __restore_cpu_cpufeatures. Once the idle code is fixed, this 162 * could clear LPCR too. 163 */ 164 } 165 166 static int __init feat_try_enable_unknown(struct dt_cpu_feature *f) 167 { 168 if (f->hv_support == HV_SUPPORT_NONE) { 169 } else if (f->hv_support & HV_SUPPORT_HFSCR) { 170 u64 hfscr = mfspr(SPRN_HFSCR); 171 hfscr |= 1UL << f->hfscr_bit_nr; 172 mtspr(SPRN_HFSCR, hfscr); 173 } else { 174 /* Does not have a known recipe */ 175 return 0; 176 } 177 178 if (f->os_support == OS_SUPPORT_NONE) { 179 } else if (f->os_support & OS_SUPPORT_FSCR) { 180 u64 fscr = mfspr(SPRN_FSCR); 181 fscr |= 1UL << f->fscr_bit_nr; 182 mtspr(SPRN_FSCR, fscr); 183 } else { 184 /* Does not have a known recipe */ 185 return 0; 186 } 187 188 if ((f->usable_privilege & USABLE_PR) && (f->hwcap_bit_nr != -1)) { 189 uint32_t word = f->hwcap_bit_nr / 32; 190 uint32_t bit = f->hwcap_bit_nr % 32; 191 192 if (word == 0) 193 cur_cpu_spec->cpu_user_features |= 1U << bit; 194 else if (word == 1) 195 cur_cpu_spec->cpu_user_features2 |= 1U << bit; 196 else 197 pr_err("%s could not advertise to user (no hwcap bits)\n", f->name); 198 } 199 200 return 1; 201 } 202 203 static int __init feat_enable(struct dt_cpu_feature *f) 204 { 205 if (f->hv_support != HV_SUPPORT_NONE) { 206 if (f->hfscr_bit_nr != -1) { 207 u64 hfscr = mfspr(SPRN_HFSCR); 208 hfscr |= 1UL << f->hfscr_bit_nr; 209 mtspr(SPRN_HFSCR, hfscr); 210 } 211 } 212 213 if (f->os_support != OS_SUPPORT_NONE) { 214 if (f->fscr_bit_nr != -1) { 215 u64 fscr = mfspr(SPRN_FSCR); 216 fscr |= 1UL << f->fscr_bit_nr; 217 mtspr(SPRN_FSCR, fscr); 218 } 219 } 220 221 if ((f->usable_privilege & USABLE_PR) && (f->hwcap_bit_nr != -1)) { 222 uint32_t word = f->hwcap_bit_nr / 32; 223 uint32_t bit = f->hwcap_bit_nr % 32; 224 225 if (word == 0) 226 cur_cpu_spec->cpu_user_features |= 1U << bit; 227 else if (word == 1) 228 cur_cpu_spec->cpu_user_features2 |= 1U << bit; 229 else 230 pr_err("CPU feature: %s could not advertise to user (no hwcap bits)\n", f->name); 231 } 232 233 return 1; 234 } 235 236 static int __init feat_disable(struct dt_cpu_feature *f) 237 { 238 return 0; 239 } 240 241 static int __init feat_enable_hv(struct dt_cpu_feature *f) 242 { 243 u64 lpcr; 244 245 if (!hv_mode) { 246 pr_err("CPU feature hypervisor present in device tree but HV mode not enabled in the CPU. Ignoring.\n"); 247 return 0; 248 } 249 250 mtspr(SPRN_LPID, 0); 251 252 lpcr = mfspr(SPRN_LPCR); 253 lpcr &= ~LPCR_LPES0; /* HV external interrupts */ 254 mtspr(SPRN_LPCR, lpcr); 255 256 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE; 257 258 return 1; 259 } 260 261 static int __init feat_enable_le(struct dt_cpu_feature *f) 262 { 263 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_TRUE_LE; 264 return 1; 265 } 266 267 static int __init feat_enable_smt(struct dt_cpu_feature *f) 268 { 269 cur_cpu_spec->cpu_features |= CPU_FTR_SMT; 270 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_SMT; 271 return 1; 272 } 273 274 static int __init feat_enable_idle_nap(struct dt_cpu_feature *f) 275 { 276 u64 lpcr; 277 278 /* Set PECE wakeup modes for ISA 207 */ 279 lpcr = mfspr(SPRN_LPCR); 280 lpcr |= LPCR_PECE0; 281 lpcr |= LPCR_PECE1; 282 lpcr |= LPCR_PECE2; 283 mtspr(SPRN_LPCR, lpcr); 284 285 return 1; 286 } 287 288 static int __init feat_enable_align_dsisr(struct dt_cpu_feature *f) 289 { 290 cur_cpu_spec->cpu_features &= ~CPU_FTR_NODSISRALIGN; 291 292 return 1; 293 } 294 295 static int __init feat_enable_idle_stop(struct dt_cpu_feature *f) 296 { 297 u64 lpcr; 298 299 /* Set PECE wakeup modes for ISAv3.0B */ 300 lpcr = mfspr(SPRN_LPCR); 301 lpcr |= LPCR_PECE0; 302 lpcr |= LPCR_PECE1; 303 lpcr |= LPCR_PECE2; 304 mtspr(SPRN_LPCR, lpcr); 305 306 return 1; 307 } 308 309 static int __init feat_enable_mmu_hash(struct dt_cpu_feature *f) 310 { 311 u64 lpcr; 312 313 lpcr = mfspr(SPRN_LPCR); 314 lpcr &= ~LPCR_ISL; 315 316 /* VRMASD */ 317 lpcr |= LPCR_VPM0; 318 lpcr &= ~LPCR_VPM1; 319 lpcr |= 0x10UL << LPCR_VRMASD_SH; /* L=1 LP=00 */ 320 mtspr(SPRN_LPCR, lpcr); 321 322 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE; 323 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU; 324 325 return 1; 326 } 327 328 static int __init feat_enable_mmu_hash_v3(struct dt_cpu_feature *f) 329 { 330 u64 lpcr; 331 332 system_registers.lpcr_clear |= (LPCR_ISL | LPCR_UPRT | LPCR_HR); 333 lpcr = mfspr(SPRN_LPCR); 334 lpcr &= ~(LPCR_ISL | LPCR_UPRT | LPCR_HR); 335 mtspr(SPRN_LPCR, lpcr); 336 337 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE; 338 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU; 339 340 return 1; 341 } 342 343 344 static int __init feat_enable_mmu_radix(struct dt_cpu_feature *f) 345 { 346 #ifdef CONFIG_PPC_RADIX_MMU 347 cur_cpu_spec->mmu_features |= MMU_FTR_TYPE_RADIX; 348 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE; 349 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU; 350 351 return 1; 352 #endif 353 return 0; 354 } 355 356 static int __init feat_enable_dscr(struct dt_cpu_feature *f) 357 { 358 u64 lpcr; 359 360 feat_enable(f); 361 362 lpcr = mfspr(SPRN_LPCR); 363 lpcr &= ~LPCR_DPFD; 364 lpcr |= (4UL << LPCR_DPFD_SH); 365 mtspr(SPRN_LPCR, lpcr); 366 367 return 1; 368 } 369 370 static void hfscr_pmu_enable(void) 371 { 372 u64 hfscr = mfspr(SPRN_HFSCR); 373 hfscr |= PPC_BIT(60); 374 mtspr(SPRN_HFSCR, hfscr); 375 } 376 377 static void init_pmu_power8(void) 378 { 379 if (hv_mode) { 380 mtspr(SPRN_MMCRC, 0); 381 mtspr(SPRN_MMCRH, 0); 382 } 383 384 mtspr(SPRN_MMCRA, 0); 385 mtspr(SPRN_MMCR0, 0); 386 mtspr(SPRN_MMCR1, 0); 387 mtspr(SPRN_MMCR2, 0); 388 mtspr(SPRN_MMCRS, 0); 389 } 390 391 static int __init feat_enable_mce_power8(struct dt_cpu_feature *f) 392 { 393 cur_cpu_spec->platform = "power8"; 394 cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p8; 395 396 return 1; 397 } 398 399 static int __init feat_enable_pmu_power8(struct dt_cpu_feature *f) 400 { 401 hfscr_pmu_enable(); 402 403 init_pmu_power8(); 404 init_pmu_registers = init_pmu_power8; 405 406 cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA; 407 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT; 408 if (pvr_version_is(PVR_POWER8E)) 409 cur_cpu_spec->cpu_features |= CPU_FTR_PMAO_BUG; 410 411 cur_cpu_spec->num_pmcs = 6; 412 cur_cpu_spec->pmc_type = PPC_PMC_IBM; 413 cur_cpu_spec->oprofile_cpu_type = "ppc64/power8"; 414 415 return 1; 416 } 417 418 static void init_pmu_power9(void) 419 { 420 if (hv_mode) 421 mtspr(SPRN_MMCRC, 0); 422 423 mtspr(SPRN_MMCRA, 0); 424 mtspr(SPRN_MMCR0, 0); 425 mtspr(SPRN_MMCR1, 0); 426 mtspr(SPRN_MMCR2, 0); 427 } 428 429 static int __init feat_enable_mce_power9(struct dt_cpu_feature *f) 430 { 431 cur_cpu_spec->platform = "power9"; 432 cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p9; 433 434 return 1; 435 } 436 437 static int __init feat_enable_pmu_power9(struct dt_cpu_feature *f) 438 { 439 hfscr_pmu_enable(); 440 441 init_pmu_power9(); 442 init_pmu_registers = init_pmu_power9; 443 444 cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA; 445 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT; 446 447 cur_cpu_spec->num_pmcs = 6; 448 cur_cpu_spec->pmc_type = PPC_PMC_IBM; 449 cur_cpu_spec->oprofile_cpu_type = "ppc64/power9"; 450 451 return 1; 452 } 453 454 static int __init feat_enable_tm(struct dt_cpu_feature *f) 455 { 456 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 457 feat_enable(f); 458 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NOSC; 459 return 1; 460 #endif 461 return 0; 462 } 463 464 static int __init feat_enable_fp(struct dt_cpu_feature *f) 465 { 466 feat_enable(f); 467 cur_cpu_spec->cpu_features &= ~CPU_FTR_FPU_UNAVAILABLE; 468 469 return 1; 470 } 471 472 static int __init feat_enable_vector(struct dt_cpu_feature *f) 473 { 474 #ifdef CONFIG_ALTIVEC 475 feat_enable(f); 476 cur_cpu_spec->cpu_features |= CPU_FTR_ALTIVEC; 477 cur_cpu_spec->cpu_features |= CPU_FTR_VMX_COPY; 478 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_ALTIVEC; 479 480 return 1; 481 #endif 482 return 0; 483 } 484 485 static int __init feat_enable_vsx(struct dt_cpu_feature *f) 486 { 487 #ifdef CONFIG_VSX 488 feat_enable(f); 489 cur_cpu_spec->cpu_features |= CPU_FTR_VSX; 490 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_VSX; 491 492 return 1; 493 #endif 494 return 0; 495 } 496 497 static int __init feat_enable_purr(struct dt_cpu_feature *f) 498 { 499 cur_cpu_spec->cpu_features |= CPU_FTR_PURR | CPU_FTR_SPURR; 500 501 return 1; 502 } 503 504 static int __init feat_enable_ebb(struct dt_cpu_feature *f) 505 { 506 /* 507 * PPC_FEATURE2_EBB is enabled in PMU init code because it has 508 * historically been related to the PMU facility. This may have 509 * to be decoupled if EBB becomes more generic. For now, follow 510 * existing convention. 511 */ 512 f->hwcap_bit_nr = -1; 513 feat_enable(f); 514 515 return 1; 516 } 517 518 static int __init feat_enable_dbell(struct dt_cpu_feature *f) 519 { 520 u64 lpcr; 521 522 /* P9 has an HFSCR for privileged state */ 523 feat_enable(f); 524 525 cur_cpu_spec->cpu_features |= CPU_FTR_DBELL; 526 527 lpcr = mfspr(SPRN_LPCR); 528 lpcr |= LPCR_PECEDH; /* hyp doorbell wakeup */ 529 mtspr(SPRN_LPCR, lpcr); 530 531 return 1; 532 } 533 534 static int __init feat_enable_hvi(struct dt_cpu_feature *f) 535 { 536 u64 lpcr; 537 538 /* 539 * POWER9 XIVE interrupts including in OPAL XICS compatibility 540 * are always delivered as hypervisor virtualization interrupts (HVI) 541 * rather than EE. 542 * 543 * However LPES0 is not set here, in the chance that an EE does get 544 * delivered to the host somehow, the EE handler would not expect it 545 * to be delivered in LPES0 mode (e.g., using SRR[01]). This could 546 * happen if there is a bug in interrupt controller code, or IC is 547 * misconfigured in systemsim. 548 */ 549 550 lpcr = mfspr(SPRN_LPCR); 551 lpcr |= LPCR_HVICE; /* enable hvi interrupts */ 552 lpcr |= LPCR_HEIC; /* disable ee interrupts when MSR_HV */ 553 lpcr |= LPCR_PECE_HVEE; /* hvi can wake from stop */ 554 mtspr(SPRN_LPCR, lpcr); 555 556 return 1; 557 } 558 559 static int __init feat_enable_large_ci(struct dt_cpu_feature *f) 560 { 561 cur_cpu_spec->mmu_features |= MMU_FTR_CI_LARGE_PAGE; 562 563 return 1; 564 } 565 566 struct dt_cpu_feature_match { 567 const char *name; 568 int (*enable)(struct dt_cpu_feature *f); 569 u64 cpu_ftr_bit_mask; 570 }; 571 572 static struct dt_cpu_feature_match __initdata 573 dt_cpu_feature_match_table[] = { 574 {"hypervisor", feat_enable_hv, 0}, 575 {"big-endian", feat_enable, 0}, 576 {"little-endian", feat_enable_le, CPU_FTR_REAL_LE}, 577 {"smt", feat_enable_smt, 0}, 578 {"interrupt-facilities", feat_enable, 0}, 579 {"timer-facilities", feat_enable, 0}, 580 {"timer-facilities-v3", feat_enable, 0}, 581 {"debug-facilities", feat_enable, 0}, 582 {"come-from-address-register", feat_enable, CPU_FTR_CFAR}, 583 {"branch-tracing", feat_enable, 0}, 584 {"floating-point", feat_enable_fp, 0}, 585 {"vector", feat_enable_vector, 0}, 586 {"vector-scalar", feat_enable_vsx, 0}, 587 {"vector-scalar-v3", feat_enable, 0}, 588 {"decimal-floating-point", feat_enable, 0}, 589 {"decimal-integer", feat_enable, 0}, 590 {"quadword-load-store", feat_enable, 0}, 591 {"vector-crypto", feat_enable, 0}, 592 {"mmu-hash", feat_enable_mmu_hash, 0}, 593 {"mmu-radix", feat_enable_mmu_radix, 0}, 594 {"mmu-hash-v3", feat_enable_mmu_hash_v3, 0}, 595 {"virtual-page-class-key-protection", feat_enable, 0}, 596 {"transactional-memory", feat_enable_tm, CPU_FTR_TM}, 597 {"transactional-memory-v3", feat_enable_tm, 0}, 598 {"tm-suspend-hypervisor-assist", feat_enable, CPU_FTR_P9_TM_HV_ASSIST}, 599 {"tm-suspend-xer-so-bug", feat_enable, CPU_FTR_P9_TM_XER_SO_BUG}, 600 {"idle-nap", feat_enable_idle_nap, 0}, 601 {"alignment-interrupt-dsisr", feat_enable_align_dsisr, 0}, 602 {"idle-stop", feat_enable_idle_stop, 0}, 603 {"machine-check-power8", feat_enable_mce_power8, 0}, 604 {"performance-monitor-power8", feat_enable_pmu_power8, 0}, 605 {"data-stream-control-register", feat_enable_dscr, CPU_FTR_DSCR}, 606 {"event-based-branch", feat_enable_ebb, 0}, 607 {"target-address-register", feat_enable, 0}, 608 {"branch-history-rolling-buffer", feat_enable, 0}, 609 {"control-register", feat_enable, CPU_FTR_CTRL}, 610 {"processor-control-facility", feat_enable_dbell, CPU_FTR_DBELL}, 611 {"processor-control-facility-v3", feat_enable_dbell, CPU_FTR_DBELL}, 612 {"processor-utilization-of-resources-register", feat_enable_purr, 0}, 613 {"no-execute", feat_enable, 0}, 614 {"strong-access-ordering", feat_enable, CPU_FTR_SAO}, 615 {"cache-inhibited-large-page", feat_enable_large_ci, 0}, 616 {"coprocessor-icswx", feat_enable, 0}, 617 {"hypervisor-virtualization-interrupt", feat_enable_hvi, 0}, 618 {"program-priority-register", feat_enable, CPU_FTR_HAS_PPR}, 619 {"wait", feat_enable, 0}, 620 {"atomic-memory-operations", feat_enable, 0}, 621 {"branch-v3", feat_enable, 0}, 622 {"copy-paste", feat_enable, 0}, 623 {"decimal-floating-point-v3", feat_enable, 0}, 624 {"decimal-integer-v3", feat_enable, 0}, 625 {"fixed-point-v3", feat_enable, 0}, 626 {"floating-point-v3", feat_enable, 0}, 627 {"group-start-register", feat_enable, 0}, 628 {"pc-relative-addressing", feat_enable, 0}, 629 {"machine-check-power9", feat_enable_mce_power9, 0}, 630 {"performance-monitor-power9", feat_enable_pmu_power9, 0}, 631 {"event-based-branch-v3", feat_enable, 0}, 632 {"random-number-generator", feat_enable, 0}, 633 {"system-call-vectored", feat_disable, 0}, 634 {"trace-interrupt-v3", feat_enable, 0}, 635 {"vector-v3", feat_enable, 0}, 636 {"vector-binary128", feat_enable, 0}, 637 {"vector-binary16", feat_enable, 0}, 638 {"wait-v3", feat_enable, 0}, 639 }; 640 641 static bool __initdata using_dt_cpu_ftrs; 642 static bool __initdata enable_unknown = true; 643 644 static int __init dt_cpu_ftrs_parse(char *str) 645 { 646 if (!str) 647 return 0; 648 649 if (!strcmp(str, "off")) 650 using_dt_cpu_ftrs = false; 651 else if (!strcmp(str, "known")) 652 enable_unknown = false; 653 else 654 return 1; 655 656 return 0; 657 } 658 early_param("dt_cpu_ftrs", dt_cpu_ftrs_parse); 659 660 static void __init cpufeatures_setup_start(u32 isa) 661 { 662 pr_info("setup for ISA %d\n", isa); 663 664 if (isa >= 3000) { 665 cur_cpu_spec->cpu_features |= CPU_FTR_ARCH_300; 666 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_ARCH_3_00; 667 } 668 } 669 670 static bool __init cpufeatures_process_feature(struct dt_cpu_feature *f) 671 { 672 const struct dt_cpu_feature_match *m; 673 bool known = false; 674 int i; 675 676 for (i = 0; i < ARRAY_SIZE(dt_cpu_feature_match_table); i++) { 677 m = &dt_cpu_feature_match_table[i]; 678 if (!strcmp(f->name, m->name)) { 679 known = true; 680 if (m->enable(f)) 681 break; 682 683 pr_info("not enabling: %s (disabled or unsupported by kernel)\n", 684 f->name); 685 return false; 686 } 687 } 688 689 if (!known && enable_unknown) { 690 if (!feat_try_enable_unknown(f)) { 691 pr_info("not enabling: %s (unknown and unsupported by kernel)\n", 692 f->name); 693 return false; 694 } 695 } 696 697 if (m->cpu_ftr_bit_mask) 698 cur_cpu_spec->cpu_features |= m->cpu_ftr_bit_mask; 699 700 if (known) 701 pr_debug("enabling: %s\n", f->name); 702 else 703 pr_debug("enabling: %s (unknown)\n", f->name); 704 705 return true; 706 } 707 708 static __init void cpufeatures_cpu_quirks(void) 709 { 710 int version = mfspr(SPRN_PVR); 711 712 /* 713 * Not all quirks can be derived from the cpufeatures device tree. 714 */ 715 if ((version & 0xffffff00) == 0x004e0100) 716 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD1; 717 else if ((version & 0xffffefff) == 0x004e0200) 718 ; /* DD2.0 has no feature flag */ 719 else if ((version & 0xffffefff) == 0x004e0201) 720 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1; 721 else if ((version & 0xffffefff) == 0x004e0202) { 722 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TM_HV_ASSIST; 723 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TM_XER_SO_BUG; 724 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1; 725 } else /* DD2.1 and up have DD2_1 */ 726 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1; 727 728 if ((version & 0xffff0000) == 0x004e0000) { 729 cur_cpu_spec->cpu_features &= ~(CPU_FTR_DAWR); 730 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_BUG; 731 } 732 733 /* 734 * PKEY was not in the initial base or feature node 735 * specification, but it should become optional in the next 736 * cpu feature version sequence. 737 */ 738 cur_cpu_spec->cpu_features |= CPU_FTR_PKEY; 739 } 740 741 static void __init cpufeatures_setup_finished(void) 742 { 743 cpufeatures_cpu_quirks(); 744 745 if (hv_mode && !(cur_cpu_spec->cpu_features & CPU_FTR_HVMODE)) { 746 pr_err("hypervisor not present in device tree but HV mode is enabled in the CPU. Enabling.\n"); 747 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE; 748 } 749 750 /* Make sure powerpc_base_platform is non-NULL */ 751 powerpc_base_platform = cur_cpu_spec->platform; 752 753 system_registers.lpcr = mfspr(SPRN_LPCR); 754 system_registers.hfscr = mfspr(SPRN_HFSCR); 755 system_registers.fscr = mfspr(SPRN_FSCR); 756 757 pr_info("final cpu/mmu features = 0x%016lx 0x%08x\n", 758 cur_cpu_spec->cpu_features, cur_cpu_spec->mmu_features); 759 } 760 761 static int __init disabled_on_cmdline(void) 762 { 763 unsigned long root, chosen; 764 const char *p; 765 766 root = of_get_flat_dt_root(); 767 chosen = of_get_flat_dt_subnode_by_name(root, "chosen"); 768 if (chosen == -FDT_ERR_NOTFOUND) 769 return false; 770 771 p = of_get_flat_dt_prop(chosen, "bootargs", NULL); 772 if (!p) 773 return false; 774 775 if (strstr(p, "dt_cpu_ftrs=off")) 776 return true; 777 778 return false; 779 } 780 781 static int __init fdt_find_cpu_features(unsigned long node, const char *uname, 782 int depth, void *data) 783 { 784 if (of_flat_dt_is_compatible(node, "ibm,powerpc-cpu-features") 785 && of_get_flat_dt_prop(node, "isa", NULL)) 786 return 1; 787 788 return 0; 789 } 790 791 bool __init dt_cpu_ftrs_in_use(void) 792 { 793 return using_dt_cpu_ftrs; 794 } 795 796 bool __init dt_cpu_ftrs_init(void *fdt) 797 { 798 using_dt_cpu_ftrs = false; 799 800 /* Setup and verify the FDT, if it fails we just bail */ 801 if (!early_init_dt_verify(fdt)) 802 return false; 803 804 if (!of_scan_flat_dt(fdt_find_cpu_features, NULL)) 805 return false; 806 807 if (disabled_on_cmdline()) 808 return false; 809 810 cpufeatures_setup_cpu(); 811 812 using_dt_cpu_ftrs = true; 813 return true; 814 } 815 816 static int nr_dt_cpu_features; 817 static struct dt_cpu_feature *dt_cpu_features; 818 819 static int __init process_cpufeatures_node(unsigned long node, 820 const char *uname, int i) 821 { 822 const __be32 *prop; 823 struct dt_cpu_feature *f; 824 int len; 825 826 f = &dt_cpu_features[i]; 827 memset(f, 0, sizeof(struct dt_cpu_feature)); 828 829 f->node = node; 830 831 f->name = uname; 832 833 prop = of_get_flat_dt_prop(node, "isa", &len); 834 if (!prop) { 835 pr_warn("%s: missing isa property\n", uname); 836 return 0; 837 } 838 f->isa = be32_to_cpup(prop); 839 840 prop = of_get_flat_dt_prop(node, "usable-privilege", &len); 841 if (!prop) { 842 pr_warn("%s: missing usable-privilege property", uname); 843 return 0; 844 } 845 f->usable_privilege = be32_to_cpup(prop); 846 847 prop = of_get_flat_dt_prop(node, "hv-support", &len); 848 if (prop) 849 f->hv_support = be32_to_cpup(prop); 850 else 851 f->hv_support = HV_SUPPORT_NONE; 852 853 prop = of_get_flat_dt_prop(node, "os-support", &len); 854 if (prop) 855 f->os_support = be32_to_cpup(prop); 856 else 857 f->os_support = OS_SUPPORT_NONE; 858 859 prop = of_get_flat_dt_prop(node, "hfscr-bit-nr", &len); 860 if (prop) 861 f->hfscr_bit_nr = be32_to_cpup(prop); 862 else 863 f->hfscr_bit_nr = -1; 864 prop = of_get_flat_dt_prop(node, "fscr-bit-nr", &len); 865 if (prop) 866 f->fscr_bit_nr = be32_to_cpup(prop); 867 else 868 f->fscr_bit_nr = -1; 869 prop = of_get_flat_dt_prop(node, "hwcap-bit-nr", &len); 870 if (prop) 871 f->hwcap_bit_nr = be32_to_cpup(prop); 872 else 873 f->hwcap_bit_nr = -1; 874 875 if (f->usable_privilege & USABLE_HV) { 876 if (!(mfmsr() & MSR_HV)) { 877 pr_warn("%s: HV feature passed to guest\n", uname); 878 return 0; 879 } 880 881 if (f->hv_support == HV_SUPPORT_NONE && f->hfscr_bit_nr != -1) { 882 pr_warn("%s: unwanted hfscr_bit_nr\n", uname); 883 return 0; 884 } 885 886 if (f->hv_support == HV_SUPPORT_HFSCR) { 887 if (f->hfscr_bit_nr == -1) { 888 pr_warn("%s: missing hfscr_bit_nr\n", uname); 889 return 0; 890 } 891 } 892 } else { 893 if (f->hv_support != HV_SUPPORT_NONE || f->hfscr_bit_nr != -1) { 894 pr_warn("%s: unwanted hv_support/hfscr_bit_nr\n", uname); 895 return 0; 896 } 897 } 898 899 if (f->usable_privilege & USABLE_OS) { 900 if (f->os_support == OS_SUPPORT_NONE && f->fscr_bit_nr != -1) { 901 pr_warn("%s: unwanted fscr_bit_nr\n", uname); 902 return 0; 903 } 904 905 if (f->os_support == OS_SUPPORT_FSCR) { 906 if (f->fscr_bit_nr == -1) { 907 pr_warn("%s: missing fscr_bit_nr\n", uname); 908 return 0; 909 } 910 } 911 } else { 912 if (f->os_support != OS_SUPPORT_NONE || f->fscr_bit_nr != -1) { 913 pr_warn("%s: unwanted os_support/fscr_bit_nr\n", uname); 914 return 0; 915 } 916 } 917 918 if (!(f->usable_privilege & USABLE_PR)) { 919 if (f->hwcap_bit_nr != -1) { 920 pr_warn("%s: unwanted hwcap_bit_nr\n", uname); 921 return 0; 922 } 923 } 924 925 /* Do all the independent features in the first pass */ 926 if (!of_get_flat_dt_prop(node, "dependencies", &len)) { 927 if (cpufeatures_process_feature(f)) 928 f->enabled = 1; 929 else 930 f->disabled = 1; 931 } 932 933 return 0; 934 } 935 936 static void __init cpufeatures_deps_enable(struct dt_cpu_feature *f) 937 { 938 const __be32 *prop; 939 int len; 940 int nr_deps; 941 int i; 942 943 if (f->enabled || f->disabled) 944 return; 945 946 prop = of_get_flat_dt_prop(f->node, "dependencies", &len); 947 if (!prop) { 948 pr_warn("%s: missing dependencies property", f->name); 949 return; 950 } 951 952 nr_deps = len / sizeof(int); 953 954 for (i = 0; i < nr_deps; i++) { 955 unsigned long phandle = be32_to_cpu(prop[i]); 956 int j; 957 958 for (j = 0; j < nr_dt_cpu_features; j++) { 959 struct dt_cpu_feature *d = &dt_cpu_features[j]; 960 961 if (of_get_flat_dt_phandle(d->node) == phandle) { 962 cpufeatures_deps_enable(d); 963 if (d->disabled) { 964 f->disabled = 1; 965 return; 966 } 967 } 968 } 969 } 970 971 if (cpufeatures_process_feature(f)) 972 f->enabled = 1; 973 else 974 f->disabled = 1; 975 } 976 977 static int __init scan_cpufeatures_subnodes(unsigned long node, 978 const char *uname, 979 void *data) 980 { 981 int *count = data; 982 983 process_cpufeatures_node(node, uname, *count); 984 985 (*count)++; 986 987 return 0; 988 } 989 990 static int __init count_cpufeatures_subnodes(unsigned long node, 991 const char *uname, 992 void *data) 993 { 994 int *count = data; 995 996 (*count)++; 997 998 return 0; 999 } 1000 1001 static int __init dt_cpu_ftrs_scan_callback(unsigned long node, const char 1002 *uname, int depth, void *data) 1003 { 1004 const __be32 *prop; 1005 int count, i; 1006 u32 isa; 1007 1008 /* We are scanning "ibm,powerpc-cpu-features" nodes only */ 1009 if (!of_flat_dt_is_compatible(node, "ibm,powerpc-cpu-features")) 1010 return 0; 1011 1012 prop = of_get_flat_dt_prop(node, "isa", NULL); 1013 if (!prop) 1014 /* We checked before, "can't happen" */ 1015 return 0; 1016 1017 isa = be32_to_cpup(prop); 1018 1019 /* Count and allocate space for cpu features */ 1020 of_scan_flat_dt_subnodes(node, count_cpufeatures_subnodes, 1021 &nr_dt_cpu_features); 1022 dt_cpu_features = __va( 1023 memblock_alloc(sizeof(struct dt_cpu_feature)* 1024 nr_dt_cpu_features, PAGE_SIZE)); 1025 1026 cpufeatures_setup_start(isa); 1027 1028 /* Scan nodes into dt_cpu_features and enable those without deps */ 1029 count = 0; 1030 of_scan_flat_dt_subnodes(node, scan_cpufeatures_subnodes, &count); 1031 1032 /* Recursive enable remaining features with dependencies */ 1033 for (i = 0; i < nr_dt_cpu_features; i++) { 1034 struct dt_cpu_feature *f = &dt_cpu_features[i]; 1035 1036 cpufeatures_deps_enable(f); 1037 } 1038 1039 prop = of_get_flat_dt_prop(node, "display-name", NULL); 1040 if (prop && strlen((char *)prop) != 0) { 1041 strlcpy(dt_cpu_name, (char *)prop, sizeof(dt_cpu_name)); 1042 cur_cpu_spec->cpu_name = dt_cpu_name; 1043 } 1044 1045 cpufeatures_setup_finished(); 1046 1047 memblock_free(__pa(dt_cpu_features), 1048 sizeof(struct dt_cpu_feature)*nr_dt_cpu_features); 1049 1050 return 0; 1051 } 1052 1053 void __init dt_cpu_ftrs_scan(void) 1054 { 1055 if (!using_dt_cpu_ftrs) 1056 return; 1057 1058 of_scan_flat_dt(dt_cpu_ftrs_scan_callback, NULL); 1059 } 1060