1 /* 2 * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org) 3 * 4 * Modifications for ppc64: 5 * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13 #include <linux/config.h> 14 #include <linux/string.h> 15 #include <linux/sched.h> 16 #include <linux/threads.h> 17 #include <linux/init.h> 18 #include <linux/module.h> 19 20 #include <asm/oprofile_impl.h> 21 #include <asm/cputable.h> 22 23 struct cpu_spec* cur_cpu_spec = NULL; 24 EXPORT_SYMBOL(cur_cpu_spec); 25 26 /* NOTE: 27 * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's 28 * the responsibility of the appropriate CPU save/restore functions to 29 * eventually copy these settings over. Those save/restore aren't yet 30 * part of the cputable though. That has to be fixed for both ppc32 31 * and ppc64 32 */ 33 #ifdef CONFIG_PPC64 34 extern void __setup_cpu_power3(unsigned long offset, struct cpu_spec* spec); 35 extern void __setup_cpu_power4(unsigned long offset, struct cpu_spec* spec); 36 extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec); 37 #else 38 extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec); 39 extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec); 40 extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec); 41 extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec); 42 extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec); 43 extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec); 44 extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec); 45 extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec); 46 #endif /* CONFIG_PPC32 */ 47 extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec); 48 49 /* This table only contains "desktop" CPUs, it need to be filled with embedded 50 * ones as well... 51 */ 52 #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \ 53 PPC_FEATURE_HAS_MMU) 54 #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64) 55 #define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4) 56 #define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5) 57 #define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS) 58 59 60 /* We only set the spe features if the kernel was compiled with 61 * spe support 62 */ 63 #ifdef CONFIG_SPE 64 #define PPC_FEATURE_SPE_COMP PPC_FEATURE_HAS_SPE 65 #else 66 #define PPC_FEATURE_SPE_COMP 0 67 #endif 68 69 struct cpu_spec cpu_specs[] = { 70 #ifdef CONFIG_PPC64 71 { /* Power3 */ 72 .pvr_mask = 0xffff0000, 73 .pvr_value = 0x00400000, 74 .cpu_name = "POWER3 (630)", 75 .cpu_features = CPU_FTRS_POWER3, 76 .cpu_user_features = COMMON_USER_PPC64, 77 .icache_bsize = 128, 78 .dcache_bsize = 128, 79 .num_pmcs = 8, 80 .cpu_setup = __setup_cpu_power3, 81 .oprofile_cpu_type = "ppc64/power3", 82 .oprofile_type = RS64, 83 }, 84 { /* Power3+ */ 85 .pvr_mask = 0xffff0000, 86 .pvr_value = 0x00410000, 87 .cpu_name = "POWER3 (630+)", 88 .cpu_features = CPU_FTRS_POWER3, 89 .cpu_user_features = COMMON_USER_PPC64, 90 .icache_bsize = 128, 91 .dcache_bsize = 128, 92 .num_pmcs = 8, 93 .cpu_setup = __setup_cpu_power3, 94 .oprofile_cpu_type = "ppc64/power3", 95 .oprofile_type = RS64, 96 }, 97 { /* Northstar */ 98 .pvr_mask = 0xffff0000, 99 .pvr_value = 0x00330000, 100 .cpu_name = "RS64-II (northstar)", 101 .cpu_features = CPU_FTRS_RS64, 102 .cpu_user_features = COMMON_USER_PPC64, 103 .icache_bsize = 128, 104 .dcache_bsize = 128, 105 .num_pmcs = 8, 106 .cpu_setup = __setup_cpu_power3, 107 .oprofile_cpu_type = "ppc64/rs64", 108 .oprofile_type = RS64, 109 }, 110 { /* Pulsar */ 111 .pvr_mask = 0xffff0000, 112 .pvr_value = 0x00340000, 113 .cpu_name = "RS64-III (pulsar)", 114 .cpu_features = CPU_FTRS_RS64, 115 .cpu_user_features = COMMON_USER_PPC64, 116 .icache_bsize = 128, 117 .dcache_bsize = 128, 118 .num_pmcs = 8, 119 .cpu_setup = __setup_cpu_power3, 120 .oprofile_cpu_type = "ppc64/rs64", 121 .oprofile_type = RS64, 122 }, 123 { /* I-star */ 124 .pvr_mask = 0xffff0000, 125 .pvr_value = 0x00360000, 126 .cpu_name = "RS64-III (icestar)", 127 .cpu_features = CPU_FTRS_RS64, 128 .cpu_user_features = COMMON_USER_PPC64, 129 .icache_bsize = 128, 130 .dcache_bsize = 128, 131 .num_pmcs = 8, 132 .cpu_setup = __setup_cpu_power3, 133 .oprofile_cpu_type = "ppc64/rs64", 134 .oprofile_type = RS64, 135 }, 136 { /* S-star */ 137 .pvr_mask = 0xffff0000, 138 .pvr_value = 0x00370000, 139 .cpu_name = "RS64-IV (sstar)", 140 .cpu_features = CPU_FTRS_RS64, 141 .cpu_user_features = COMMON_USER_PPC64, 142 .icache_bsize = 128, 143 .dcache_bsize = 128, 144 .num_pmcs = 8, 145 .cpu_setup = __setup_cpu_power3, 146 .oprofile_cpu_type = "ppc64/rs64", 147 .oprofile_type = RS64, 148 }, 149 { /* Power4 */ 150 .pvr_mask = 0xffff0000, 151 .pvr_value = 0x00350000, 152 .cpu_name = "POWER4 (gp)", 153 .cpu_features = CPU_FTRS_POWER4, 154 .cpu_user_features = COMMON_USER_POWER4, 155 .icache_bsize = 128, 156 .dcache_bsize = 128, 157 .num_pmcs = 8, 158 .cpu_setup = __setup_cpu_power4, 159 .oprofile_cpu_type = "ppc64/power4", 160 .oprofile_type = POWER4, 161 }, 162 { /* Power4+ */ 163 .pvr_mask = 0xffff0000, 164 .pvr_value = 0x00380000, 165 .cpu_name = "POWER4+ (gq)", 166 .cpu_features = CPU_FTRS_POWER4, 167 .cpu_user_features = COMMON_USER_POWER4, 168 .icache_bsize = 128, 169 .dcache_bsize = 128, 170 .num_pmcs = 8, 171 .cpu_setup = __setup_cpu_power4, 172 .oprofile_cpu_type = "ppc64/power4", 173 .oprofile_type = POWER4, 174 }, 175 { /* PPC970 */ 176 .pvr_mask = 0xffff0000, 177 .pvr_value = 0x00390000, 178 .cpu_name = "PPC970", 179 .cpu_features = CPU_FTRS_PPC970, 180 .cpu_user_features = COMMON_USER_POWER4 | 181 PPC_FEATURE_HAS_ALTIVEC_COMP, 182 .icache_bsize = 128, 183 .dcache_bsize = 128, 184 .num_pmcs = 8, 185 .cpu_setup = __setup_cpu_ppc970, 186 .oprofile_cpu_type = "ppc64/970", 187 .oprofile_type = POWER4, 188 }, 189 #endif /* CONFIG_PPC64 */ 190 #if defined(CONFIG_PPC64) || defined(CONFIG_POWER4) 191 { /* PPC970FX */ 192 .pvr_mask = 0xffff0000, 193 .pvr_value = 0x003c0000, 194 .cpu_name = "PPC970FX", 195 #ifdef CONFIG_PPC32 196 .cpu_features = CPU_FTRS_970_32, 197 #else 198 .cpu_features = CPU_FTRS_PPC970, 199 #endif 200 .cpu_user_features = COMMON_USER_POWER4 | 201 PPC_FEATURE_HAS_ALTIVEC_COMP, 202 .icache_bsize = 128, 203 .dcache_bsize = 128, 204 .num_pmcs = 8, 205 .cpu_setup = __setup_cpu_ppc970, 206 .oprofile_cpu_type = "ppc64/970", 207 .oprofile_type = POWER4, 208 }, 209 #endif /* defined(CONFIG_PPC64) || defined(CONFIG_POWER4) */ 210 #ifdef CONFIG_PPC64 211 { /* PPC970MP */ 212 .pvr_mask = 0xffff0000, 213 .pvr_value = 0x00440000, 214 .cpu_name = "PPC970MP", 215 .cpu_features = CPU_FTRS_PPC970, 216 .cpu_user_features = COMMON_USER_POWER4 | 217 PPC_FEATURE_HAS_ALTIVEC_COMP, 218 .icache_bsize = 128, 219 .dcache_bsize = 128, 220 .cpu_setup = __setup_cpu_ppc970, 221 .oprofile_cpu_type = "ppc64/970", 222 .oprofile_type = POWER4, 223 }, 224 { /* Power5 GR */ 225 .pvr_mask = 0xffff0000, 226 .pvr_value = 0x003a0000, 227 .cpu_name = "POWER5 (gr)", 228 .cpu_features = CPU_FTRS_POWER5, 229 .cpu_user_features = COMMON_USER_POWER5, 230 .icache_bsize = 128, 231 .dcache_bsize = 128, 232 .num_pmcs = 6, 233 .cpu_setup = __setup_cpu_power4, 234 .oprofile_cpu_type = "ppc64/power5", 235 .oprofile_type = POWER4, 236 }, 237 { /* Power5 GS */ 238 .pvr_mask = 0xffff0000, 239 .pvr_value = 0x003b0000, 240 .cpu_name = "POWER5+ (gs)", 241 .cpu_features = CPU_FTRS_POWER5, 242 .cpu_user_features = COMMON_USER_POWER5_PLUS, 243 .icache_bsize = 128, 244 .dcache_bsize = 128, 245 .num_pmcs = 6, 246 .cpu_setup = __setup_cpu_power4, 247 .oprofile_cpu_type = "ppc64/power5+", 248 .oprofile_type = POWER4, 249 }, 250 { /* Cell Broadband Engine */ 251 .pvr_mask = 0xffff0000, 252 .pvr_value = 0x00700000, 253 .cpu_name = "Cell Broadband Engine", 254 .cpu_features = CPU_FTRS_CELL, 255 .cpu_user_features = COMMON_USER_PPC64 | 256 PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP, 257 .icache_bsize = 128, 258 .dcache_bsize = 128, 259 .cpu_setup = __setup_cpu_be, 260 }, 261 { /* default match */ 262 .pvr_mask = 0x00000000, 263 .pvr_value = 0x00000000, 264 .cpu_name = "POWER4 (compatible)", 265 .cpu_features = CPU_FTRS_COMPATIBLE, 266 .cpu_user_features = COMMON_USER_PPC64, 267 .icache_bsize = 128, 268 .dcache_bsize = 128, 269 .num_pmcs = 6, 270 .cpu_setup = __setup_cpu_power4, 271 } 272 #endif /* CONFIG_PPC64 */ 273 #ifdef CONFIG_PPC32 274 #if CLASSIC_PPC 275 { /* 601 */ 276 .pvr_mask = 0xffff0000, 277 .pvr_value = 0x00010000, 278 .cpu_name = "601", 279 .cpu_features = CPU_FTRS_PPC601, 280 .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR | 281 PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB, 282 .icache_bsize = 32, 283 .dcache_bsize = 32, 284 }, 285 { /* 603 */ 286 .pvr_mask = 0xffff0000, 287 .pvr_value = 0x00030000, 288 .cpu_name = "603", 289 .cpu_features = CPU_FTRS_603, 290 .cpu_user_features = COMMON_USER, 291 .icache_bsize = 32, 292 .dcache_bsize = 32, 293 .cpu_setup = __setup_cpu_603 294 }, 295 { /* 603e */ 296 .pvr_mask = 0xffff0000, 297 .pvr_value = 0x00060000, 298 .cpu_name = "603e", 299 .cpu_features = CPU_FTRS_603, 300 .cpu_user_features = COMMON_USER, 301 .icache_bsize = 32, 302 .dcache_bsize = 32, 303 .cpu_setup = __setup_cpu_603 304 }, 305 { /* 603ev */ 306 .pvr_mask = 0xffff0000, 307 .pvr_value = 0x00070000, 308 .cpu_name = "603ev", 309 .cpu_features = CPU_FTRS_603, 310 .cpu_user_features = COMMON_USER, 311 .icache_bsize = 32, 312 .dcache_bsize = 32, 313 .cpu_setup = __setup_cpu_603 314 }, 315 { /* 604 */ 316 .pvr_mask = 0xffff0000, 317 .pvr_value = 0x00040000, 318 .cpu_name = "604", 319 .cpu_features = CPU_FTRS_604, 320 .cpu_user_features = COMMON_USER, 321 .icache_bsize = 32, 322 .dcache_bsize = 32, 323 .num_pmcs = 2, 324 .cpu_setup = __setup_cpu_604 325 }, 326 { /* 604e */ 327 .pvr_mask = 0xfffff000, 328 .pvr_value = 0x00090000, 329 .cpu_name = "604e", 330 .cpu_features = CPU_FTRS_604, 331 .cpu_user_features = COMMON_USER, 332 .icache_bsize = 32, 333 .dcache_bsize = 32, 334 .num_pmcs = 4, 335 .cpu_setup = __setup_cpu_604 336 }, 337 { /* 604r */ 338 .pvr_mask = 0xffff0000, 339 .pvr_value = 0x00090000, 340 .cpu_name = "604r", 341 .cpu_features = CPU_FTRS_604, 342 .cpu_user_features = COMMON_USER, 343 .icache_bsize = 32, 344 .dcache_bsize = 32, 345 .num_pmcs = 4, 346 .cpu_setup = __setup_cpu_604 347 }, 348 { /* 604ev */ 349 .pvr_mask = 0xffff0000, 350 .pvr_value = 0x000a0000, 351 .cpu_name = "604ev", 352 .cpu_features = CPU_FTRS_604, 353 .cpu_user_features = COMMON_USER, 354 .icache_bsize = 32, 355 .dcache_bsize = 32, 356 .num_pmcs = 4, 357 .cpu_setup = __setup_cpu_604 358 }, 359 { /* 740/750 (0x4202, don't support TAU ?) */ 360 .pvr_mask = 0xffffffff, 361 .pvr_value = 0x00084202, 362 .cpu_name = "740/750", 363 .cpu_features = CPU_FTRS_740_NOTAU, 364 .cpu_user_features = COMMON_USER, 365 .icache_bsize = 32, 366 .dcache_bsize = 32, 367 .num_pmcs = 4, 368 .cpu_setup = __setup_cpu_750 369 }, 370 { /* 750CX (80100 and 8010x?) */ 371 .pvr_mask = 0xfffffff0, 372 .pvr_value = 0x00080100, 373 .cpu_name = "750CX", 374 .cpu_features = CPU_FTRS_750, 375 .cpu_user_features = COMMON_USER, 376 .icache_bsize = 32, 377 .dcache_bsize = 32, 378 .num_pmcs = 4, 379 .cpu_setup = __setup_cpu_750cx 380 }, 381 { /* 750CX (82201 and 82202) */ 382 .pvr_mask = 0xfffffff0, 383 .pvr_value = 0x00082200, 384 .cpu_name = "750CX", 385 .cpu_features = CPU_FTRS_750, 386 .cpu_user_features = COMMON_USER, 387 .icache_bsize = 32, 388 .dcache_bsize = 32, 389 .num_pmcs = 4, 390 .cpu_setup = __setup_cpu_750cx 391 }, 392 { /* 750CXe (82214) */ 393 .pvr_mask = 0xfffffff0, 394 .pvr_value = 0x00082210, 395 .cpu_name = "750CXe", 396 .cpu_features = CPU_FTRS_750, 397 .cpu_user_features = COMMON_USER, 398 .icache_bsize = 32, 399 .dcache_bsize = 32, 400 .num_pmcs = 4, 401 .cpu_setup = __setup_cpu_750cx 402 }, 403 { /* 750CXe "Gekko" (83214) */ 404 .pvr_mask = 0xffffffff, 405 .pvr_value = 0x00083214, 406 .cpu_name = "750CXe", 407 .cpu_features = CPU_FTRS_750, 408 .cpu_user_features = COMMON_USER, 409 .icache_bsize = 32, 410 .dcache_bsize = 32, 411 .num_pmcs = 4, 412 .cpu_setup = __setup_cpu_750cx 413 }, 414 { /* 745/755 */ 415 .pvr_mask = 0xfffff000, 416 .pvr_value = 0x00083000, 417 .cpu_name = "745/755", 418 .cpu_features = CPU_FTRS_750, 419 .cpu_user_features = COMMON_USER, 420 .icache_bsize = 32, 421 .dcache_bsize = 32, 422 .num_pmcs = 4, 423 .cpu_setup = __setup_cpu_750 424 }, 425 { /* 750FX rev 1.x */ 426 .pvr_mask = 0xffffff00, 427 .pvr_value = 0x70000100, 428 .cpu_name = "750FX", 429 .cpu_features = CPU_FTRS_750FX1, 430 .cpu_user_features = COMMON_USER, 431 .icache_bsize = 32, 432 .dcache_bsize = 32, 433 .num_pmcs = 4, 434 .cpu_setup = __setup_cpu_750 435 }, 436 { /* 750FX rev 2.0 must disable HID0[DPM] */ 437 .pvr_mask = 0xffffffff, 438 .pvr_value = 0x70000200, 439 .cpu_name = "750FX", 440 .cpu_features = CPU_FTRS_750FX2, 441 .cpu_user_features = COMMON_USER, 442 .icache_bsize = 32, 443 .dcache_bsize = 32, 444 .num_pmcs = 4, 445 .cpu_setup = __setup_cpu_750 446 }, 447 { /* 750FX (All revs except 2.0) */ 448 .pvr_mask = 0xffff0000, 449 .pvr_value = 0x70000000, 450 .cpu_name = "750FX", 451 .cpu_features = CPU_FTRS_750FX, 452 .cpu_user_features = COMMON_USER, 453 .icache_bsize = 32, 454 .dcache_bsize = 32, 455 .num_pmcs = 4, 456 .cpu_setup = __setup_cpu_750fx 457 }, 458 { /* 750GX */ 459 .pvr_mask = 0xffff0000, 460 .pvr_value = 0x70020000, 461 .cpu_name = "750GX", 462 .cpu_features = CPU_FTRS_750GX, 463 .cpu_user_features = COMMON_USER, 464 .icache_bsize = 32, 465 .dcache_bsize = 32, 466 .num_pmcs = 4, 467 .cpu_setup = __setup_cpu_750fx 468 }, 469 { /* 740/750 (L2CR bit need fixup for 740) */ 470 .pvr_mask = 0xffff0000, 471 .pvr_value = 0x00080000, 472 .cpu_name = "740/750", 473 .cpu_features = CPU_FTRS_740, 474 .cpu_user_features = COMMON_USER, 475 .icache_bsize = 32, 476 .dcache_bsize = 32, 477 .num_pmcs = 4, 478 .cpu_setup = __setup_cpu_750 479 }, 480 { /* 7400 rev 1.1 ? (no TAU) */ 481 .pvr_mask = 0xffffffff, 482 .pvr_value = 0x000c1101, 483 .cpu_name = "7400 (1.1)", 484 .cpu_features = CPU_FTRS_7400_NOTAU, 485 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 486 .icache_bsize = 32, 487 .dcache_bsize = 32, 488 .num_pmcs = 4, 489 .cpu_setup = __setup_cpu_7400 490 }, 491 { /* 7400 */ 492 .pvr_mask = 0xffff0000, 493 .pvr_value = 0x000c0000, 494 .cpu_name = "7400", 495 .cpu_features = CPU_FTRS_7400, 496 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 497 .icache_bsize = 32, 498 .dcache_bsize = 32, 499 .num_pmcs = 4, 500 .cpu_setup = __setup_cpu_7400 501 }, 502 { /* 7410 */ 503 .pvr_mask = 0xffff0000, 504 .pvr_value = 0x800c0000, 505 .cpu_name = "7410", 506 .cpu_features = CPU_FTRS_7400, 507 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 508 .icache_bsize = 32, 509 .dcache_bsize = 32, 510 .num_pmcs = 4, 511 .cpu_setup = __setup_cpu_7410 512 }, 513 { /* 7450 2.0 - no doze/nap */ 514 .pvr_mask = 0xffffffff, 515 .pvr_value = 0x80000200, 516 .cpu_name = "7450", 517 .cpu_features = CPU_FTRS_7450_20, 518 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 519 .icache_bsize = 32, 520 .dcache_bsize = 32, 521 .num_pmcs = 6, 522 .cpu_setup = __setup_cpu_745x, 523 .oprofile_cpu_type = "ppc/7450", 524 .oprofile_type = G4, 525 }, 526 { /* 7450 2.1 */ 527 .pvr_mask = 0xffffffff, 528 .pvr_value = 0x80000201, 529 .cpu_name = "7450", 530 .cpu_features = CPU_FTRS_7450_21, 531 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 532 .icache_bsize = 32, 533 .dcache_bsize = 32, 534 .num_pmcs = 6, 535 .cpu_setup = __setup_cpu_745x, 536 .oprofile_cpu_type = "ppc/7450", 537 .oprofile_type = G4, 538 }, 539 { /* 7450 2.3 and newer */ 540 .pvr_mask = 0xffff0000, 541 .pvr_value = 0x80000000, 542 .cpu_name = "7450", 543 .cpu_features = CPU_FTRS_7450_23, 544 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 545 .icache_bsize = 32, 546 .dcache_bsize = 32, 547 .num_pmcs = 6, 548 .cpu_setup = __setup_cpu_745x, 549 .oprofile_cpu_type = "ppc/7450", 550 .oprofile_type = G4, 551 }, 552 { /* 7455 rev 1.x */ 553 .pvr_mask = 0xffffff00, 554 .pvr_value = 0x80010100, 555 .cpu_name = "7455", 556 .cpu_features = CPU_FTRS_7455_1, 557 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 558 .icache_bsize = 32, 559 .dcache_bsize = 32, 560 .num_pmcs = 6, 561 .cpu_setup = __setup_cpu_745x, 562 .oprofile_cpu_type = "ppc/7450", 563 .oprofile_type = G4, 564 }, 565 { /* 7455 rev 2.0 */ 566 .pvr_mask = 0xffffffff, 567 .pvr_value = 0x80010200, 568 .cpu_name = "7455", 569 .cpu_features = CPU_FTRS_7455_20, 570 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 571 .icache_bsize = 32, 572 .dcache_bsize = 32, 573 .num_pmcs = 6, 574 .cpu_setup = __setup_cpu_745x, 575 .oprofile_cpu_type = "ppc/7450", 576 .oprofile_type = G4, 577 }, 578 { /* 7455 others */ 579 .pvr_mask = 0xffff0000, 580 .pvr_value = 0x80010000, 581 .cpu_name = "7455", 582 .cpu_features = CPU_FTRS_7455, 583 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 584 .icache_bsize = 32, 585 .dcache_bsize = 32, 586 .num_pmcs = 6, 587 .cpu_setup = __setup_cpu_745x, 588 .oprofile_cpu_type = "ppc/7450", 589 .oprofile_type = G4, 590 }, 591 { /* 7447/7457 Rev 1.0 */ 592 .pvr_mask = 0xffffffff, 593 .pvr_value = 0x80020100, 594 .cpu_name = "7447/7457", 595 .cpu_features = CPU_FTRS_7447_10, 596 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 597 .icache_bsize = 32, 598 .dcache_bsize = 32, 599 .num_pmcs = 6, 600 .cpu_setup = __setup_cpu_745x, 601 .oprofile_cpu_type = "ppc/7450", 602 .oprofile_type = G4, 603 }, 604 { /* 7447/7457 Rev 1.1 */ 605 .pvr_mask = 0xffffffff, 606 .pvr_value = 0x80020101, 607 .cpu_name = "7447/7457", 608 .cpu_features = CPU_FTRS_7447_10, 609 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 610 .icache_bsize = 32, 611 .dcache_bsize = 32, 612 .num_pmcs = 6, 613 .cpu_setup = __setup_cpu_745x, 614 .oprofile_cpu_type = "ppc/7450", 615 .oprofile_type = G4, 616 }, 617 { /* 7447/7457 Rev 1.2 and later */ 618 .pvr_mask = 0xffff0000, 619 .pvr_value = 0x80020000, 620 .cpu_name = "7447/7457", 621 .cpu_features = CPU_FTRS_7447, 622 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 623 .icache_bsize = 32, 624 .dcache_bsize = 32, 625 .num_pmcs = 6, 626 .cpu_setup = __setup_cpu_745x, 627 .oprofile_cpu_type = "ppc/7450", 628 .oprofile_type = G4, 629 }, 630 { /* 7447A */ 631 .pvr_mask = 0xffff0000, 632 .pvr_value = 0x80030000, 633 .cpu_name = "7447A", 634 .cpu_features = CPU_FTRS_7447A, 635 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 636 .icache_bsize = 32, 637 .dcache_bsize = 32, 638 .num_pmcs = 6, 639 .cpu_setup = __setup_cpu_745x, 640 .oprofile_cpu_type = "ppc/7450", 641 .oprofile_type = G4, 642 }, 643 { /* 7448 */ 644 .pvr_mask = 0xffff0000, 645 .pvr_value = 0x80040000, 646 .cpu_name = "7448", 647 .cpu_features = CPU_FTRS_7447A, 648 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 649 .icache_bsize = 32, 650 .dcache_bsize = 32, 651 .num_pmcs = 6, 652 .cpu_setup = __setup_cpu_745x, 653 .oprofile_cpu_type = "ppc/7450", 654 .oprofile_type = G4, 655 }, 656 { /* 82xx (8240, 8245, 8260 are all 603e cores) */ 657 .pvr_mask = 0x7fff0000, 658 .pvr_value = 0x00810000, 659 .cpu_name = "82xx", 660 .cpu_features = CPU_FTRS_82XX, 661 .cpu_user_features = COMMON_USER, 662 .icache_bsize = 32, 663 .dcache_bsize = 32, 664 .cpu_setup = __setup_cpu_603 665 }, 666 { /* All G2_LE (603e core, plus some) have the same pvr */ 667 .pvr_mask = 0x7fff0000, 668 .pvr_value = 0x00820000, 669 .cpu_name = "G2_LE", 670 .cpu_features = CPU_FTRS_G2_LE, 671 .cpu_user_features = COMMON_USER, 672 .icache_bsize = 32, 673 .dcache_bsize = 32, 674 .cpu_setup = __setup_cpu_603 675 }, 676 { /* e300 (a 603e core, plus some) on 83xx */ 677 .pvr_mask = 0x7fff0000, 678 .pvr_value = 0x00830000, 679 .cpu_name = "e300", 680 .cpu_features = CPU_FTRS_E300, 681 .cpu_user_features = COMMON_USER, 682 .icache_bsize = 32, 683 .dcache_bsize = 32, 684 .cpu_setup = __setup_cpu_603 685 }, 686 { /* default match, we assume split I/D cache & TB (non-601)... */ 687 .pvr_mask = 0x00000000, 688 .pvr_value = 0x00000000, 689 .cpu_name = "(generic PPC)", 690 .cpu_features = CPU_FTRS_CLASSIC32, 691 .cpu_user_features = COMMON_USER, 692 .icache_bsize = 32, 693 .dcache_bsize = 32, 694 }, 695 #endif /* CLASSIC_PPC */ 696 #ifdef CONFIG_8xx 697 { /* 8xx */ 698 .pvr_mask = 0xffff0000, 699 .pvr_value = 0x00500000, 700 .cpu_name = "8xx", 701 /* CPU_FTR_MAYBE_CAN_DOZE is possible, 702 * if the 8xx code is there.... */ 703 .cpu_features = CPU_FTRS_8XX, 704 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 705 .icache_bsize = 16, 706 .dcache_bsize = 16, 707 }, 708 #endif /* CONFIG_8xx */ 709 #ifdef CONFIG_40x 710 { /* 403GC */ 711 .pvr_mask = 0xffffff00, 712 .pvr_value = 0x00200200, 713 .cpu_name = "403GC", 714 .cpu_features = CPU_FTRS_40X, 715 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 716 .icache_bsize = 16, 717 .dcache_bsize = 16, 718 }, 719 { /* 403GCX */ 720 .pvr_mask = 0xffffff00, 721 .pvr_value = 0x00201400, 722 .cpu_name = "403GCX", 723 .cpu_features = CPU_FTRS_40X, 724 .cpu_user_features = PPC_FEATURE_32 | 725 PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB, 726 .icache_bsize = 16, 727 .dcache_bsize = 16, 728 }, 729 { /* 403G ?? */ 730 .pvr_mask = 0xffff0000, 731 .pvr_value = 0x00200000, 732 .cpu_name = "403G ??", 733 .cpu_features = CPU_FTRS_40X, 734 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 735 .icache_bsize = 16, 736 .dcache_bsize = 16, 737 }, 738 { /* 405GP */ 739 .pvr_mask = 0xffff0000, 740 .pvr_value = 0x40110000, 741 .cpu_name = "405GP", 742 .cpu_features = CPU_FTRS_40X, 743 .cpu_user_features = PPC_FEATURE_32 | 744 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 745 .icache_bsize = 32, 746 .dcache_bsize = 32, 747 }, 748 { /* STB 03xxx */ 749 .pvr_mask = 0xffff0000, 750 .pvr_value = 0x40130000, 751 .cpu_name = "STB03xxx", 752 .cpu_features = CPU_FTRS_40X, 753 .cpu_user_features = PPC_FEATURE_32 | 754 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 755 .icache_bsize = 32, 756 .dcache_bsize = 32, 757 }, 758 { /* STB 04xxx */ 759 .pvr_mask = 0xffff0000, 760 .pvr_value = 0x41810000, 761 .cpu_name = "STB04xxx", 762 .cpu_features = CPU_FTRS_40X, 763 .cpu_user_features = PPC_FEATURE_32 | 764 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 765 .icache_bsize = 32, 766 .dcache_bsize = 32, 767 }, 768 { /* NP405L */ 769 .pvr_mask = 0xffff0000, 770 .pvr_value = 0x41610000, 771 .cpu_name = "NP405L", 772 .cpu_features = CPU_FTRS_40X, 773 .cpu_user_features = PPC_FEATURE_32 | 774 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 775 .icache_bsize = 32, 776 .dcache_bsize = 32, 777 }, 778 { /* NP4GS3 */ 779 .pvr_mask = 0xffff0000, 780 .pvr_value = 0x40B10000, 781 .cpu_name = "NP4GS3", 782 .cpu_features = CPU_FTRS_40X, 783 .cpu_user_features = PPC_FEATURE_32 | 784 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 785 .icache_bsize = 32, 786 .dcache_bsize = 32, 787 }, 788 { /* NP405H */ 789 .pvr_mask = 0xffff0000, 790 .pvr_value = 0x41410000, 791 .cpu_name = "NP405H", 792 .cpu_features = CPU_FTRS_40X, 793 .cpu_user_features = PPC_FEATURE_32 | 794 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 795 .icache_bsize = 32, 796 .dcache_bsize = 32, 797 }, 798 { /* 405GPr */ 799 .pvr_mask = 0xffff0000, 800 .pvr_value = 0x50910000, 801 .cpu_name = "405GPr", 802 .cpu_features = CPU_FTRS_40X, 803 .cpu_user_features = PPC_FEATURE_32 | 804 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 805 .icache_bsize = 32, 806 .dcache_bsize = 32, 807 }, 808 { /* STBx25xx */ 809 .pvr_mask = 0xffff0000, 810 .pvr_value = 0x51510000, 811 .cpu_name = "STBx25xx", 812 .cpu_features = CPU_FTRS_40X, 813 .cpu_user_features = PPC_FEATURE_32 | 814 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 815 .icache_bsize = 32, 816 .dcache_bsize = 32, 817 }, 818 { /* 405LP */ 819 .pvr_mask = 0xffff0000, 820 .pvr_value = 0x41F10000, 821 .cpu_name = "405LP", 822 .cpu_features = CPU_FTRS_40X, 823 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 824 .icache_bsize = 32, 825 .dcache_bsize = 32, 826 }, 827 { /* Xilinx Virtex-II Pro */ 828 .pvr_mask = 0xffff0000, 829 .pvr_value = 0x20010000, 830 .cpu_name = "Virtex-II Pro", 831 .cpu_features = CPU_FTRS_40X, 832 .cpu_user_features = PPC_FEATURE_32 | 833 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 834 .icache_bsize = 32, 835 .dcache_bsize = 32, 836 }, 837 { /* 405EP */ 838 .pvr_mask = 0xffff0000, 839 .pvr_value = 0x51210000, 840 .cpu_name = "405EP", 841 .cpu_features = CPU_FTRS_40X, 842 .cpu_user_features = PPC_FEATURE_32 | 843 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 844 .icache_bsize = 32, 845 .dcache_bsize = 32, 846 }, 847 848 #endif /* CONFIG_40x */ 849 #ifdef CONFIG_44x 850 { 851 .pvr_mask = 0xf0000fff, 852 .pvr_value = 0x40000850, 853 .cpu_name = "440EP Rev. A", 854 .cpu_features = CPU_FTRS_44X, 855 .cpu_user_features = COMMON_USER, /* 440EP has an FPU */ 856 .icache_bsize = 32, 857 .dcache_bsize = 32, 858 }, 859 { 860 .pvr_mask = 0xf0000fff, 861 .pvr_value = 0x400008d3, 862 .cpu_name = "440EP Rev. B", 863 .cpu_features = CPU_FTRS_44X, 864 .cpu_user_features = COMMON_USER, /* 440EP has an FPU */ 865 .icache_bsize = 32, 866 .dcache_bsize = 32, 867 }, 868 { /* 440GP Rev. B */ 869 .pvr_mask = 0xf0000fff, 870 .pvr_value = 0x40000440, 871 .cpu_name = "440GP Rev. B", 872 .cpu_features = CPU_FTRS_44X, 873 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 874 .icache_bsize = 32, 875 .dcache_bsize = 32, 876 }, 877 { /* 440GP Rev. C */ 878 .pvr_mask = 0xf0000fff, 879 .pvr_value = 0x40000481, 880 .cpu_name = "440GP Rev. C", 881 .cpu_features = CPU_FTRS_44X, 882 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 883 .icache_bsize = 32, 884 .dcache_bsize = 32, 885 }, 886 { /* 440GX Rev. A */ 887 .pvr_mask = 0xf0000fff, 888 .pvr_value = 0x50000850, 889 .cpu_name = "440GX Rev. A", 890 .cpu_features = CPU_FTRS_44X, 891 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 892 .icache_bsize = 32, 893 .dcache_bsize = 32, 894 }, 895 { /* 440GX Rev. B */ 896 .pvr_mask = 0xf0000fff, 897 .pvr_value = 0x50000851, 898 .cpu_name = "440GX Rev. B", 899 .cpu_features = CPU_FTRS_44X, 900 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 901 .icache_bsize = 32, 902 .dcache_bsize = 32, 903 }, 904 { /* 440GX Rev. C */ 905 .pvr_mask = 0xf0000fff, 906 .pvr_value = 0x50000892, 907 .cpu_name = "440GX Rev. C", 908 .cpu_features = CPU_FTRS_44X, 909 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 910 .icache_bsize = 32, 911 .dcache_bsize = 32, 912 }, 913 { /* 440GX Rev. F */ 914 .pvr_mask = 0xf0000fff, 915 .pvr_value = 0x50000894, 916 .cpu_name = "440GX Rev. F", 917 .cpu_features = CPU_FTRS_44X, 918 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 919 .icache_bsize = 32, 920 .dcache_bsize = 32, 921 }, 922 { /* 440SP Rev. A */ 923 .pvr_mask = 0xff000fff, 924 .pvr_value = 0x53000891, 925 .cpu_name = "440SP Rev. A", 926 .cpu_features = CPU_FTRS_44X, 927 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 928 .icache_bsize = 32, 929 .dcache_bsize = 32, 930 }, 931 { /* 440SPe Rev. A */ 932 .pvr_mask = 0xff000fff, 933 .pvr_value = 0x53000890, 934 .cpu_name = "440SPe Rev. A", 935 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 936 CPU_FTR_USE_TB, 937 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 938 .icache_bsize = 32, 939 .dcache_bsize = 32, 940 }, 941 #endif /* CONFIG_44x */ 942 #ifdef CONFIG_FSL_BOOKE 943 { /* e200z5 */ 944 .pvr_mask = 0xfff00000, 945 .pvr_value = 0x81000000, 946 .cpu_name = "e200z5", 947 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ 948 .cpu_features = CPU_FTRS_E200, 949 .cpu_user_features = PPC_FEATURE_32 | 950 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_EFP_SINGLE | 951 PPC_FEATURE_UNIFIED_CACHE, 952 .dcache_bsize = 32, 953 }, 954 { /* e200z6 */ 955 .pvr_mask = 0xfff00000, 956 .pvr_value = 0x81100000, 957 .cpu_name = "e200z6", 958 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ 959 .cpu_features = CPU_FTRS_E200, 960 .cpu_user_features = PPC_FEATURE_32 | 961 PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP | 962 PPC_FEATURE_HAS_EFP_SINGLE | 963 PPC_FEATURE_UNIFIED_CACHE, 964 .dcache_bsize = 32, 965 }, 966 { /* e500 */ 967 .pvr_mask = 0xffff0000, 968 .pvr_value = 0x80200000, 969 .cpu_name = "e500", 970 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ 971 .cpu_features = CPU_FTRS_E500, 972 .cpu_user_features = PPC_FEATURE_32 | 973 PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP | 974 PPC_FEATURE_HAS_EFP_SINGLE, 975 .icache_bsize = 32, 976 .dcache_bsize = 32, 977 .num_pmcs = 4, 978 .oprofile_cpu_type = "ppc/e500", 979 .oprofile_type = BOOKE, 980 }, 981 { /* e500v2 */ 982 .pvr_mask = 0xffff0000, 983 .pvr_value = 0x80210000, 984 .cpu_name = "e500v2", 985 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ 986 .cpu_features = CPU_FTRS_E500_2, 987 .cpu_user_features = PPC_FEATURE_32 | 988 PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP | 989 PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE, 990 .icache_bsize = 32, 991 .dcache_bsize = 32, 992 .num_pmcs = 4, 993 .oprofile_cpu_type = "ppc/e500", 994 .oprofile_type = BOOKE, 995 }, 996 #endif 997 #if !CLASSIC_PPC 998 { /* default match */ 999 .pvr_mask = 0x00000000, 1000 .pvr_value = 0x00000000, 1001 .cpu_name = "(generic PPC)", 1002 .cpu_features = CPU_FTRS_GENERIC_32, 1003 .cpu_user_features = PPC_FEATURE_32, 1004 .icache_bsize = 32, 1005 .dcache_bsize = 32, 1006 } 1007 #endif /* !CLASSIC_PPC */ 1008 #endif /* CONFIG_PPC32 */ 1009 }; 1010