1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org) 4 * 5 * Modifications for ppc64: 6 * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com> 7 */ 8 9 #include <linux/string.h> 10 #include <linux/sched.h> 11 #include <linux/threads.h> 12 #include <linux/init.h> 13 #include <linux/export.h> 14 #include <linux/jump_label.h> 15 #include <linux/of.h> 16 17 #include <asm/cputable.h> 18 #include <asm/mce.h> 19 #include <asm/mmu.h> 20 #include <asm/setup.h> 21 22 static struct cpu_spec the_cpu_spec __read_mostly; 23 24 struct cpu_spec* cur_cpu_spec __read_mostly = NULL; 25 EXPORT_SYMBOL(cur_cpu_spec); 26 27 /* The platform string corresponding to the real PVR */ 28 const char *powerpc_base_platform; 29 30 /* NOTE: 31 * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's 32 * the responsibility of the appropriate CPU save/restore functions to 33 * eventually copy these settings over. Those save/restore aren't yet 34 * part of the cputable though. That has to be fixed for both ppc32 35 * and ppc64 36 */ 37 #ifdef CONFIG_PPC32 38 extern void __setup_cpu_e500v1(unsigned long offset, struct cpu_spec* spec); 39 extern void __setup_cpu_e500v2(unsigned long offset, struct cpu_spec* spec); 40 extern void __setup_cpu_e500mc(unsigned long offset, struct cpu_spec* spec); 41 extern void __setup_cpu_440ep(unsigned long offset, struct cpu_spec* spec); 42 extern void __setup_cpu_440epx(unsigned long offset, struct cpu_spec* spec); 43 extern void __setup_cpu_440gx(unsigned long offset, struct cpu_spec* spec); 44 extern void __setup_cpu_440grx(unsigned long offset, struct cpu_spec* spec); 45 extern void __setup_cpu_440spe(unsigned long offset, struct cpu_spec* spec); 46 extern void __setup_cpu_440x5(unsigned long offset, struct cpu_spec* spec); 47 extern void __setup_cpu_460ex(unsigned long offset, struct cpu_spec* spec); 48 extern void __setup_cpu_460gt(unsigned long offset, struct cpu_spec* spec); 49 extern void __setup_cpu_460sx(unsigned long offset, struct cpu_spec *spec); 50 extern void __setup_cpu_apm821xx(unsigned long offset, struct cpu_spec *spec); 51 extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec); 52 extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec); 53 extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec); 54 extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec); 55 extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec); 56 extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec); 57 extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec); 58 extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec); 59 #endif /* CONFIG_PPC32 */ 60 #ifdef CONFIG_PPC64 61 #include <asm/cpu_setup_power.h> 62 extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec); 63 extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec); 64 extern void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec* spec); 65 extern void __restore_cpu_pa6t(void); 66 extern void __restore_cpu_ppc970(void); 67 extern long __machine_check_early_realmode_p7(struct pt_regs *regs); 68 extern long __machine_check_early_realmode_p8(struct pt_regs *regs); 69 extern long __machine_check_early_realmode_p9(struct pt_regs *regs); 70 #endif /* CONFIG_PPC64 */ 71 #if defined(CONFIG_E500) 72 extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec); 73 extern void __setup_cpu_e6500(unsigned long offset, struct cpu_spec* spec); 74 extern void __restore_cpu_e5500(void); 75 extern void __restore_cpu_e6500(void); 76 #endif /* CONFIG_E500 */ 77 78 /* This table only contains "desktop" CPUs, it need to be filled with embedded 79 * ones as well... 80 */ 81 #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \ 82 PPC_FEATURE_HAS_MMU) 83 #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64) 84 #define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4) 85 #define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5 |\ 86 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP) 87 #define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS|\ 88 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP) 89 #define COMMON_USER_POWER6 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\ 90 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \ 91 PPC_FEATURE_TRUE_LE | \ 92 PPC_FEATURE_PSERIES_PERFMON_COMPAT) 93 #define COMMON_USER_POWER7 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\ 94 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \ 95 PPC_FEATURE_TRUE_LE | \ 96 PPC_FEATURE_PSERIES_PERFMON_COMPAT) 97 #define COMMON_USER2_POWER7 (PPC_FEATURE2_DSCR) 98 #define COMMON_USER_POWER8 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\ 99 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \ 100 PPC_FEATURE_TRUE_LE | \ 101 PPC_FEATURE_PSERIES_PERFMON_COMPAT) 102 #define COMMON_USER2_POWER8 (PPC_FEATURE2_ARCH_2_07 | \ 103 PPC_FEATURE2_HTM_COMP | \ 104 PPC_FEATURE2_HTM_NOSC_COMP | \ 105 PPC_FEATURE2_DSCR | \ 106 PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | \ 107 PPC_FEATURE2_VEC_CRYPTO) 108 #define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\ 109 PPC_FEATURE_TRUE_LE | \ 110 PPC_FEATURE_HAS_ALTIVEC_COMP) 111 #define COMMON_USER_POWER9 COMMON_USER_POWER8 112 #define COMMON_USER2_POWER9 (COMMON_USER2_POWER8 | \ 113 PPC_FEATURE2_ARCH_3_00 | \ 114 PPC_FEATURE2_HAS_IEEE128 | \ 115 PPC_FEATURE2_DARN | \ 116 PPC_FEATURE2_SCV) 117 #define COMMON_USER_POWER10 COMMON_USER_POWER9 118 #define COMMON_USER2_POWER10 (PPC_FEATURE2_ARCH_3_1 | \ 119 PPC_FEATURE2_MMA | \ 120 PPC_FEATURE2_ARCH_3_00 | \ 121 PPC_FEATURE2_HAS_IEEE128 | \ 122 PPC_FEATURE2_DARN | \ 123 PPC_FEATURE2_SCV | \ 124 PPC_FEATURE2_ARCH_2_07 | \ 125 PPC_FEATURE2_DSCR | \ 126 PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | \ 127 PPC_FEATURE2_VEC_CRYPTO) 128 129 #ifdef CONFIG_PPC_BOOK3E_64 130 #define COMMON_USER_BOOKE (COMMON_USER_PPC64 | PPC_FEATURE_BOOKE) 131 #else 132 #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \ 133 PPC_FEATURE_BOOKE) 134 #endif 135 136 static struct cpu_spec __initdata cpu_specs[] = { 137 #ifdef CONFIG_PPC_BOOK3S_64 138 { /* PPC970 */ 139 .pvr_mask = 0xffff0000, 140 .pvr_value = 0x00390000, 141 .cpu_name = "PPC970", 142 .cpu_features = CPU_FTRS_PPC970, 143 .cpu_user_features = COMMON_USER_POWER4 | 144 PPC_FEATURE_HAS_ALTIVEC_COMP, 145 .mmu_features = MMU_FTRS_PPC970, 146 .icache_bsize = 128, 147 .dcache_bsize = 128, 148 .num_pmcs = 8, 149 .pmc_type = PPC_PMC_IBM, 150 .cpu_setup = __setup_cpu_ppc970, 151 .cpu_restore = __restore_cpu_ppc970, 152 .platform = "ppc970", 153 }, 154 { /* PPC970FX */ 155 .pvr_mask = 0xffff0000, 156 .pvr_value = 0x003c0000, 157 .cpu_name = "PPC970FX", 158 .cpu_features = CPU_FTRS_PPC970, 159 .cpu_user_features = COMMON_USER_POWER4 | 160 PPC_FEATURE_HAS_ALTIVEC_COMP, 161 .mmu_features = MMU_FTRS_PPC970, 162 .icache_bsize = 128, 163 .dcache_bsize = 128, 164 .num_pmcs = 8, 165 .pmc_type = PPC_PMC_IBM, 166 .cpu_setup = __setup_cpu_ppc970, 167 .cpu_restore = __restore_cpu_ppc970, 168 .platform = "ppc970", 169 }, 170 { /* PPC970MP DD1.0 - no DEEPNAP, use regular 970 init */ 171 .pvr_mask = 0xffffffff, 172 .pvr_value = 0x00440100, 173 .cpu_name = "PPC970MP", 174 .cpu_features = CPU_FTRS_PPC970, 175 .cpu_user_features = COMMON_USER_POWER4 | 176 PPC_FEATURE_HAS_ALTIVEC_COMP, 177 .mmu_features = MMU_FTRS_PPC970, 178 .icache_bsize = 128, 179 .dcache_bsize = 128, 180 .num_pmcs = 8, 181 .pmc_type = PPC_PMC_IBM, 182 .cpu_setup = __setup_cpu_ppc970, 183 .cpu_restore = __restore_cpu_ppc970, 184 .platform = "ppc970", 185 }, 186 { /* PPC970MP */ 187 .pvr_mask = 0xffff0000, 188 .pvr_value = 0x00440000, 189 .cpu_name = "PPC970MP", 190 .cpu_features = CPU_FTRS_PPC970, 191 .cpu_user_features = COMMON_USER_POWER4 | 192 PPC_FEATURE_HAS_ALTIVEC_COMP, 193 .mmu_features = MMU_FTRS_PPC970, 194 .icache_bsize = 128, 195 .dcache_bsize = 128, 196 .num_pmcs = 8, 197 .pmc_type = PPC_PMC_IBM, 198 .cpu_setup = __setup_cpu_ppc970MP, 199 .cpu_restore = __restore_cpu_ppc970, 200 .platform = "ppc970", 201 }, 202 { /* PPC970GX */ 203 .pvr_mask = 0xffff0000, 204 .pvr_value = 0x00450000, 205 .cpu_name = "PPC970GX", 206 .cpu_features = CPU_FTRS_PPC970, 207 .cpu_user_features = COMMON_USER_POWER4 | 208 PPC_FEATURE_HAS_ALTIVEC_COMP, 209 .mmu_features = MMU_FTRS_PPC970, 210 .icache_bsize = 128, 211 .dcache_bsize = 128, 212 .num_pmcs = 8, 213 .pmc_type = PPC_PMC_IBM, 214 .cpu_setup = __setup_cpu_ppc970, 215 .platform = "ppc970", 216 }, 217 { /* Power5 GR */ 218 .pvr_mask = 0xffff0000, 219 .pvr_value = 0x003a0000, 220 .cpu_name = "POWER5 (gr)", 221 .cpu_features = CPU_FTRS_POWER5, 222 .cpu_user_features = COMMON_USER_POWER5, 223 .mmu_features = MMU_FTRS_POWER5, 224 .icache_bsize = 128, 225 .dcache_bsize = 128, 226 .num_pmcs = 6, 227 .pmc_type = PPC_PMC_IBM, 228 .platform = "power5", 229 }, 230 { /* Power5++ */ 231 .pvr_mask = 0xffffff00, 232 .pvr_value = 0x003b0300, 233 .cpu_name = "POWER5+ (gs)", 234 .cpu_features = CPU_FTRS_POWER5, 235 .cpu_user_features = COMMON_USER_POWER5_PLUS, 236 .mmu_features = MMU_FTRS_POWER5, 237 .icache_bsize = 128, 238 .dcache_bsize = 128, 239 .num_pmcs = 6, 240 .platform = "power5+", 241 }, 242 { /* Power5 GS */ 243 .pvr_mask = 0xffff0000, 244 .pvr_value = 0x003b0000, 245 .cpu_name = "POWER5+ (gs)", 246 .cpu_features = CPU_FTRS_POWER5, 247 .cpu_user_features = COMMON_USER_POWER5_PLUS, 248 .mmu_features = MMU_FTRS_POWER5, 249 .icache_bsize = 128, 250 .dcache_bsize = 128, 251 .num_pmcs = 6, 252 .pmc_type = PPC_PMC_IBM, 253 .platform = "power5+", 254 }, 255 { /* POWER6 in P5+ mode; 2.04-compliant processor */ 256 .pvr_mask = 0xffffffff, 257 .pvr_value = 0x0f000001, 258 .cpu_name = "POWER5+", 259 .cpu_features = CPU_FTRS_POWER5, 260 .cpu_user_features = COMMON_USER_POWER5_PLUS, 261 .mmu_features = MMU_FTRS_POWER5, 262 .icache_bsize = 128, 263 .dcache_bsize = 128, 264 .platform = "power5+", 265 }, 266 { /* Power6 */ 267 .pvr_mask = 0xffff0000, 268 .pvr_value = 0x003e0000, 269 .cpu_name = "POWER6 (raw)", 270 .cpu_features = CPU_FTRS_POWER6, 271 .cpu_user_features = COMMON_USER_POWER6 | 272 PPC_FEATURE_POWER6_EXT, 273 .mmu_features = MMU_FTRS_POWER6, 274 .icache_bsize = 128, 275 .dcache_bsize = 128, 276 .num_pmcs = 6, 277 .pmc_type = PPC_PMC_IBM, 278 .platform = "power6x", 279 }, 280 { /* 2.05-compliant processor, i.e. Power6 "architected" mode */ 281 .pvr_mask = 0xffffffff, 282 .pvr_value = 0x0f000002, 283 .cpu_name = "POWER6 (architected)", 284 .cpu_features = CPU_FTRS_POWER6, 285 .cpu_user_features = COMMON_USER_POWER6, 286 .mmu_features = MMU_FTRS_POWER6, 287 .icache_bsize = 128, 288 .dcache_bsize = 128, 289 .platform = "power6", 290 }, 291 { /* 2.06-compliant processor, i.e. Power7 "architected" mode */ 292 .pvr_mask = 0xffffffff, 293 .pvr_value = 0x0f000003, 294 .cpu_name = "POWER7 (architected)", 295 .cpu_features = CPU_FTRS_POWER7, 296 .cpu_user_features = COMMON_USER_POWER7, 297 .cpu_user_features2 = COMMON_USER2_POWER7, 298 .mmu_features = MMU_FTRS_POWER7, 299 .icache_bsize = 128, 300 .dcache_bsize = 128, 301 .cpu_setup = __setup_cpu_power7, 302 .cpu_restore = __restore_cpu_power7, 303 .machine_check_early = __machine_check_early_realmode_p7, 304 .platform = "power7", 305 }, 306 { /* 2.07-compliant processor, i.e. Power8 "architected" mode */ 307 .pvr_mask = 0xffffffff, 308 .pvr_value = 0x0f000004, 309 .cpu_name = "POWER8 (architected)", 310 .cpu_features = CPU_FTRS_POWER8, 311 .cpu_user_features = COMMON_USER_POWER8, 312 .cpu_user_features2 = COMMON_USER2_POWER8, 313 .mmu_features = MMU_FTRS_POWER8, 314 .icache_bsize = 128, 315 .dcache_bsize = 128, 316 .cpu_setup = __setup_cpu_power8, 317 .cpu_restore = __restore_cpu_power8, 318 .machine_check_early = __machine_check_early_realmode_p8, 319 .platform = "power8", 320 }, 321 { /* 3.00-compliant processor, i.e. Power9 "architected" mode */ 322 .pvr_mask = 0xffffffff, 323 .pvr_value = 0x0f000005, 324 .cpu_name = "POWER9 (architected)", 325 .cpu_features = CPU_FTRS_POWER9, 326 .cpu_user_features = COMMON_USER_POWER9, 327 .cpu_user_features2 = COMMON_USER2_POWER9, 328 .mmu_features = MMU_FTRS_POWER9, 329 .icache_bsize = 128, 330 .dcache_bsize = 128, 331 .cpu_setup = __setup_cpu_power9, 332 .cpu_restore = __restore_cpu_power9, 333 .platform = "power9", 334 }, 335 { /* 3.1-compliant processor, i.e. Power10 "architected" mode */ 336 .pvr_mask = 0xffffffff, 337 .pvr_value = 0x0f000006, 338 .cpu_name = "POWER10 (architected)", 339 .cpu_features = CPU_FTRS_POWER10, 340 .cpu_user_features = COMMON_USER_POWER10, 341 .cpu_user_features2 = COMMON_USER2_POWER10, 342 .mmu_features = MMU_FTRS_POWER10, 343 .icache_bsize = 128, 344 .dcache_bsize = 128, 345 .cpu_setup = __setup_cpu_power10, 346 .cpu_restore = __restore_cpu_power10, 347 .platform = "power10", 348 }, 349 { /* Power7 */ 350 .pvr_mask = 0xffff0000, 351 .pvr_value = 0x003f0000, 352 .cpu_name = "POWER7 (raw)", 353 .cpu_features = CPU_FTRS_POWER7, 354 .cpu_user_features = COMMON_USER_POWER7, 355 .cpu_user_features2 = COMMON_USER2_POWER7, 356 .mmu_features = MMU_FTRS_POWER7, 357 .icache_bsize = 128, 358 .dcache_bsize = 128, 359 .num_pmcs = 6, 360 .pmc_type = PPC_PMC_IBM, 361 .cpu_setup = __setup_cpu_power7, 362 .cpu_restore = __restore_cpu_power7, 363 .machine_check_early = __machine_check_early_realmode_p7, 364 .platform = "power7", 365 }, 366 { /* Power7+ */ 367 .pvr_mask = 0xffff0000, 368 .pvr_value = 0x004A0000, 369 .cpu_name = "POWER7+ (raw)", 370 .cpu_features = CPU_FTRS_POWER7, 371 .cpu_user_features = COMMON_USER_POWER7, 372 .cpu_user_features2 = COMMON_USER2_POWER7, 373 .mmu_features = MMU_FTRS_POWER7, 374 .icache_bsize = 128, 375 .dcache_bsize = 128, 376 .num_pmcs = 6, 377 .pmc_type = PPC_PMC_IBM, 378 .cpu_setup = __setup_cpu_power7, 379 .cpu_restore = __restore_cpu_power7, 380 .machine_check_early = __machine_check_early_realmode_p7, 381 .platform = "power7+", 382 }, 383 { /* Power8E */ 384 .pvr_mask = 0xffff0000, 385 .pvr_value = 0x004b0000, 386 .cpu_name = "POWER8E (raw)", 387 .cpu_features = CPU_FTRS_POWER8E, 388 .cpu_user_features = COMMON_USER_POWER8, 389 .cpu_user_features2 = COMMON_USER2_POWER8, 390 .mmu_features = MMU_FTRS_POWER8, 391 .icache_bsize = 128, 392 .dcache_bsize = 128, 393 .num_pmcs = 6, 394 .pmc_type = PPC_PMC_IBM, 395 .cpu_setup = __setup_cpu_power8, 396 .cpu_restore = __restore_cpu_power8, 397 .machine_check_early = __machine_check_early_realmode_p8, 398 .platform = "power8", 399 }, 400 { /* Power8NVL */ 401 .pvr_mask = 0xffff0000, 402 .pvr_value = 0x004c0000, 403 .cpu_name = "POWER8NVL (raw)", 404 .cpu_features = CPU_FTRS_POWER8, 405 .cpu_user_features = COMMON_USER_POWER8, 406 .cpu_user_features2 = COMMON_USER2_POWER8, 407 .mmu_features = MMU_FTRS_POWER8, 408 .icache_bsize = 128, 409 .dcache_bsize = 128, 410 .num_pmcs = 6, 411 .pmc_type = PPC_PMC_IBM, 412 .cpu_setup = __setup_cpu_power8, 413 .cpu_restore = __restore_cpu_power8, 414 .machine_check_early = __machine_check_early_realmode_p8, 415 .platform = "power8", 416 }, 417 { /* Power8 */ 418 .pvr_mask = 0xffff0000, 419 .pvr_value = 0x004d0000, 420 .cpu_name = "POWER8 (raw)", 421 .cpu_features = CPU_FTRS_POWER8, 422 .cpu_user_features = COMMON_USER_POWER8, 423 .cpu_user_features2 = COMMON_USER2_POWER8, 424 .mmu_features = MMU_FTRS_POWER8, 425 .icache_bsize = 128, 426 .dcache_bsize = 128, 427 .num_pmcs = 6, 428 .pmc_type = PPC_PMC_IBM, 429 .cpu_setup = __setup_cpu_power8, 430 .cpu_restore = __restore_cpu_power8, 431 .machine_check_early = __machine_check_early_realmode_p8, 432 .platform = "power8", 433 }, 434 { /* Power9 DD2.0 */ 435 .pvr_mask = 0xffffefff, 436 .pvr_value = 0x004e0200, 437 .cpu_name = "POWER9 (raw)", 438 .cpu_features = CPU_FTRS_POWER9_DD2_0, 439 .cpu_user_features = COMMON_USER_POWER9, 440 .cpu_user_features2 = COMMON_USER2_POWER9, 441 .mmu_features = MMU_FTRS_POWER9, 442 .icache_bsize = 128, 443 .dcache_bsize = 128, 444 .num_pmcs = 6, 445 .pmc_type = PPC_PMC_IBM, 446 .cpu_setup = __setup_cpu_power9, 447 .cpu_restore = __restore_cpu_power9, 448 .machine_check_early = __machine_check_early_realmode_p9, 449 .platform = "power9", 450 }, 451 { /* Power9 DD 2.1 */ 452 .pvr_mask = 0xffffefff, 453 .pvr_value = 0x004e0201, 454 .cpu_name = "POWER9 (raw)", 455 .cpu_features = CPU_FTRS_POWER9_DD2_1, 456 .cpu_user_features = COMMON_USER_POWER9, 457 .cpu_user_features2 = COMMON_USER2_POWER9, 458 .mmu_features = MMU_FTRS_POWER9, 459 .icache_bsize = 128, 460 .dcache_bsize = 128, 461 .num_pmcs = 6, 462 .pmc_type = PPC_PMC_IBM, 463 .cpu_setup = __setup_cpu_power9, 464 .cpu_restore = __restore_cpu_power9, 465 .machine_check_early = __machine_check_early_realmode_p9, 466 .platform = "power9", 467 }, 468 { /* Power9 DD2.2 */ 469 .pvr_mask = 0xffffefff, 470 .pvr_value = 0x004e0202, 471 .cpu_name = "POWER9 (raw)", 472 .cpu_features = CPU_FTRS_POWER9_DD2_2, 473 .cpu_user_features = COMMON_USER_POWER9, 474 .cpu_user_features2 = COMMON_USER2_POWER9, 475 .mmu_features = MMU_FTRS_POWER9, 476 .icache_bsize = 128, 477 .dcache_bsize = 128, 478 .num_pmcs = 6, 479 .pmc_type = PPC_PMC_IBM, 480 .cpu_setup = __setup_cpu_power9, 481 .cpu_restore = __restore_cpu_power9, 482 .machine_check_early = __machine_check_early_realmode_p9, 483 .platform = "power9", 484 }, 485 { /* Power9 DD2.3 or later */ 486 .pvr_mask = 0xffff0000, 487 .pvr_value = 0x004e0000, 488 .cpu_name = "POWER9 (raw)", 489 .cpu_features = CPU_FTRS_POWER9_DD2_3, 490 .cpu_user_features = COMMON_USER_POWER9, 491 .cpu_user_features2 = COMMON_USER2_POWER9, 492 .mmu_features = MMU_FTRS_POWER9, 493 .icache_bsize = 128, 494 .dcache_bsize = 128, 495 .num_pmcs = 6, 496 .pmc_type = PPC_PMC_IBM, 497 .cpu_setup = __setup_cpu_power9, 498 .cpu_restore = __restore_cpu_power9, 499 .machine_check_early = __machine_check_early_realmode_p9, 500 .platform = "power9", 501 }, 502 { /* Power10 */ 503 .pvr_mask = 0xffff0000, 504 .pvr_value = 0x00800000, 505 .cpu_name = "POWER10 (raw)", 506 .cpu_features = CPU_FTRS_POWER10, 507 .cpu_user_features = COMMON_USER_POWER10, 508 .cpu_user_features2 = COMMON_USER2_POWER10, 509 .mmu_features = MMU_FTRS_POWER10, 510 .icache_bsize = 128, 511 .dcache_bsize = 128, 512 .num_pmcs = 6, 513 .pmc_type = PPC_PMC_IBM, 514 .cpu_setup = __setup_cpu_power10, 515 .cpu_restore = __restore_cpu_power10, 516 .machine_check_early = __machine_check_early_realmode_p10, 517 .platform = "power10", 518 }, 519 { /* Cell Broadband Engine */ 520 .pvr_mask = 0xffff0000, 521 .pvr_value = 0x00700000, 522 .cpu_name = "Cell Broadband Engine", 523 .cpu_features = CPU_FTRS_CELL, 524 .cpu_user_features = COMMON_USER_PPC64 | 525 PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP | 526 PPC_FEATURE_SMT, 527 .mmu_features = MMU_FTRS_CELL, 528 .icache_bsize = 128, 529 .dcache_bsize = 128, 530 .num_pmcs = 4, 531 .pmc_type = PPC_PMC_IBM, 532 .platform = "ppc-cell-be", 533 }, 534 { /* PA Semi PA6T */ 535 .pvr_mask = 0x7fff0000, 536 .pvr_value = 0x00900000, 537 .cpu_name = "PA6T", 538 .cpu_features = CPU_FTRS_PA6T, 539 .cpu_user_features = COMMON_USER_PA6T, 540 .mmu_features = MMU_FTRS_PA6T, 541 .icache_bsize = 64, 542 .dcache_bsize = 64, 543 .num_pmcs = 6, 544 .pmc_type = PPC_PMC_PA6T, 545 .cpu_setup = __setup_cpu_pa6t, 546 .cpu_restore = __restore_cpu_pa6t, 547 .platform = "pa6t", 548 }, 549 { /* default match */ 550 .pvr_mask = 0x00000000, 551 .pvr_value = 0x00000000, 552 .cpu_name = "POWER5 (compatible)", 553 .cpu_features = CPU_FTRS_COMPATIBLE, 554 .cpu_user_features = COMMON_USER_PPC64, 555 .mmu_features = MMU_FTRS_POWER, 556 .icache_bsize = 128, 557 .dcache_bsize = 128, 558 .num_pmcs = 6, 559 .pmc_type = PPC_PMC_IBM, 560 .platform = "power5", 561 } 562 #endif /* CONFIG_PPC_BOOK3S_64 */ 563 564 #ifdef CONFIG_PPC32 565 #ifdef CONFIG_PPC_BOOK3S_32 566 #ifdef CONFIG_PPC_BOOK3S_604 567 { /* 604 */ 568 .pvr_mask = 0xffff0000, 569 .pvr_value = 0x00040000, 570 .cpu_name = "604", 571 .cpu_features = CPU_FTRS_604, 572 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 573 .mmu_features = MMU_FTR_HPTE_TABLE, 574 .icache_bsize = 32, 575 .dcache_bsize = 32, 576 .num_pmcs = 2, 577 .cpu_setup = __setup_cpu_604, 578 .machine_check = machine_check_generic, 579 .platform = "ppc604", 580 }, 581 { /* 604e */ 582 .pvr_mask = 0xfffff000, 583 .pvr_value = 0x00090000, 584 .cpu_name = "604e", 585 .cpu_features = CPU_FTRS_604, 586 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 587 .mmu_features = MMU_FTR_HPTE_TABLE, 588 .icache_bsize = 32, 589 .dcache_bsize = 32, 590 .num_pmcs = 4, 591 .cpu_setup = __setup_cpu_604, 592 .machine_check = machine_check_generic, 593 .platform = "ppc604", 594 }, 595 { /* 604r */ 596 .pvr_mask = 0xffff0000, 597 .pvr_value = 0x00090000, 598 .cpu_name = "604r", 599 .cpu_features = CPU_FTRS_604, 600 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 601 .mmu_features = MMU_FTR_HPTE_TABLE, 602 .icache_bsize = 32, 603 .dcache_bsize = 32, 604 .num_pmcs = 4, 605 .cpu_setup = __setup_cpu_604, 606 .machine_check = machine_check_generic, 607 .platform = "ppc604", 608 }, 609 { /* 604ev */ 610 .pvr_mask = 0xffff0000, 611 .pvr_value = 0x000a0000, 612 .cpu_name = "604ev", 613 .cpu_features = CPU_FTRS_604, 614 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 615 .mmu_features = MMU_FTR_HPTE_TABLE, 616 .icache_bsize = 32, 617 .dcache_bsize = 32, 618 .num_pmcs = 4, 619 .cpu_setup = __setup_cpu_604, 620 .machine_check = machine_check_generic, 621 .platform = "ppc604", 622 }, 623 { /* 740/750 (0x4202, don't support TAU ?) */ 624 .pvr_mask = 0xffffffff, 625 .pvr_value = 0x00084202, 626 .cpu_name = "740/750", 627 .cpu_features = CPU_FTRS_740_NOTAU, 628 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 629 .mmu_features = MMU_FTR_HPTE_TABLE, 630 .icache_bsize = 32, 631 .dcache_bsize = 32, 632 .num_pmcs = 4, 633 .cpu_setup = __setup_cpu_750, 634 .machine_check = machine_check_generic, 635 .platform = "ppc750", 636 }, 637 { /* 750CX (80100 and 8010x?) */ 638 .pvr_mask = 0xfffffff0, 639 .pvr_value = 0x00080100, 640 .cpu_name = "750CX", 641 .cpu_features = CPU_FTRS_750, 642 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 643 .mmu_features = MMU_FTR_HPTE_TABLE, 644 .icache_bsize = 32, 645 .dcache_bsize = 32, 646 .num_pmcs = 4, 647 .cpu_setup = __setup_cpu_750cx, 648 .machine_check = machine_check_generic, 649 .platform = "ppc750", 650 }, 651 { /* 750CX (82201 and 82202) */ 652 .pvr_mask = 0xfffffff0, 653 .pvr_value = 0x00082200, 654 .cpu_name = "750CX", 655 .cpu_features = CPU_FTRS_750, 656 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 657 .mmu_features = MMU_FTR_HPTE_TABLE, 658 .icache_bsize = 32, 659 .dcache_bsize = 32, 660 .num_pmcs = 4, 661 .pmc_type = PPC_PMC_IBM, 662 .cpu_setup = __setup_cpu_750cx, 663 .machine_check = machine_check_generic, 664 .platform = "ppc750", 665 }, 666 { /* 750CXe (82214) */ 667 .pvr_mask = 0xfffffff0, 668 .pvr_value = 0x00082210, 669 .cpu_name = "750CXe", 670 .cpu_features = CPU_FTRS_750, 671 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 672 .mmu_features = MMU_FTR_HPTE_TABLE, 673 .icache_bsize = 32, 674 .dcache_bsize = 32, 675 .num_pmcs = 4, 676 .pmc_type = PPC_PMC_IBM, 677 .cpu_setup = __setup_cpu_750cx, 678 .machine_check = machine_check_generic, 679 .platform = "ppc750", 680 }, 681 { /* 750CXe "Gekko" (83214) */ 682 .pvr_mask = 0xffffffff, 683 .pvr_value = 0x00083214, 684 .cpu_name = "750CXe", 685 .cpu_features = CPU_FTRS_750, 686 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 687 .mmu_features = MMU_FTR_HPTE_TABLE, 688 .icache_bsize = 32, 689 .dcache_bsize = 32, 690 .num_pmcs = 4, 691 .pmc_type = PPC_PMC_IBM, 692 .cpu_setup = __setup_cpu_750cx, 693 .machine_check = machine_check_generic, 694 .platform = "ppc750", 695 }, 696 { /* 750CL (and "Broadway") */ 697 .pvr_mask = 0xfffff0e0, 698 .pvr_value = 0x00087000, 699 .cpu_name = "750CL", 700 .cpu_features = CPU_FTRS_750CL, 701 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 702 .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 703 .icache_bsize = 32, 704 .dcache_bsize = 32, 705 .num_pmcs = 4, 706 .pmc_type = PPC_PMC_IBM, 707 .cpu_setup = __setup_cpu_750, 708 .machine_check = machine_check_generic, 709 .platform = "ppc750", 710 }, 711 { /* 745/755 */ 712 .pvr_mask = 0xfffff000, 713 .pvr_value = 0x00083000, 714 .cpu_name = "745/755", 715 .cpu_features = CPU_FTRS_750, 716 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 717 .mmu_features = MMU_FTR_HPTE_TABLE, 718 .icache_bsize = 32, 719 .dcache_bsize = 32, 720 .num_pmcs = 4, 721 .pmc_type = PPC_PMC_IBM, 722 .cpu_setup = __setup_cpu_750, 723 .machine_check = machine_check_generic, 724 .platform = "ppc750", 725 }, 726 { /* 750FX rev 1.x */ 727 .pvr_mask = 0xffffff00, 728 .pvr_value = 0x70000100, 729 .cpu_name = "750FX", 730 .cpu_features = CPU_FTRS_750FX1, 731 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 732 .mmu_features = MMU_FTR_HPTE_TABLE, 733 .icache_bsize = 32, 734 .dcache_bsize = 32, 735 .num_pmcs = 4, 736 .pmc_type = PPC_PMC_IBM, 737 .cpu_setup = __setup_cpu_750, 738 .machine_check = machine_check_generic, 739 .platform = "ppc750", 740 }, 741 { /* 750FX rev 2.0 must disable HID0[DPM] */ 742 .pvr_mask = 0xffffffff, 743 .pvr_value = 0x70000200, 744 .cpu_name = "750FX", 745 .cpu_features = CPU_FTRS_750FX2, 746 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 747 .mmu_features = MMU_FTR_HPTE_TABLE, 748 .icache_bsize = 32, 749 .dcache_bsize = 32, 750 .num_pmcs = 4, 751 .pmc_type = PPC_PMC_IBM, 752 .cpu_setup = __setup_cpu_750, 753 .machine_check = machine_check_generic, 754 .platform = "ppc750", 755 }, 756 { /* 750FX (All revs except 2.0) */ 757 .pvr_mask = 0xffff0000, 758 .pvr_value = 0x70000000, 759 .cpu_name = "750FX", 760 .cpu_features = CPU_FTRS_750FX, 761 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 762 .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 763 .icache_bsize = 32, 764 .dcache_bsize = 32, 765 .num_pmcs = 4, 766 .pmc_type = PPC_PMC_IBM, 767 .cpu_setup = __setup_cpu_750fx, 768 .machine_check = machine_check_generic, 769 .platform = "ppc750", 770 }, 771 { /* 750GX */ 772 .pvr_mask = 0xffff0000, 773 .pvr_value = 0x70020000, 774 .cpu_name = "750GX", 775 .cpu_features = CPU_FTRS_750GX, 776 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 777 .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 778 .icache_bsize = 32, 779 .dcache_bsize = 32, 780 .num_pmcs = 4, 781 .pmc_type = PPC_PMC_IBM, 782 .cpu_setup = __setup_cpu_750fx, 783 .machine_check = machine_check_generic, 784 .platform = "ppc750", 785 }, 786 { /* 740/750 (L2CR bit need fixup for 740) */ 787 .pvr_mask = 0xffff0000, 788 .pvr_value = 0x00080000, 789 .cpu_name = "740/750", 790 .cpu_features = CPU_FTRS_740, 791 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 792 .mmu_features = MMU_FTR_HPTE_TABLE, 793 .icache_bsize = 32, 794 .dcache_bsize = 32, 795 .num_pmcs = 4, 796 .pmc_type = PPC_PMC_IBM, 797 .cpu_setup = __setup_cpu_750, 798 .machine_check = machine_check_generic, 799 .platform = "ppc750", 800 }, 801 { /* 7400 rev 1.1 ? (no TAU) */ 802 .pvr_mask = 0xffffffff, 803 .pvr_value = 0x000c1101, 804 .cpu_name = "7400 (1.1)", 805 .cpu_features = CPU_FTRS_7400_NOTAU, 806 .cpu_user_features = COMMON_USER | 807 PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 808 .mmu_features = MMU_FTR_HPTE_TABLE, 809 .icache_bsize = 32, 810 .dcache_bsize = 32, 811 .num_pmcs = 4, 812 .pmc_type = PPC_PMC_G4, 813 .cpu_setup = __setup_cpu_7400, 814 .machine_check = machine_check_generic, 815 .platform = "ppc7400", 816 }, 817 { /* 7400 */ 818 .pvr_mask = 0xffff0000, 819 .pvr_value = 0x000c0000, 820 .cpu_name = "7400", 821 .cpu_features = CPU_FTRS_7400, 822 .cpu_user_features = COMMON_USER | 823 PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 824 .mmu_features = MMU_FTR_HPTE_TABLE, 825 .icache_bsize = 32, 826 .dcache_bsize = 32, 827 .num_pmcs = 4, 828 .pmc_type = PPC_PMC_G4, 829 .cpu_setup = __setup_cpu_7400, 830 .machine_check = machine_check_generic, 831 .platform = "ppc7400", 832 }, 833 { /* 7410 */ 834 .pvr_mask = 0xffff0000, 835 .pvr_value = 0x800c0000, 836 .cpu_name = "7410", 837 .cpu_features = CPU_FTRS_7400, 838 .cpu_user_features = COMMON_USER | 839 PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 840 .mmu_features = MMU_FTR_HPTE_TABLE, 841 .icache_bsize = 32, 842 .dcache_bsize = 32, 843 .num_pmcs = 4, 844 .pmc_type = PPC_PMC_G4, 845 .cpu_setup = __setup_cpu_7410, 846 .machine_check = machine_check_generic, 847 .platform = "ppc7400", 848 }, 849 { /* 7450 2.0 - no doze/nap */ 850 .pvr_mask = 0xffffffff, 851 .pvr_value = 0x80000200, 852 .cpu_name = "7450", 853 .cpu_features = CPU_FTRS_7450_20, 854 .cpu_user_features = COMMON_USER | 855 PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 856 .mmu_features = MMU_FTR_HPTE_TABLE, 857 .icache_bsize = 32, 858 .dcache_bsize = 32, 859 .num_pmcs = 6, 860 .pmc_type = PPC_PMC_G4, 861 .cpu_setup = __setup_cpu_745x, 862 .machine_check = machine_check_generic, 863 .platform = "ppc7450", 864 }, 865 { /* 7450 2.1 */ 866 .pvr_mask = 0xffffffff, 867 .pvr_value = 0x80000201, 868 .cpu_name = "7450", 869 .cpu_features = CPU_FTRS_7450_21, 870 .cpu_user_features = COMMON_USER | 871 PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 872 .mmu_features = MMU_FTR_HPTE_TABLE, 873 .icache_bsize = 32, 874 .dcache_bsize = 32, 875 .num_pmcs = 6, 876 .pmc_type = PPC_PMC_G4, 877 .cpu_setup = __setup_cpu_745x, 878 .machine_check = machine_check_generic, 879 .platform = "ppc7450", 880 }, 881 { /* 7450 2.3 and newer */ 882 .pvr_mask = 0xffff0000, 883 .pvr_value = 0x80000000, 884 .cpu_name = "7450", 885 .cpu_features = CPU_FTRS_7450_23, 886 .cpu_user_features = COMMON_USER | 887 PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 888 .mmu_features = MMU_FTR_HPTE_TABLE, 889 .icache_bsize = 32, 890 .dcache_bsize = 32, 891 .num_pmcs = 6, 892 .pmc_type = PPC_PMC_G4, 893 .cpu_setup = __setup_cpu_745x, 894 .machine_check = machine_check_generic, 895 .platform = "ppc7450", 896 }, 897 { /* 7455 rev 1.x */ 898 .pvr_mask = 0xffffff00, 899 .pvr_value = 0x80010100, 900 .cpu_name = "7455", 901 .cpu_features = CPU_FTRS_7455_1, 902 .cpu_user_features = COMMON_USER | 903 PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 904 .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 905 .icache_bsize = 32, 906 .dcache_bsize = 32, 907 .num_pmcs = 6, 908 .pmc_type = PPC_PMC_G4, 909 .cpu_setup = __setup_cpu_745x, 910 .machine_check = machine_check_generic, 911 .platform = "ppc7450", 912 }, 913 { /* 7455 rev 2.0 */ 914 .pvr_mask = 0xffffffff, 915 .pvr_value = 0x80010200, 916 .cpu_name = "7455", 917 .cpu_features = CPU_FTRS_7455_20, 918 .cpu_user_features = COMMON_USER | 919 PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 920 .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 921 .icache_bsize = 32, 922 .dcache_bsize = 32, 923 .num_pmcs = 6, 924 .pmc_type = PPC_PMC_G4, 925 .cpu_setup = __setup_cpu_745x, 926 .machine_check = machine_check_generic, 927 .platform = "ppc7450", 928 }, 929 { /* 7455 others */ 930 .pvr_mask = 0xffff0000, 931 .pvr_value = 0x80010000, 932 .cpu_name = "7455", 933 .cpu_features = CPU_FTRS_7455, 934 .cpu_user_features = COMMON_USER | 935 PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 936 .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 937 .icache_bsize = 32, 938 .dcache_bsize = 32, 939 .num_pmcs = 6, 940 .pmc_type = PPC_PMC_G4, 941 .cpu_setup = __setup_cpu_745x, 942 .machine_check = machine_check_generic, 943 .platform = "ppc7450", 944 }, 945 { /* 7447/7457 Rev 1.0 */ 946 .pvr_mask = 0xffffffff, 947 .pvr_value = 0x80020100, 948 .cpu_name = "7447/7457", 949 .cpu_features = CPU_FTRS_7447_10, 950 .cpu_user_features = COMMON_USER | 951 PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 952 .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 953 .icache_bsize = 32, 954 .dcache_bsize = 32, 955 .num_pmcs = 6, 956 .pmc_type = PPC_PMC_G4, 957 .cpu_setup = __setup_cpu_745x, 958 .machine_check = machine_check_generic, 959 .platform = "ppc7450", 960 }, 961 { /* 7447/7457 Rev 1.1 */ 962 .pvr_mask = 0xffffffff, 963 .pvr_value = 0x80020101, 964 .cpu_name = "7447/7457", 965 .cpu_features = CPU_FTRS_7447_10, 966 .cpu_user_features = COMMON_USER | 967 PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 968 .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 969 .icache_bsize = 32, 970 .dcache_bsize = 32, 971 .num_pmcs = 6, 972 .pmc_type = PPC_PMC_G4, 973 .cpu_setup = __setup_cpu_745x, 974 .machine_check = machine_check_generic, 975 .platform = "ppc7450", 976 }, 977 { /* 7447/7457 Rev 1.2 and later */ 978 .pvr_mask = 0xffff0000, 979 .pvr_value = 0x80020000, 980 .cpu_name = "7447/7457", 981 .cpu_features = CPU_FTRS_7447, 982 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 983 .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 984 .icache_bsize = 32, 985 .dcache_bsize = 32, 986 .num_pmcs = 6, 987 .pmc_type = PPC_PMC_G4, 988 .cpu_setup = __setup_cpu_745x, 989 .machine_check = machine_check_generic, 990 .platform = "ppc7450", 991 }, 992 { /* 7447A */ 993 .pvr_mask = 0xffff0000, 994 .pvr_value = 0x80030000, 995 .cpu_name = "7447A", 996 .cpu_features = CPU_FTRS_7447A, 997 .cpu_user_features = COMMON_USER | 998 PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 999 .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 1000 .icache_bsize = 32, 1001 .dcache_bsize = 32, 1002 .num_pmcs = 6, 1003 .pmc_type = PPC_PMC_G4, 1004 .cpu_setup = __setup_cpu_745x, 1005 .machine_check = machine_check_generic, 1006 .platform = "ppc7450", 1007 }, 1008 { /* 7448 */ 1009 .pvr_mask = 0xffff0000, 1010 .pvr_value = 0x80040000, 1011 .cpu_name = "7448", 1012 .cpu_features = CPU_FTRS_7448, 1013 .cpu_user_features = COMMON_USER | 1014 PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 1015 .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 1016 .icache_bsize = 32, 1017 .dcache_bsize = 32, 1018 .num_pmcs = 6, 1019 .pmc_type = PPC_PMC_G4, 1020 .cpu_setup = __setup_cpu_745x, 1021 .machine_check = machine_check_generic, 1022 .platform = "ppc7450", 1023 }, 1024 #endif /* CONFIG_PPC_BOOK3S_604 */ 1025 #ifdef CONFIG_PPC_BOOK3S_603 1026 { /* 603 */ 1027 .pvr_mask = 0xffff0000, 1028 .pvr_value = 0x00030000, 1029 .cpu_name = "603", 1030 .cpu_features = CPU_FTRS_603, 1031 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 1032 .mmu_features = 0, 1033 .icache_bsize = 32, 1034 .dcache_bsize = 32, 1035 .cpu_setup = __setup_cpu_603, 1036 .machine_check = machine_check_generic, 1037 .platform = "ppc603", 1038 }, 1039 { /* 603e */ 1040 .pvr_mask = 0xffff0000, 1041 .pvr_value = 0x00060000, 1042 .cpu_name = "603e", 1043 .cpu_features = CPU_FTRS_603, 1044 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 1045 .mmu_features = 0, 1046 .icache_bsize = 32, 1047 .dcache_bsize = 32, 1048 .cpu_setup = __setup_cpu_603, 1049 .machine_check = machine_check_generic, 1050 .platform = "ppc603", 1051 }, 1052 { /* 603ev */ 1053 .pvr_mask = 0xffff0000, 1054 .pvr_value = 0x00070000, 1055 .cpu_name = "603ev", 1056 .cpu_features = CPU_FTRS_603, 1057 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 1058 .mmu_features = 0, 1059 .icache_bsize = 32, 1060 .dcache_bsize = 32, 1061 .cpu_setup = __setup_cpu_603, 1062 .machine_check = machine_check_generic, 1063 .platform = "ppc603", 1064 }, 1065 { /* 82xx (8240, 8245, 8260 are all 603e cores) */ 1066 .pvr_mask = 0x7fff0000, 1067 .pvr_value = 0x00810000, 1068 .cpu_name = "82xx", 1069 .cpu_features = CPU_FTRS_82XX, 1070 .cpu_user_features = COMMON_USER, 1071 .mmu_features = 0, 1072 .icache_bsize = 32, 1073 .dcache_bsize = 32, 1074 .cpu_setup = __setup_cpu_603, 1075 .machine_check = machine_check_generic, 1076 .platform = "ppc603", 1077 }, 1078 { /* All G2_LE (603e core, plus some) have the same pvr */ 1079 .pvr_mask = 0x7fff0000, 1080 .pvr_value = 0x00820000, 1081 .cpu_name = "G2_LE", 1082 .cpu_features = CPU_FTRS_G2_LE, 1083 .cpu_user_features = COMMON_USER, 1084 .mmu_features = MMU_FTR_USE_HIGH_BATS, 1085 .icache_bsize = 32, 1086 .dcache_bsize = 32, 1087 .cpu_setup = __setup_cpu_603, 1088 .machine_check = machine_check_generic, 1089 .platform = "ppc603", 1090 }, 1091 #ifdef CONFIG_PPC_83xx 1092 { /* e300c1 (a 603e core, plus some) on 83xx */ 1093 .pvr_mask = 0x7fff0000, 1094 .pvr_value = 0x00830000, 1095 .cpu_name = "e300c1", 1096 .cpu_features = CPU_FTRS_E300, 1097 .cpu_user_features = COMMON_USER, 1098 .mmu_features = MMU_FTR_USE_HIGH_BATS, 1099 .icache_bsize = 32, 1100 .dcache_bsize = 32, 1101 .cpu_setup = __setup_cpu_603, 1102 .machine_check = machine_check_83xx, 1103 .platform = "ppc603", 1104 }, 1105 { /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */ 1106 .pvr_mask = 0x7fff0000, 1107 .pvr_value = 0x00840000, 1108 .cpu_name = "e300c2", 1109 .cpu_features = CPU_FTRS_E300C2, 1110 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 1111 .mmu_features = MMU_FTR_USE_HIGH_BATS | 1112 MMU_FTR_NEED_DTLB_SW_LRU, 1113 .icache_bsize = 32, 1114 .dcache_bsize = 32, 1115 .cpu_setup = __setup_cpu_603, 1116 .machine_check = machine_check_83xx, 1117 .platform = "ppc603", 1118 }, 1119 { /* e300c3 (e300c1, plus one IU, half cache size) on 83xx */ 1120 .pvr_mask = 0x7fff0000, 1121 .pvr_value = 0x00850000, 1122 .cpu_name = "e300c3", 1123 .cpu_features = CPU_FTRS_E300, 1124 .cpu_user_features = COMMON_USER, 1125 .mmu_features = MMU_FTR_USE_HIGH_BATS | 1126 MMU_FTR_NEED_DTLB_SW_LRU, 1127 .icache_bsize = 32, 1128 .dcache_bsize = 32, 1129 .cpu_setup = __setup_cpu_603, 1130 .machine_check = machine_check_83xx, 1131 .num_pmcs = 4, 1132 .platform = "ppc603", 1133 }, 1134 { /* e300c4 (e300c1, plus one IU) */ 1135 .pvr_mask = 0x7fff0000, 1136 .pvr_value = 0x00860000, 1137 .cpu_name = "e300c4", 1138 .cpu_features = CPU_FTRS_E300, 1139 .cpu_user_features = COMMON_USER, 1140 .mmu_features = MMU_FTR_USE_HIGH_BATS | 1141 MMU_FTR_NEED_DTLB_SW_LRU, 1142 .icache_bsize = 32, 1143 .dcache_bsize = 32, 1144 .cpu_setup = __setup_cpu_603, 1145 .machine_check = machine_check_83xx, 1146 .num_pmcs = 4, 1147 .platform = "ppc603", 1148 }, 1149 #endif 1150 #endif /* CONFIG_PPC_BOOK3S_603 */ 1151 #ifdef CONFIG_PPC_BOOK3S_604 1152 { /* default match, we assume split I/D cache & TB (non-601)... */ 1153 .pvr_mask = 0x00000000, 1154 .pvr_value = 0x00000000, 1155 .cpu_name = "(generic PPC)", 1156 .cpu_features = CPU_FTRS_CLASSIC32, 1157 .cpu_user_features = COMMON_USER, 1158 .mmu_features = MMU_FTR_HPTE_TABLE, 1159 .icache_bsize = 32, 1160 .dcache_bsize = 32, 1161 .machine_check = machine_check_generic, 1162 .platform = "ppc603", 1163 }, 1164 #endif /* CONFIG_PPC_BOOK3S_604 */ 1165 #endif /* CONFIG_PPC_BOOK3S_32 */ 1166 #ifdef CONFIG_PPC_8xx 1167 { /* 8xx */ 1168 .pvr_mask = 0xffff0000, 1169 .pvr_value = PVR_8xx, 1170 .cpu_name = "8xx", 1171 /* CPU_FTR_MAYBE_CAN_DOZE is possible, 1172 * if the 8xx code is there.... */ 1173 .cpu_features = CPU_FTRS_8XX, 1174 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 1175 .mmu_features = MMU_FTR_TYPE_8xx, 1176 .icache_bsize = 16, 1177 .dcache_bsize = 16, 1178 .machine_check = machine_check_8xx, 1179 .platform = "ppc823", 1180 }, 1181 #endif /* CONFIG_PPC_8xx */ 1182 #ifdef CONFIG_40x 1183 { /* STB 04xxx */ 1184 .pvr_mask = 0xffff0000, 1185 .pvr_value = 0x41810000, 1186 .cpu_name = "STB04xxx", 1187 .cpu_features = CPU_FTRS_40X, 1188 .cpu_user_features = PPC_FEATURE_32 | 1189 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1190 .mmu_features = MMU_FTR_TYPE_40x, 1191 .icache_bsize = 32, 1192 .dcache_bsize = 32, 1193 .machine_check = machine_check_4xx, 1194 .platform = "ppc405", 1195 }, 1196 { /* NP405L */ 1197 .pvr_mask = 0xffff0000, 1198 .pvr_value = 0x41610000, 1199 .cpu_name = "NP405L", 1200 .cpu_features = CPU_FTRS_40X, 1201 .cpu_user_features = PPC_FEATURE_32 | 1202 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1203 .mmu_features = MMU_FTR_TYPE_40x, 1204 .icache_bsize = 32, 1205 .dcache_bsize = 32, 1206 .machine_check = machine_check_4xx, 1207 .platform = "ppc405", 1208 }, 1209 { /* NP4GS3 */ 1210 .pvr_mask = 0xffff0000, 1211 .pvr_value = 0x40B10000, 1212 .cpu_name = "NP4GS3", 1213 .cpu_features = CPU_FTRS_40X, 1214 .cpu_user_features = PPC_FEATURE_32 | 1215 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1216 .mmu_features = MMU_FTR_TYPE_40x, 1217 .icache_bsize = 32, 1218 .dcache_bsize = 32, 1219 .machine_check = machine_check_4xx, 1220 .platform = "ppc405", 1221 }, 1222 { /* NP405H */ 1223 .pvr_mask = 0xffff0000, 1224 .pvr_value = 0x41410000, 1225 .cpu_name = "NP405H", 1226 .cpu_features = CPU_FTRS_40X, 1227 .cpu_user_features = PPC_FEATURE_32 | 1228 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1229 .mmu_features = MMU_FTR_TYPE_40x, 1230 .icache_bsize = 32, 1231 .dcache_bsize = 32, 1232 .machine_check = machine_check_4xx, 1233 .platform = "ppc405", 1234 }, 1235 { /* 405GPr */ 1236 .pvr_mask = 0xffff0000, 1237 .pvr_value = 0x50910000, 1238 .cpu_name = "405GPr", 1239 .cpu_features = CPU_FTRS_40X, 1240 .cpu_user_features = PPC_FEATURE_32 | 1241 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1242 .mmu_features = MMU_FTR_TYPE_40x, 1243 .icache_bsize = 32, 1244 .dcache_bsize = 32, 1245 .machine_check = machine_check_4xx, 1246 .platform = "ppc405", 1247 }, 1248 { /* STBx25xx */ 1249 .pvr_mask = 0xffff0000, 1250 .pvr_value = 0x51510000, 1251 .cpu_name = "STBx25xx", 1252 .cpu_features = CPU_FTRS_40X, 1253 .cpu_user_features = PPC_FEATURE_32 | 1254 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1255 .mmu_features = MMU_FTR_TYPE_40x, 1256 .icache_bsize = 32, 1257 .dcache_bsize = 32, 1258 .machine_check = machine_check_4xx, 1259 .platform = "ppc405", 1260 }, 1261 { /* 405LP */ 1262 .pvr_mask = 0xffff0000, 1263 .pvr_value = 0x41F10000, 1264 .cpu_name = "405LP", 1265 .cpu_features = CPU_FTRS_40X, 1266 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 1267 .mmu_features = MMU_FTR_TYPE_40x, 1268 .icache_bsize = 32, 1269 .dcache_bsize = 32, 1270 .machine_check = machine_check_4xx, 1271 .platform = "ppc405", 1272 }, 1273 { /* 405EP */ 1274 .pvr_mask = 0xffff0000, 1275 .pvr_value = 0x51210000, 1276 .cpu_name = "405EP", 1277 .cpu_features = CPU_FTRS_40X, 1278 .cpu_user_features = PPC_FEATURE_32 | 1279 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1280 .mmu_features = MMU_FTR_TYPE_40x, 1281 .icache_bsize = 32, 1282 .dcache_bsize = 32, 1283 .machine_check = machine_check_4xx, 1284 .platform = "ppc405", 1285 }, 1286 { /* 405EX Rev. A/B with Security */ 1287 .pvr_mask = 0xffff000f, 1288 .pvr_value = 0x12910007, 1289 .cpu_name = "405EX Rev. A/B", 1290 .cpu_features = CPU_FTRS_40X, 1291 .cpu_user_features = PPC_FEATURE_32 | 1292 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1293 .mmu_features = MMU_FTR_TYPE_40x, 1294 .icache_bsize = 32, 1295 .dcache_bsize = 32, 1296 .machine_check = machine_check_4xx, 1297 .platform = "ppc405", 1298 }, 1299 { /* 405EX Rev. C without Security */ 1300 .pvr_mask = 0xffff000f, 1301 .pvr_value = 0x1291000d, 1302 .cpu_name = "405EX Rev. C", 1303 .cpu_features = CPU_FTRS_40X, 1304 .cpu_user_features = PPC_FEATURE_32 | 1305 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1306 .mmu_features = MMU_FTR_TYPE_40x, 1307 .icache_bsize = 32, 1308 .dcache_bsize = 32, 1309 .machine_check = machine_check_4xx, 1310 .platform = "ppc405", 1311 }, 1312 { /* 405EX Rev. C with Security */ 1313 .pvr_mask = 0xffff000f, 1314 .pvr_value = 0x1291000f, 1315 .cpu_name = "405EX Rev. C", 1316 .cpu_features = CPU_FTRS_40X, 1317 .cpu_user_features = PPC_FEATURE_32 | 1318 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1319 .mmu_features = MMU_FTR_TYPE_40x, 1320 .icache_bsize = 32, 1321 .dcache_bsize = 32, 1322 .machine_check = machine_check_4xx, 1323 .platform = "ppc405", 1324 }, 1325 { /* 405EX Rev. D without Security */ 1326 .pvr_mask = 0xffff000f, 1327 .pvr_value = 0x12910003, 1328 .cpu_name = "405EX Rev. D", 1329 .cpu_features = CPU_FTRS_40X, 1330 .cpu_user_features = PPC_FEATURE_32 | 1331 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1332 .mmu_features = MMU_FTR_TYPE_40x, 1333 .icache_bsize = 32, 1334 .dcache_bsize = 32, 1335 .machine_check = machine_check_4xx, 1336 .platform = "ppc405", 1337 }, 1338 { /* 405EX Rev. D with Security */ 1339 .pvr_mask = 0xffff000f, 1340 .pvr_value = 0x12910005, 1341 .cpu_name = "405EX Rev. D", 1342 .cpu_features = CPU_FTRS_40X, 1343 .cpu_user_features = PPC_FEATURE_32 | 1344 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1345 .mmu_features = MMU_FTR_TYPE_40x, 1346 .icache_bsize = 32, 1347 .dcache_bsize = 32, 1348 .machine_check = machine_check_4xx, 1349 .platform = "ppc405", 1350 }, 1351 { /* 405EXr Rev. A/B without Security */ 1352 .pvr_mask = 0xffff000f, 1353 .pvr_value = 0x12910001, 1354 .cpu_name = "405EXr Rev. A/B", 1355 .cpu_features = CPU_FTRS_40X, 1356 .cpu_user_features = PPC_FEATURE_32 | 1357 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1358 .mmu_features = MMU_FTR_TYPE_40x, 1359 .icache_bsize = 32, 1360 .dcache_bsize = 32, 1361 .machine_check = machine_check_4xx, 1362 .platform = "ppc405", 1363 }, 1364 { /* 405EXr Rev. C without Security */ 1365 .pvr_mask = 0xffff000f, 1366 .pvr_value = 0x12910009, 1367 .cpu_name = "405EXr Rev. C", 1368 .cpu_features = CPU_FTRS_40X, 1369 .cpu_user_features = PPC_FEATURE_32 | 1370 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1371 .mmu_features = MMU_FTR_TYPE_40x, 1372 .icache_bsize = 32, 1373 .dcache_bsize = 32, 1374 .machine_check = machine_check_4xx, 1375 .platform = "ppc405", 1376 }, 1377 { /* 405EXr Rev. C with Security */ 1378 .pvr_mask = 0xffff000f, 1379 .pvr_value = 0x1291000b, 1380 .cpu_name = "405EXr Rev. C", 1381 .cpu_features = CPU_FTRS_40X, 1382 .cpu_user_features = PPC_FEATURE_32 | 1383 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1384 .mmu_features = MMU_FTR_TYPE_40x, 1385 .icache_bsize = 32, 1386 .dcache_bsize = 32, 1387 .machine_check = machine_check_4xx, 1388 .platform = "ppc405", 1389 }, 1390 { /* 405EXr Rev. D without Security */ 1391 .pvr_mask = 0xffff000f, 1392 .pvr_value = 0x12910000, 1393 .cpu_name = "405EXr Rev. D", 1394 .cpu_features = CPU_FTRS_40X, 1395 .cpu_user_features = PPC_FEATURE_32 | 1396 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1397 .mmu_features = MMU_FTR_TYPE_40x, 1398 .icache_bsize = 32, 1399 .dcache_bsize = 32, 1400 .machine_check = machine_check_4xx, 1401 .platform = "ppc405", 1402 }, 1403 { /* 405EXr Rev. D with Security */ 1404 .pvr_mask = 0xffff000f, 1405 .pvr_value = 0x12910002, 1406 .cpu_name = "405EXr Rev. D", 1407 .cpu_features = CPU_FTRS_40X, 1408 .cpu_user_features = PPC_FEATURE_32 | 1409 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1410 .mmu_features = MMU_FTR_TYPE_40x, 1411 .icache_bsize = 32, 1412 .dcache_bsize = 32, 1413 .machine_check = machine_check_4xx, 1414 .platform = "ppc405", 1415 }, 1416 { 1417 /* 405EZ */ 1418 .pvr_mask = 0xffff0000, 1419 .pvr_value = 0x41510000, 1420 .cpu_name = "405EZ", 1421 .cpu_features = CPU_FTRS_40X, 1422 .cpu_user_features = PPC_FEATURE_32 | 1423 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1424 .mmu_features = MMU_FTR_TYPE_40x, 1425 .icache_bsize = 32, 1426 .dcache_bsize = 32, 1427 .machine_check = machine_check_4xx, 1428 .platform = "ppc405", 1429 }, 1430 { /* APM8018X */ 1431 .pvr_mask = 0xffff0000, 1432 .pvr_value = 0x7ff11432, 1433 .cpu_name = "APM8018X", 1434 .cpu_features = CPU_FTRS_40X, 1435 .cpu_user_features = PPC_FEATURE_32 | 1436 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1437 .mmu_features = MMU_FTR_TYPE_40x, 1438 .icache_bsize = 32, 1439 .dcache_bsize = 32, 1440 .machine_check = machine_check_4xx, 1441 .platform = "ppc405", 1442 }, 1443 { /* default match */ 1444 .pvr_mask = 0x00000000, 1445 .pvr_value = 0x00000000, 1446 .cpu_name = "(generic 40x PPC)", 1447 .cpu_features = CPU_FTRS_40X, 1448 .cpu_user_features = PPC_FEATURE_32 | 1449 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1450 .mmu_features = MMU_FTR_TYPE_40x, 1451 .icache_bsize = 32, 1452 .dcache_bsize = 32, 1453 .machine_check = machine_check_4xx, 1454 .platform = "ppc405", 1455 } 1456 1457 #endif /* CONFIG_40x */ 1458 #ifdef CONFIG_44x 1459 #ifndef CONFIG_PPC_47x 1460 { 1461 .pvr_mask = 0xf0000fff, 1462 .pvr_value = 0x40000850, 1463 .cpu_name = "440GR Rev. A", 1464 .cpu_features = CPU_FTRS_44X, 1465 .cpu_user_features = COMMON_USER_BOOKE, 1466 .mmu_features = MMU_FTR_TYPE_44x, 1467 .icache_bsize = 32, 1468 .dcache_bsize = 32, 1469 .machine_check = machine_check_4xx, 1470 .platform = "ppc440", 1471 }, 1472 { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */ 1473 .pvr_mask = 0xf0000fff, 1474 .pvr_value = 0x40000858, 1475 .cpu_name = "440EP Rev. A", 1476 .cpu_features = CPU_FTRS_44X, 1477 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1478 .mmu_features = MMU_FTR_TYPE_44x, 1479 .icache_bsize = 32, 1480 .dcache_bsize = 32, 1481 .cpu_setup = __setup_cpu_440ep, 1482 .machine_check = machine_check_4xx, 1483 .platform = "ppc440", 1484 }, 1485 { 1486 .pvr_mask = 0xf0000fff, 1487 .pvr_value = 0x400008d3, 1488 .cpu_name = "440GR Rev. B", 1489 .cpu_features = CPU_FTRS_44X, 1490 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1491 .mmu_features = MMU_FTR_TYPE_44x, 1492 .icache_bsize = 32, 1493 .dcache_bsize = 32, 1494 .machine_check = machine_check_4xx, 1495 .platform = "ppc440", 1496 }, 1497 { /* Matches both physical and logical PVR for 440EP (logical pvr = pvr | 0x8) */ 1498 .pvr_mask = 0xf0000ff7, 1499 .pvr_value = 0x400008d4, 1500 .cpu_name = "440EP Rev. C", 1501 .cpu_features = CPU_FTRS_44X, 1502 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1503 .mmu_features = MMU_FTR_TYPE_44x, 1504 .icache_bsize = 32, 1505 .dcache_bsize = 32, 1506 .cpu_setup = __setup_cpu_440ep, 1507 .machine_check = machine_check_4xx, 1508 .platform = "ppc440", 1509 }, 1510 { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */ 1511 .pvr_mask = 0xf0000fff, 1512 .pvr_value = 0x400008db, 1513 .cpu_name = "440EP Rev. B", 1514 .cpu_features = CPU_FTRS_44X, 1515 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1516 .mmu_features = MMU_FTR_TYPE_44x, 1517 .icache_bsize = 32, 1518 .dcache_bsize = 32, 1519 .cpu_setup = __setup_cpu_440ep, 1520 .machine_check = machine_check_4xx, 1521 .platform = "ppc440", 1522 }, 1523 { /* 440GRX */ 1524 .pvr_mask = 0xf0000ffb, 1525 .pvr_value = 0x200008D0, 1526 .cpu_name = "440GRX", 1527 .cpu_features = CPU_FTRS_44X, 1528 .cpu_user_features = COMMON_USER_BOOKE, 1529 .mmu_features = MMU_FTR_TYPE_44x, 1530 .icache_bsize = 32, 1531 .dcache_bsize = 32, 1532 .cpu_setup = __setup_cpu_440grx, 1533 .machine_check = machine_check_440A, 1534 .platform = "ppc440", 1535 }, 1536 { /* Use logical PVR for 440EPx (logical pvr = pvr | 0x8) */ 1537 .pvr_mask = 0xf0000ffb, 1538 .pvr_value = 0x200008D8, 1539 .cpu_name = "440EPX", 1540 .cpu_features = CPU_FTRS_44X, 1541 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1542 .mmu_features = MMU_FTR_TYPE_44x, 1543 .icache_bsize = 32, 1544 .dcache_bsize = 32, 1545 .cpu_setup = __setup_cpu_440epx, 1546 .machine_check = machine_check_440A, 1547 .platform = "ppc440", 1548 }, 1549 { /* 440GP Rev. B */ 1550 .pvr_mask = 0xf0000fff, 1551 .pvr_value = 0x40000440, 1552 .cpu_name = "440GP Rev. B", 1553 .cpu_features = CPU_FTRS_44X, 1554 .cpu_user_features = COMMON_USER_BOOKE, 1555 .mmu_features = MMU_FTR_TYPE_44x, 1556 .icache_bsize = 32, 1557 .dcache_bsize = 32, 1558 .machine_check = machine_check_4xx, 1559 .platform = "ppc440gp", 1560 }, 1561 { /* 440GP Rev. C */ 1562 .pvr_mask = 0xf0000fff, 1563 .pvr_value = 0x40000481, 1564 .cpu_name = "440GP Rev. C", 1565 .cpu_features = CPU_FTRS_44X, 1566 .cpu_user_features = COMMON_USER_BOOKE, 1567 .mmu_features = MMU_FTR_TYPE_44x, 1568 .icache_bsize = 32, 1569 .dcache_bsize = 32, 1570 .machine_check = machine_check_4xx, 1571 .platform = "ppc440gp", 1572 }, 1573 { /* 440GX Rev. A */ 1574 .pvr_mask = 0xf0000fff, 1575 .pvr_value = 0x50000850, 1576 .cpu_name = "440GX Rev. A", 1577 .cpu_features = CPU_FTRS_44X, 1578 .cpu_user_features = COMMON_USER_BOOKE, 1579 .mmu_features = MMU_FTR_TYPE_44x, 1580 .icache_bsize = 32, 1581 .dcache_bsize = 32, 1582 .cpu_setup = __setup_cpu_440gx, 1583 .machine_check = machine_check_440A, 1584 .platform = "ppc440", 1585 }, 1586 { /* 440GX Rev. B */ 1587 .pvr_mask = 0xf0000fff, 1588 .pvr_value = 0x50000851, 1589 .cpu_name = "440GX Rev. B", 1590 .cpu_features = CPU_FTRS_44X, 1591 .cpu_user_features = COMMON_USER_BOOKE, 1592 .mmu_features = MMU_FTR_TYPE_44x, 1593 .icache_bsize = 32, 1594 .dcache_bsize = 32, 1595 .cpu_setup = __setup_cpu_440gx, 1596 .machine_check = machine_check_440A, 1597 .platform = "ppc440", 1598 }, 1599 { /* 440GX Rev. C */ 1600 .pvr_mask = 0xf0000fff, 1601 .pvr_value = 0x50000892, 1602 .cpu_name = "440GX Rev. C", 1603 .cpu_features = CPU_FTRS_44X, 1604 .cpu_user_features = COMMON_USER_BOOKE, 1605 .mmu_features = MMU_FTR_TYPE_44x, 1606 .icache_bsize = 32, 1607 .dcache_bsize = 32, 1608 .cpu_setup = __setup_cpu_440gx, 1609 .machine_check = machine_check_440A, 1610 .platform = "ppc440", 1611 }, 1612 { /* 440GX Rev. F */ 1613 .pvr_mask = 0xf0000fff, 1614 .pvr_value = 0x50000894, 1615 .cpu_name = "440GX Rev. F", 1616 .cpu_features = CPU_FTRS_44X, 1617 .cpu_user_features = COMMON_USER_BOOKE, 1618 .mmu_features = MMU_FTR_TYPE_44x, 1619 .icache_bsize = 32, 1620 .dcache_bsize = 32, 1621 .cpu_setup = __setup_cpu_440gx, 1622 .machine_check = machine_check_440A, 1623 .platform = "ppc440", 1624 }, 1625 { /* 440SP Rev. A */ 1626 .pvr_mask = 0xfff00fff, 1627 .pvr_value = 0x53200891, 1628 .cpu_name = "440SP Rev. A", 1629 .cpu_features = CPU_FTRS_44X, 1630 .cpu_user_features = COMMON_USER_BOOKE, 1631 .mmu_features = MMU_FTR_TYPE_44x, 1632 .icache_bsize = 32, 1633 .dcache_bsize = 32, 1634 .machine_check = machine_check_4xx, 1635 .platform = "ppc440", 1636 }, 1637 { /* 440SPe Rev. A */ 1638 .pvr_mask = 0xfff00fff, 1639 .pvr_value = 0x53400890, 1640 .cpu_name = "440SPe Rev. A", 1641 .cpu_features = CPU_FTRS_44X, 1642 .cpu_user_features = COMMON_USER_BOOKE, 1643 .mmu_features = MMU_FTR_TYPE_44x, 1644 .icache_bsize = 32, 1645 .dcache_bsize = 32, 1646 .cpu_setup = __setup_cpu_440spe, 1647 .machine_check = machine_check_440A, 1648 .platform = "ppc440", 1649 }, 1650 { /* 440SPe Rev. B */ 1651 .pvr_mask = 0xfff00fff, 1652 .pvr_value = 0x53400891, 1653 .cpu_name = "440SPe Rev. B", 1654 .cpu_features = CPU_FTRS_44X, 1655 .cpu_user_features = COMMON_USER_BOOKE, 1656 .mmu_features = MMU_FTR_TYPE_44x, 1657 .icache_bsize = 32, 1658 .dcache_bsize = 32, 1659 .cpu_setup = __setup_cpu_440spe, 1660 .machine_check = machine_check_440A, 1661 .platform = "ppc440", 1662 }, 1663 { /* 460EX */ 1664 .pvr_mask = 0xffff0006, 1665 .pvr_value = 0x13020002, 1666 .cpu_name = "460EX", 1667 .cpu_features = CPU_FTRS_440x6, 1668 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1669 .mmu_features = MMU_FTR_TYPE_44x, 1670 .icache_bsize = 32, 1671 .dcache_bsize = 32, 1672 .cpu_setup = __setup_cpu_460ex, 1673 .machine_check = machine_check_440A, 1674 .platform = "ppc440", 1675 }, 1676 { /* 460EX Rev B */ 1677 .pvr_mask = 0xffff0007, 1678 .pvr_value = 0x13020004, 1679 .cpu_name = "460EX Rev. B", 1680 .cpu_features = CPU_FTRS_440x6, 1681 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1682 .mmu_features = MMU_FTR_TYPE_44x, 1683 .icache_bsize = 32, 1684 .dcache_bsize = 32, 1685 .cpu_setup = __setup_cpu_460ex, 1686 .machine_check = machine_check_440A, 1687 .platform = "ppc440", 1688 }, 1689 { /* 460GT */ 1690 .pvr_mask = 0xffff0006, 1691 .pvr_value = 0x13020000, 1692 .cpu_name = "460GT", 1693 .cpu_features = CPU_FTRS_440x6, 1694 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1695 .mmu_features = MMU_FTR_TYPE_44x, 1696 .icache_bsize = 32, 1697 .dcache_bsize = 32, 1698 .cpu_setup = __setup_cpu_460gt, 1699 .machine_check = machine_check_440A, 1700 .platform = "ppc440", 1701 }, 1702 { /* 460GT Rev B */ 1703 .pvr_mask = 0xffff0007, 1704 .pvr_value = 0x13020005, 1705 .cpu_name = "460GT Rev. B", 1706 .cpu_features = CPU_FTRS_440x6, 1707 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1708 .mmu_features = MMU_FTR_TYPE_44x, 1709 .icache_bsize = 32, 1710 .dcache_bsize = 32, 1711 .cpu_setup = __setup_cpu_460gt, 1712 .machine_check = machine_check_440A, 1713 .platform = "ppc440", 1714 }, 1715 { /* 460SX */ 1716 .pvr_mask = 0xffffff00, 1717 .pvr_value = 0x13541800, 1718 .cpu_name = "460SX", 1719 .cpu_features = CPU_FTRS_44X, 1720 .cpu_user_features = COMMON_USER_BOOKE, 1721 .mmu_features = MMU_FTR_TYPE_44x, 1722 .icache_bsize = 32, 1723 .dcache_bsize = 32, 1724 .cpu_setup = __setup_cpu_460sx, 1725 .machine_check = machine_check_440A, 1726 .platform = "ppc440", 1727 }, 1728 { /* 464 in APM821xx */ 1729 .pvr_mask = 0xfffffff0, 1730 .pvr_value = 0x12C41C80, 1731 .cpu_name = "APM821XX", 1732 .cpu_features = CPU_FTRS_44X, 1733 .cpu_user_features = COMMON_USER_BOOKE | 1734 PPC_FEATURE_HAS_FPU, 1735 .mmu_features = MMU_FTR_TYPE_44x, 1736 .icache_bsize = 32, 1737 .dcache_bsize = 32, 1738 .cpu_setup = __setup_cpu_apm821xx, 1739 .machine_check = machine_check_440A, 1740 .platform = "ppc440", 1741 }, 1742 { /* default match */ 1743 .pvr_mask = 0x00000000, 1744 .pvr_value = 0x00000000, 1745 .cpu_name = "(generic 44x PPC)", 1746 .cpu_features = CPU_FTRS_44X, 1747 .cpu_user_features = COMMON_USER_BOOKE, 1748 .mmu_features = MMU_FTR_TYPE_44x, 1749 .icache_bsize = 32, 1750 .dcache_bsize = 32, 1751 .machine_check = machine_check_4xx, 1752 .platform = "ppc440", 1753 } 1754 #else /* CONFIG_PPC_47x */ 1755 { /* 476 DD2 core */ 1756 .pvr_mask = 0xffffffff, 1757 .pvr_value = 0x11a52080, 1758 .cpu_name = "476", 1759 .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD2, 1760 .cpu_user_features = COMMON_USER_BOOKE | 1761 PPC_FEATURE_HAS_FPU, 1762 .mmu_features = MMU_FTR_TYPE_47x | 1763 MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL, 1764 .icache_bsize = 32, 1765 .dcache_bsize = 128, 1766 .machine_check = machine_check_47x, 1767 .platform = "ppc470", 1768 }, 1769 { /* 476fpe */ 1770 .pvr_mask = 0xffff0000, 1771 .pvr_value = 0x7ff50000, 1772 .cpu_name = "476fpe", 1773 .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD2, 1774 .cpu_user_features = COMMON_USER_BOOKE | 1775 PPC_FEATURE_HAS_FPU, 1776 .mmu_features = MMU_FTR_TYPE_47x | 1777 MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL, 1778 .icache_bsize = 32, 1779 .dcache_bsize = 128, 1780 .machine_check = machine_check_47x, 1781 .platform = "ppc470", 1782 }, 1783 { /* 476 iss */ 1784 .pvr_mask = 0xffff0000, 1785 .pvr_value = 0x00050000, 1786 .cpu_name = "476", 1787 .cpu_features = CPU_FTRS_47X, 1788 .cpu_user_features = COMMON_USER_BOOKE | 1789 PPC_FEATURE_HAS_FPU, 1790 .mmu_features = MMU_FTR_TYPE_47x | 1791 MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL, 1792 .icache_bsize = 32, 1793 .dcache_bsize = 128, 1794 .machine_check = machine_check_47x, 1795 .platform = "ppc470", 1796 }, 1797 { /* 476 others */ 1798 .pvr_mask = 0xffff0000, 1799 .pvr_value = 0x11a50000, 1800 .cpu_name = "476", 1801 .cpu_features = CPU_FTRS_47X, 1802 .cpu_user_features = COMMON_USER_BOOKE | 1803 PPC_FEATURE_HAS_FPU, 1804 .mmu_features = MMU_FTR_TYPE_47x | 1805 MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL, 1806 .icache_bsize = 32, 1807 .dcache_bsize = 128, 1808 .machine_check = machine_check_47x, 1809 .platform = "ppc470", 1810 }, 1811 { /* default match */ 1812 .pvr_mask = 0x00000000, 1813 .pvr_value = 0x00000000, 1814 .cpu_name = "(generic 47x PPC)", 1815 .cpu_features = CPU_FTRS_47X, 1816 .cpu_user_features = COMMON_USER_BOOKE, 1817 .mmu_features = MMU_FTR_TYPE_47x, 1818 .icache_bsize = 32, 1819 .dcache_bsize = 128, 1820 .machine_check = machine_check_47x, 1821 .platform = "ppc470", 1822 } 1823 #endif /* CONFIG_PPC_47x */ 1824 #endif /* CONFIG_44x */ 1825 #endif /* CONFIG_PPC32 */ 1826 #ifdef CONFIG_E500 1827 #ifdef CONFIG_PPC32 1828 #ifndef CONFIG_PPC_E500MC 1829 { /* e500 */ 1830 .pvr_mask = 0xffff0000, 1831 .pvr_value = 0x80200000, 1832 .cpu_name = "e500", 1833 .cpu_features = CPU_FTRS_E500, 1834 .cpu_user_features = COMMON_USER_BOOKE | 1835 PPC_FEATURE_HAS_SPE_COMP | 1836 PPC_FEATURE_HAS_EFP_SINGLE_COMP, 1837 .cpu_user_features2 = PPC_FEATURE2_ISEL, 1838 .mmu_features = MMU_FTR_TYPE_FSL_E, 1839 .icache_bsize = 32, 1840 .dcache_bsize = 32, 1841 .num_pmcs = 4, 1842 .cpu_setup = __setup_cpu_e500v1, 1843 .machine_check = machine_check_e500, 1844 .platform = "ppc8540", 1845 }, 1846 { /* e500v2 */ 1847 .pvr_mask = 0xffff0000, 1848 .pvr_value = 0x80210000, 1849 .cpu_name = "e500v2", 1850 .cpu_features = CPU_FTRS_E500_2, 1851 .cpu_user_features = COMMON_USER_BOOKE | 1852 PPC_FEATURE_HAS_SPE_COMP | 1853 PPC_FEATURE_HAS_EFP_SINGLE_COMP | 1854 PPC_FEATURE_HAS_EFP_DOUBLE_COMP, 1855 .cpu_user_features2 = PPC_FEATURE2_ISEL, 1856 .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS, 1857 .icache_bsize = 32, 1858 .dcache_bsize = 32, 1859 .num_pmcs = 4, 1860 .cpu_setup = __setup_cpu_e500v2, 1861 .machine_check = machine_check_e500, 1862 .platform = "ppc8548", 1863 .cpu_down_flush = cpu_down_flush_e500v2, 1864 }, 1865 #else 1866 { /* e500mc */ 1867 .pvr_mask = 0xffff0000, 1868 .pvr_value = 0x80230000, 1869 .cpu_name = "e500mc", 1870 .cpu_features = CPU_FTRS_E500MC, 1871 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1872 .cpu_user_features2 = PPC_FEATURE2_ISEL, 1873 .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | 1874 MMU_FTR_USE_TLBILX, 1875 .icache_bsize = 64, 1876 .dcache_bsize = 64, 1877 .num_pmcs = 4, 1878 .cpu_setup = __setup_cpu_e500mc, 1879 .machine_check = machine_check_e500mc, 1880 .platform = "ppce500mc", 1881 .cpu_down_flush = cpu_down_flush_e500mc, 1882 }, 1883 #endif /* CONFIG_PPC_E500MC */ 1884 #endif /* CONFIG_PPC32 */ 1885 #ifdef CONFIG_PPC_E500MC 1886 { /* e5500 */ 1887 .pvr_mask = 0xffff0000, 1888 .pvr_value = 0x80240000, 1889 .cpu_name = "e5500", 1890 .cpu_features = CPU_FTRS_E5500, 1891 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1892 .cpu_user_features2 = PPC_FEATURE2_ISEL, 1893 .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | 1894 MMU_FTR_USE_TLBILX, 1895 .icache_bsize = 64, 1896 .dcache_bsize = 64, 1897 .num_pmcs = 4, 1898 .cpu_setup = __setup_cpu_e5500, 1899 #ifndef CONFIG_PPC32 1900 .cpu_restore = __restore_cpu_e5500, 1901 #endif 1902 .machine_check = machine_check_e500mc, 1903 .platform = "ppce5500", 1904 .cpu_down_flush = cpu_down_flush_e5500, 1905 }, 1906 { /* e6500 */ 1907 .pvr_mask = 0xffff0000, 1908 .pvr_value = 0x80400000, 1909 .cpu_name = "e6500", 1910 .cpu_features = CPU_FTRS_E6500, 1911 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU | 1912 PPC_FEATURE_HAS_ALTIVEC_COMP, 1913 .cpu_user_features2 = PPC_FEATURE2_ISEL, 1914 .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | 1915 MMU_FTR_USE_TLBILX, 1916 .icache_bsize = 64, 1917 .dcache_bsize = 64, 1918 .num_pmcs = 6, 1919 .cpu_setup = __setup_cpu_e6500, 1920 #ifndef CONFIG_PPC32 1921 .cpu_restore = __restore_cpu_e6500, 1922 #endif 1923 .machine_check = machine_check_e500mc, 1924 .platform = "ppce6500", 1925 .cpu_down_flush = cpu_down_flush_e6500, 1926 }, 1927 #endif /* CONFIG_PPC_E500MC */ 1928 #ifdef CONFIG_PPC32 1929 { /* default match */ 1930 .pvr_mask = 0x00000000, 1931 .pvr_value = 0x00000000, 1932 .cpu_name = "(generic E500 PPC)", 1933 .cpu_features = CPU_FTRS_E500, 1934 .cpu_user_features = COMMON_USER_BOOKE | 1935 PPC_FEATURE_HAS_SPE_COMP | 1936 PPC_FEATURE_HAS_EFP_SINGLE_COMP, 1937 .mmu_features = MMU_FTR_TYPE_FSL_E, 1938 .icache_bsize = 32, 1939 .dcache_bsize = 32, 1940 .machine_check = machine_check_e500, 1941 .platform = "powerpc", 1942 } 1943 #endif /* CONFIG_PPC32 */ 1944 #endif /* CONFIG_E500 */ 1945 }; 1946 1947 void __init set_cur_cpu_spec(struct cpu_spec *s) 1948 { 1949 struct cpu_spec *t = &the_cpu_spec; 1950 1951 t = PTRRELOC(t); 1952 /* 1953 * use memcpy() instead of *t = *s so that GCC replaces it 1954 * by __memcpy() when KASAN is active 1955 */ 1956 memcpy(t, s, sizeof(*t)); 1957 1958 *PTRRELOC(&cur_cpu_spec) = &the_cpu_spec; 1959 } 1960 1961 static struct cpu_spec * __init setup_cpu_spec(unsigned long offset, 1962 struct cpu_spec *s) 1963 { 1964 struct cpu_spec *t = &the_cpu_spec; 1965 struct cpu_spec old; 1966 1967 t = PTRRELOC(t); 1968 old = *t; 1969 1970 /* 1971 * Copy everything, then do fixups. Use memcpy() instead of *t = *s 1972 * so that GCC replaces it by __memcpy() when KASAN is active 1973 */ 1974 memcpy(t, s, sizeof(*t)); 1975 1976 /* 1977 * If we are overriding a previous value derived from the real 1978 * PVR with a new value obtained using a logical PVR value, 1979 * don't modify the performance monitor fields. 1980 */ 1981 if (old.num_pmcs && !s->num_pmcs) { 1982 t->num_pmcs = old.num_pmcs; 1983 t->pmc_type = old.pmc_type; 1984 1985 /* 1986 * Let's ensure that the 1987 * fix for the PMAO bug is enabled on compatibility mode. 1988 */ 1989 t->cpu_features |= old.cpu_features & CPU_FTR_PMAO_BUG; 1990 } 1991 1992 *PTRRELOC(&cur_cpu_spec) = &the_cpu_spec; 1993 1994 /* 1995 * Set the base platform string once; assumes 1996 * we're called with real pvr first. 1997 */ 1998 if (*PTRRELOC(&powerpc_base_platform) == NULL) 1999 *PTRRELOC(&powerpc_base_platform) = t->platform; 2000 2001 #if defined(CONFIG_PPC64) || defined(CONFIG_BOOKE) 2002 /* ppc64 and booke expect identify_cpu to also call setup_cpu for 2003 * that processor. I will consolidate that at a later time, for now, 2004 * just use #ifdef. We also don't need to PTRRELOC the function 2005 * pointer on ppc64 and booke as we are running at 0 in real mode 2006 * on ppc64 and reloc_offset is always 0 on booke. 2007 */ 2008 if (t->cpu_setup) { 2009 t->cpu_setup(offset, t); 2010 } 2011 #endif /* CONFIG_PPC64 || CONFIG_BOOKE */ 2012 2013 return t; 2014 } 2015 2016 struct cpu_spec * __init identify_cpu(unsigned long offset, unsigned int pvr) 2017 { 2018 struct cpu_spec *s = cpu_specs; 2019 int i; 2020 2021 s = PTRRELOC(s); 2022 2023 for (i = 0; i < ARRAY_SIZE(cpu_specs); i++,s++) { 2024 if ((pvr & s->pvr_mask) == s->pvr_value) 2025 return setup_cpu_spec(offset, s); 2026 } 2027 2028 BUG(); 2029 2030 return NULL; 2031 } 2032 2033 /* 2034 * Used by cpufeatures to get the name for CPUs with a PVR table. 2035 * If they don't hae a PVR table, cpufeatures gets the name from 2036 * cpu device-tree node. 2037 */ 2038 void __init identify_cpu_name(unsigned int pvr) 2039 { 2040 struct cpu_spec *s = cpu_specs; 2041 struct cpu_spec *t = &the_cpu_spec; 2042 int i; 2043 2044 s = PTRRELOC(s); 2045 t = PTRRELOC(t); 2046 2047 for (i = 0; i < ARRAY_SIZE(cpu_specs); i++,s++) { 2048 if ((pvr & s->pvr_mask) == s->pvr_value) { 2049 t->cpu_name = s->cpu_name; 2050 return; 2051 } 2052 } 2053 } 2054 2055 2056 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS 2057 struct static_key_true cpu_feature_keys[NUM_CPU_FTR_KEYS] = { 2058 [0 ... NUM_CPU_FTR_KEYS - 1] = STATIC_KEY_TRUE_INIT 2059 }; 2060 EXPORT_SYMBOL_GPL(cpu_feature_keys); 2061 2062 void __init cpu_feature_keys_init(void) 2063 { 2064 int i; 2065 2066 for (i = 0; i < NUM_CPU_FTR_KEYS; i++) { 2067 unsigned long f = 1ul << i; 2068 2069 if (!(cur_cpu_spec->cpu_features & f)) 2070 static_branch_disable(&cpu_feature_keys[i]); 2071 } 2072 } 2073 2074 struct static_key_true mmu_feature_keys[NUM_MMU_FTR_KEYS] = { 2075 [0 ... NUM_MMU_FTR_KEYS - 1] = STATIC_KEY_TRUE_INIT 2076 }; 2077 EXPORT_SYMBOL(mmu_feature_keys); 2078 2079 void __init mmu_feature_keys_init(void) 2080 { 2081 int i; 2082 2083 for (i = 0; i < NUM_MMU_FTR_KEYS; i++) { 2084 unsigned long f = 1ul << i; 2085 2086 if (!(cur_cpu_spec->mmu_features & f)) 2087 static_branch_disable(&mmu_feature_keys[i]); 2088 } 2089 } 2090 #endif 2091