1 /* 2 * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org) 3 * 4 * Modifications for ppc64: 5 * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13 #include <linux/string.h> 14 #include <linux/sched.h> 15 #include <linux/threads.h> 16 #include <linux/init.h> 17 #include <linux/export.h> 18 19 #include <asm/oprofile_impl.h> 20 #include <asm/cputable.h> 21 #include <asm/prom.h> /* for PTRRELOC on ARCH=ppc */ 22 #include <asm/mmu.h> 23 #include <asm/setup.h> 24 25 struct cpu_spec* cur_cpu_spec = NULL; 26 EXPORT_SYMBOL(cur_cpu_spec); 27 28 /* The platform string corresponding to the real PVR */ 29 const char *powerpc_base_platform; 30 31 /* NOTE: 32 * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's 33 * the responsibility of the appropriate CPU save/restore functions to 34 * eventually copy these settings over. Those save/restore aren't yet 35 * part of the cputable though. That has to be fixed for both ppc32 36 * and ppc64 37 */ 38 #ifdef CONFIG_PPC32 39 extern void __setup_cpu_e200(unsigned long offset, struct cpu_spec* spec); 40 extern void __setup_cpu_e500v1(unsigned long offset, struct cpu_spec* spec); 41 extern void __setup_cpu_e500v2(unsigned long offset, struct cpu_spec* spec); 42 extern void __setup_cpu_e500mc(unsigned long offset, struct cpu_spec* spec); 43 extern void __setup_cpu_440ep(unsigned long offset, struct cpu_spec* spec); 44 extern void __setup_cpu_440epx(unsigned long offset, struct cpu_spec* spec); 45 extern void __setup_cpu_440gx(unsigned long offset, struct cpu_spec* spec); 46 extern void __setup_cpu_440grx(unsigned long offset, struct cpu_spec* spec); 47 extern void __setup_cpu_440spe(unsigned long offset, struct cpu_spec* spec); 48 extern void __setup_cpu_440x5(unsigned long offset, struct cpu_spec* spec); 49 extern void __setup_cpu_460ex(unsigned long offset, struct cpu_spec* spec); 50 extern void __setup_cpu_460gt(unsigned long offset, struct cpu_spec* spec); 51 extern void __setup_cpu_460sx(unsigned long offset, struct cpu_spec *spec); 52 extern void __setup_cpu_apm821xx(unsigned long offset, struct cpu_spec *spec); 53 extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec); 54 extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec); 55 extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec); 56 extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec); 57 extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec); 58 extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec); 59 extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec); 60 extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec); 61 #endif /* CONFIG_PPC32 */ 62 #ifdef CONFIG_PPC64 63 extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec); 64 extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec); 65 extern void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec* spec); 66 extern void __setup_cpu_a2(unsigned long offset, struct cpu_spec* spec); 67 extern void __restore_cpu_pa6t(void); 68 extern void __restore_cpu_ppc970(void); 69 extern void __setup_cpu_power7(unsigned long offset, struct cpu_spec* spec); 70 extern void __restore_cpu_power7(void); 71 extern void __setup_cpu_power8(unsigned long offset, struct cpu_spec* spec); 72 extern void __restore_cpu_power8(void); 73 extern void __restore_cpu_a2(void); 74 extern void __flush_tlb_power7(unsigned long inval_selector); 75 extern void __flush_tlb_power8(unsigned long inval_selector); 76 extern long __machine_check_early_realmode_p7(struct pt_regs *regs); 77 extern long __machine_check_early_realmode_p8(struct pt_regs *regs); 78 #endif /* CONFIG_PPC64 */ 79 #if defined(CONFIG_E500) 80 extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec); 81 extern void __setup_cpu_e6500(unsigned long offset, struct cpu_spec* spec); 82 extern void __restore_cpu_e5500(void); 83 extern void __restore_cpu_e6500(void); 84 #endif /* CONFIG_E500 */ 85 86 /* This table only contains "desktop" CPUs, it need to be filled with embedded 87 * ones as well... 88 */ 89 #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \ 90 PPC_FEATURE_HAS_MMU) 91 #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64) 92 #define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4) 93 #define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5 |\ 94 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP) 95 #define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS|\ 96 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP) 97 #define COMMON_USER_POWER6 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\ 98 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \ 99 PPC_FEATURE_TRUE_LE | \ 100 PPC_FEATURE_PSERIES_PERFMON_COMPAT) 101 #define COMMON_USER_POWER7 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\ 102 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \ 103 PPC_FEATURE_TRUE_LE | \ 104 PPC_FEATURE_PSERIES_PERFMON_COMPAT) 105 #define COMMON_USER2_POWER7 (PPC_FEATURE2_DSCR) 106 #define COMMON_USER_POWER8 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\ 107 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \ 108 PPC_FEATURE_TRUE_LE | \ 109 PPC_FEATURE_PSERIES_PERFMON_COMPAT) 110 #define COMMON_USER2_POWER8 (PPC_FEATURE2_ARCH_2_07 | \ 111 PPC_FEATURE2_HTM_COMP | PPC_FEATURE2_DSCR | \ 112 PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | \ 113 PPC_FEATURE2_VEC_CRYPTO) 114 #define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\ 115 PPC_FEATURE_TRUE_LE | \ 116 PPC_FEATURE_HAS_ALTIVEC_COMP) 117 #ifdef CONFIG_PPC_BOOK3E_64 118 #define COMMON_USER_BOOKE (COMMON_USER_PPC64 | PPC_FEATURE_BOOKE) 119 #else 120 #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \ 121 PPC_FEATURE_BOOKE) 122 #endif 123 124 static struct cpu_spec __initdata cpu_specs[] = { 125 #ifdef CONFIG_PPC_BOOK3S_64 126 { /* Power4 */ 127 .pvr_mask = 0xffff0000, 128 .pvr_value = 0x00350000, 129 .cpu_name = "POWER4 (gp)", 130 .cpu_features = CPU_FTRS_POWER4, 131 .cpu_user_features = COMMON_USER_POWER4, 132 .mmu_features = MMU_FTRS_POWER4, 133 .icache_bsize = 128, 134 .dcache_bsize = 128, 135 .num_pmcs = 8, 136 .pmc_type = PPC_PMC_IBM, 137 .oprofile_cpu_type = "ppc64/power4", 138 .oprofile_type = PPC_OPROFILE_POWER4, 139 .platform = "power4", 140 }, 141 { /* Power4+ */ 142 .pvr_mask = 0xffff0000, 143 .pvr_value = 0x00380000, 144 .cpu_name = "POWER4+ (gq)", 145 .cpu_features = CPU_FTRS_POWER4, 146 .cpu_user_features = COMMON_USER_POWER4, 147 .mmu_features = MMU_FTRS_POWER4, 148 .icache_bsize = 128, 149 .dcache_bsize = 128, 150 .num_pmcs = 8, 151 .pmc_type = PPC_PMC_IBM, 152 .oprofile_cpu_type = "ppc64/power4", 153 .oprofile_type = PPC_OPROFILE_POWER4, 154 .platform = "power4", 155 }, 156 { /* PPC970 */ 157 .pvr_mask = 0xffff0000, 158 .pvr_value = 0x00390000, 159 .cpu_name = "PPC970", 160 .cpu_features = CPU_FTRS_PPC970, 161 .cpu_user_features = COMMON_USER_POWER4 | 162 PPC_FEATURE_HAS_ALTIVEC_COMP, 163 .mmu_features = MMU_FTRS_PPC970, 164 .icache_bsize = 128, 165 .dcache_bsize = 128, 166 .num_pmcs = 8, 167 .pmc_type = PPC_PMC_IBM, 168 .cpu_setup = __setup_cpu_ppc970, 169 .cpu_restore = __restore_cpu_ppc970, 170 .oprofile_cpu_type = "ppc64/970", 171 .oprofile_type = PPC_OPROFILE_POWER4, 172 .platform = "ppc970", 173 }, 174 { /* PPC970FX */ 175 .pvr_mask = 0xffff0000, 176 .pvr_value = 0x003c0000, 177 .cpu_name = "PPC970FX", 178 .cpu_features = CPU_FTRS_PPC970, 179 .cpu_user_features = COMMON_USER_POWER4 | 180 PPC_FEATURE_HAS_ALTIVEC_COMP, 181 .mmu_features = MMU_FTRS_PPC970, 182 .icache_bsize = 128, 183 .dcache_bsize = 128, 184 .num_pmcs = 8, 185 .pmc_type = PPC_PMC_IBM, 186 .cpu_setup = __setup_cpu_ppc970, 187 .cpu_restore = __restore_cpu_ppc970, 188 .oprofile_cpu_type = "ppc64/970", 189 .oprofile_type = PPC_OPROFILE_POWER4, 190 .platform = "ppc970", 191 }, 192 { /* PPC970MP DD1.0 - no DEEPNAP, use regular 970 init */ 193 .pvr_mask = 0xffffffff, 194 .pvr_value = 0x00440100, 195 .cpu_name = "PPC970MP", 196 .cpu_features = CPU_FTRS_PPC970, 197 .cpu_user_features = COMMON_USER_POWER4 | 198 PPC_FEATURE_HAS_ALTIVEC_COMP, 199 .mmu_features = MMU_FTRS_PPC970, 200 .icache_bsize = 128, 201 .dcache_bsize = 128, 202 .num_pmcs = 8, 203 .pmc_type = PPC_PMC_IBM, 204 .cpu_setup = __setup_cpu_ppc970, 205 .cpu_restore = __restore_cpu_ppc970, 206 .oprofile_cpu_type = "ppc64/970MP", 207 .oprofile_type = PPC_OPROFILE_POWER4, 208 .platform = "ppc970", 209 }, 210 { /* PPC970MP */ 211 .pvr_mask = 0xffff0000, 212 .pvr_value = 0x00440000, 213 .cpu_name = "PPC970MP", 214 .cpu_features = CPU_FTRS_PPC970, 215 .cpu_user_features = COMMON_USER_POWER4 | 216 PPC_FEATURE_HAS_ALTIVEC_COMP, 217 .mmu_features = MMU_FTRS_PPC970, 218 .icache_bsize = 128, 219 .dcache_bsize = 128, 220 .num_pmcs = 8, 221 .pmc_type = PPC_PMC_IBM, 222 .cpu_setup = __setup_cpu_ppc970MP, 223 .cpu_restore = __restore_cpu_ppc970, 224 .oprofile_cpu_type = "ppc64/970MP", 225 .oprofile_type = PPC_OPROFILE_POWER4, 226 .platform = "ppc970", 227 }, 228 { /* PPC970GX */ 229 .pvr_mask = 0xffff0000, 230 .pvr_value = 0x00450000, 231 .cpu_name = "PPC970GX", 232 .cpu_features = CPU_FTRS_PPC970, 233 .cpu_user_features = COMMON_USER_POWER4 | 234 PPC_FEATURE_HAS_ALTIVEC_COMP, 235 .mmu_features = MMU_FTRS_PPC970, 236 .icache_bsize = 128, 237 .dcache_bsize = 128, 238 .num_pmcs = 8, 239 .pmc_type = PPC_PMC_IBM, 240 .cpu_setup = __setup_cpu_ppc970, 241 .oprofile_cpu_type = "ppc64/970", 242 .oprofile_type = PPC_OPROFILE_POWER4, 243 .platform = "ppc970", 244 }, 245 { /* Power5 GR */ 246 .pvr_mask = 0xffff0000, 247 .pvr_value = 0x003a0000, 248 .cpu_name = "POWER5 (gr)", 249 .cpu_features = CPU_FTRS_POWER5, 250 .cpu_user_features = COMMON_USER_POWER5, 251 .mmu_features = MMU_FTRS_POWER5, 252 .icache_bsize = 128, 253 .dcache_bsize = 128, 254 .num_pmcs = 6, 255 .pmc_type = PPC_PMC_IBM, 256 .oprofile_cpu_type = "ppc64/power5", 257 .oprofile_type = PPC_OPROFILE_POWER4, 258 /* SIHV / SIPR bits are implemented on POWER4+ (GQ) 259 * and above but only works on POWER5 and above 260 */ 261 .oprofile_mmcra_sihv = MMCRA_SIHV, 262 .oprofile_mmcra_sipr = MMCRA_SIPR, 263 .platform = "power5", 264 }, 265 { /* Power5++ */ 266 .pvr_mask = 0xffffff00, 267 .pvr_value = 0x003b0300, 268 .cpu_name = "POWER5+ (gs)", 269 .cpu_features = CPU_FTRS_POWER5, 270 .cpu_user_features = COMMON_USER_POWER5_PLUS, 271 .mmu_features = MMU_FTRS_POWER5, 272 .icache_bsize = 128, 273 .dcache_bsize = 128, 274 .num_pmcs = 6, 275 .oprofile_cpu_type = "ppc64/power5++", 276 .oprofile_type = PPC_OPROFILE_POWER4, 277 .oprofile_mmcra_sihv = MMCRA_SIHV, 278 .oprofile_mmcra_sipr = MMCRA_SIPR, 279 .platform = "power5+", 280 }, 281 { /* Power5 GS */ 282 .pvr_mask = 0xffff0000, 283 .pvr_value = 0x003b0000, 284 .cpu_name = "POWER5+ (gs)", 285 .cpu_features = CPU_FTRS_POWER5, 286 .cpu_user_features = COMMON_USER_POWER5_PLUS, 287 .mmu_features = MMU_FTRS_POWER5, 288 .icache_bsize = 128, 289 .dcache_bsize = 128, 290 .num_pmcs = 6, 291 .pmc_type = PPC_PMC_IBM, 292 .oprofile_cpu_type = "ppc64/power5+", 293 .oprofile_type = PPC_OPROFILE_POWER4, 294 .oprofile_mmcra_sihv = MMCRA_SIHV, 295 .oprofile_mmcra_sipr = MMCRA_SIPR, 296 .platform = "power5+", 297 }, 298 { /* POWER6 in P5+ mode; 2.04-compliant processor */ 299 .pvr_mask = 0xffffffff, 300 .pvr_value = 0x0f000001, 301 .cpu_name = "POWER5+", 302 .cpu_features = CPU_FTRS_POWER5, 303 .cpu_user_features = COMMON_USER_POWER5_PLUS, 304 .mmu_features = MMU_FTRS_POWER5, 305 .icache_bsize = 128, 306 .dcache_bsize = 128, 307 .oprofile_cpu_type = "ppc64/ibm-compat-v1", 308 .oprofile_type = PPC_OPROFILE_POWER4, 309 .platform = "power5+", 310 }, 311 { /* Power6 */ 312 .pvr_mask = 0xffff0000, 313 .pvr_value = 0x003e0000, 314 .cpu_name = "POWER6 (raw)", 315 .cpu_features = CPU_FTRS_POWER6, 316 .cpu_user_features = COMMON_USER_POWER6 | 317 PPC_FEATURE_POWER6_EXT, 318 .mmu_features = MMU_FTRS_POWER6, 319 .icache_bsize = 128, 320 .dcache_bsize = 128, 321 .num_pmcs = 6, 322 .pmc_type = PPC_PMC_IBM, 323 .oprofile_cpu_type = "ppc64/power6", 324 .oprofile_type = PPC_OPROFILE_POWER4, 325 .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV, 326 .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR, 327 .oprofile_mmcra_clear = POWER6_MMCRA_THRM | 328 POWER6_MMCRA_OTHER, 329 .platform = "power6x", 330 }, 331 { /* 2.05-compliant processor, i.e. Power6 "architected" mode */ 332 .pvr_mask = 0xffffffff, 333 .pvr_value = 0x0f000002, 334 .cpu_name = "POWER6 (architected)", 335 .cpu_features = CPU_FTRS_POWER6, 336 .cpu_user_features = COMMON_USER_POWER6, 337 .mmu_features = MMU_FTRS_POWER6, 338 .icache_bsize = 128, 339 .dcache_bsize = 128, 340 .oprofile_cpu_type = "ppc64/ibm-compat-v1", 341 .oprofile_type = PPC_OPROFILE_POWER4, 342 .platform = "power6", 343 }, 344 { /* 2.06-compliant processor, i.e. Power7 "architected" mode */ 345 .pvr_mask = 0xffffffff, 346 .pvr_value = 0x0f000003, 347 .cpu_name = "POWER7 (architected)", 348 .cpu_features = CPU_FTRS_POWER7, 349 .cpu_user_features = COMMON_USER_POWER7, 350 .cpu_user_features2 = COMMON_USER2_POWER7, 351 .mmu_features = MMU_FTRS_POWER7, 352 .icache_bsize = 128, 353 .dcache_bsize = 128, 354 .oprofile_type = PPC_OPROFILE_POWER4, 355 .oprofile_cpu_type = "ppc64/ibm-compat-v1", 356 .cpu_setup = __setup_cpu_power7, 357 .cpu_restore = __restore_cpu_power7, 358 .flush_tlb = __flush_tlb_power7, 359 .machine_check_early = __machine_check_early_realmode_p7, 360 .platform = "power7", 361 }, 362 { /* 2.07-compliant processor, i.e. Power8 "architected" mode */ 363 .pvr_mask = 0xffffffff, 364 .pvr_value = 0x0f000004, 365 .cpu_name = "POWER8 (architected)", 366 .cpu_features = CPU_FTRS_POWER8, 367 .cpu_user_features = COMMON_USER_POWER8, 368 .cpu_user_features2 = COMMON_USER2_POWER8, 369 .mmu_features = MMU_FTRS_POWER8, 370 .icache_bsize = 128, 371 .dcache_bsize = 128, 372 .oprofile_type = PPC_OPROFILE_INVALID, 373 .oprofile_cpu_type = "ppc64/ibm-compat-v1", 374 .cpu_setup = __setup_cpu_power8, 375 .cpu_restore = __restore_cpu_power8, 376 .flush_tlb = __flush_tlb_power8, 377 .machine_check_early = __machine_check_early_realmode_p8, 378 .platform = "power8", 379 }, 380 { /* Power7 */ 381 .pvr_mask = 0xffff0000, 382 .pvr_value = 0x003f0000, 383 .cpu_name = "POWER7 (raw)", 384 .cpu_features = CPU_FTRS_POWER7, 385 .cpu_user_features = COMMON_USER_POWER7, 386 .cpu_user_features2 = COMMON_USER2_POWER7, 387 .mmu_features = MMU_FTRS_POWER7, 388 .icache_bsize = 128, 389 .dcache_bsize = 128, 390 .num_pmcs = 6, 391 .pmc_type = PPC_PMC_IBM, 392 .oprofile_cpu_type = "ppc64/power7", 393 .oprofile_type = PPC_OPROFILE_POWER4, 394 .cpu_setup = __setup_cpu_power7, 395 .cpu_restore = __restore_cpu_power7, 396 .flush_tlb = __flush_tlb_power7, 397 .machine_check_early = __machine_check_early_realmode_p7, 398 .platform = "power7", 399 }, 400 { /* Power7+ */ 401 .pvr_mask = 0xffff0000, 402 .pvr_value = 0x004A0000, 403 .cpu_name = "POWER7+ (raw)", 404 .cpu_features = CPU_FTRS_POWER7, 405 .cpu_user_features = COMMON_USER_POWER7, 406 .cpu_user_features2 = COMMON_USER2_POWER7, 407 .mmu_features = MMU_FTRS_POWER7, 408 .icache_bsize = 128, 409 .dcache_bsize = 128, 410 .num_pmcs = 6, 411 .pmc_type = PPC_PMC_IBM, 412 .oprofile_cpu_type = "ppc64/power7", 413 .oprofile_type = PPC_OPROFILE_POWER4, 414 .cpu_setup = __setup_cpu_power7, 415 .cpu_restore = __restore_cpu_power7, 416 .flush_tlb = __flush_tlb_power7, 417 .machine_check_early = __machine_check_early_realmode_p7, 418 .platform = "power7+", 419 }, 420 { /* Power8E */ 421 .pvr_mask = 0xffff0000, 422 .pvr_value = 0x004b0000, 423 .cpu_name = "POWER8E (raw)", 424 .cpu_features = CPU_FTRS_POWER8E, 425 .cpu_user_features = COMMON_USER_POWER8, 426 .cpu_user_features2 = COMMON_USER2_POWER8, 427 .mmu_features = MMU_FTRS_POWER8, 428 .icache_bsize = 128, 429 .dcache_bsize = 128, 430 .num_pmcs = 6, 431 .pmc_type = PPC_PMC_IBM, 432 .oprofile_cpu_type = "ppc64/power8", 433 .oprofile_type = PPC_OPROFILE_INVALID, 434 .cpu_setup = __setup_cpu_power8, 435 .cpu_restore = __restore_cpu_power8, 436 .flush_tlb = __flush_tlb_power8, 437 .machine_check_early = __machine_check_early_realmode_p8, 438 .platform = "power8", 439 }, 440 { /* Power8 DD1: Does not support doorbell IPIs */ 441 .pvr_mask = 0xffffff00, 442 .pvr_value = 0x004d0100, 443 .cpu_name = "POWER8 (raw)", 444 .cpu_features = CPU_FTRS_POWER8_DD1, 445 .cpu_user_features = COMMON_USER_POWER8, 446 .cpu_user_features2 = COMMON_USER2_POWER8, 447 .mmu_features = MMU_FTRS_POWER8, 448 .icache_bsize = 128, 449 .dcache_bsize = 128, 450 .num_pmcs = 6, 451 .pmc_type = PPC_PMC_IBM, 452 .oprofile_cpu_type = "ppc64/power8", 453 .oprofile_type = PPC_OPROFILE_INVALID, 454 .cpu_setup = __setup_cpu_power8, 455 .cpu_restore = __restore_cpu_power8, 456 .flush_tlb = __flush_tlb_power8, 457 .machine_check_early = __machine_check_early_realmode_p8, 458 .platform = "power8", 459 }, 460 { /* Power8 */ 461 .pvr_mask = 0xffff0000, 462 .pvr_value = 0x004d0000, 463 .cpu_name = "POWER8 (raw)", 464 .cpu_features = CPU_FTRS_POWER8, 465 .cpu_user_features = COMMON_USER_POWER8, 466 .cpu_user_features2 = COMMON_USER2_POWER8, 467 .mmu_features = MMU_FTRS_POWER8, 468 .icache_bsize = 128, 469 .dcache_bsize = 128, 470 .num_pmcs = 6, 471 .pmc_type = PPC_PMC_IBM, 472 .oprofile_cpu_type = "ppc64/power8", 473 .oprofile_type = PPC_OPROFILE_INVALID, 474 .cpu_setup = __setup_cpu_power8, 475 .cpu_restore = __restore_cpu_power8, 476 .flush_tlb = __flush_tlb_power8, 477 .machine_check_early = __machine_check_early_realmode_p8, 478 .platform = "power8", 479 }, 480 { /* Cell Broadband Engine */ 481 .pvr_mask = 0xffff0000, 482 .pvr_value = 0x00700000, 483 .cpu_name = "Cell Broadband Engine", 484 .cpu_features = CPU_FTRS_CELL, 485 .cpu_user_features = COMMON_USER_PPC64 | 486 PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP | 487 PPC_FEATURE_SMT, 488 .mmu_features = MMU_FTRS_CELL, 489 .icache_bsize = 128, 490 .dcache_bsize = 128, 491 .num_pmcs = 4, 492 .pmc_type = PPC_PMC_IBM, 493 .oprofile_cpu_type = "ppc64/cell-be", 494 .oprofile_type = PPC_OPROFILE_CELL, 495 .platform = "ppc-cell-be", 496 }, 497 { /* PA Semi PA6T */ 498 .pvr_mask = 0x7fff0000, 499 .pvr_value = 0x00900000, 500 .cpu_name = "PA6T", 501 .cpu_features = CPU_FTRS_PA6T, 502 .cpu_user_features = COMMON_USER_PA6T, 503 .mmu_features = MMU_FTRS_PA6T, 504 .icache_bsize = 64, 505 .dcache_bsize = 64, 506 .num_pmcs = 6, 507 .pmc_type = PPC_PMC_PA6T, 508 .cpu_setup = __setup_cpu_pa6t, 509 .cpu_restore = __restore_cpu_pa6t, 510 .oprofile_cpu_type = "ppc64/pa6t", 511 .oprofile_type = PPC_OPROFILE_PA6T, 512 .platform = "pa6t", 513 }, 514 { /* default match */ 515 .pvr_mask = 0x00000000, 516 .pvr_value = 0x00000000, 517 .cpu_name = "POWER4 (compatible)", 518 .cpu_features = CPU_FTRS_COMPATIBLE, 519 .cpu_user_features = COMMON_USER_PPC64, 520 .mmu_features = MMU_FTRS_DEFAULT_HPTE_ARCH_V2, 521 .icache_bsize = 128, 522 .dcache_bsize = 128, 523 .num_pmcs = 6, 524 .pmc_type = PPC_PMC_IBM, 525 .platform = "power4", 526 } 527 #endif /* CONFIG_PPC_BOOK3S_64 */ 528 529 #ifdef CONFIG_PPC32 530 #ifdef CONFIG_PPC_BOOK3S_32 531 { /* 601 */ 532 .pvr_mask = 0xffff0000, 533 .pvr_value = 0x00010000, 534 .cpu_name = "601", 535 .cpu_features = CPU_FTRS_PPC601, 536 .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR | 537 PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB, 538 .mmu_features = MMU_FTR_HPTE_TABLE, 539 .icache_bsize = 32, 540 .dcache_bsize = 32, 541 .machine_check = machine_check_generic, 542 .platform = "ppc601", 543 }, 544 { /* 603 */ 545 .pvr_mask = 0xffff0000, 546 .pvr_value = 0x00030000, 547 .cpu_name = "603", 548 .cpu_features = CPU_FTRS_603, 549 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 550 .mmu_features = 0, 551 .icache_bsize = 32, 552 .dcache_bsize = 32, 553 .cpu_setup = __setup_cpu_603, 554 .machine_check = machine_check_generic, 555 .platform = "ppc603", 556 }, 557 { /* 603e */ 558 .pvr_mask = 0xffff0000, 559 .pvr_value = 0x00060000, 560 .cpu_name = "603e", 561 .cpu_features = CPU_FTRS_603, 562 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 563 .mmu_features = 0, 564 .icache_bsize = 32, 565 .dcache_bsize = 32, 566 .cpu_setup = __setup_cpu_603, 567 .machine_check = machine_check_generic, 568 .platform = "ppc603", 569 }, 570 { /* 603ev */ 571 .pvr_mask = 0xffff0000, 572 .pvr_value = 0x00070000, 573 .cpu_name = "603ev", 574 .cpu_features = CPU_FTRS_603, 575 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 576 .mmu_features = 0, 577 .icache_bsize = 32, 578 .dcache_bsize = 32, 579 .cpu_setup = __setup_cpu_603, 580 .machine_check = machine_check_generic, 581 .platform = "ppc603", 582 }, 583 { /* 604 */ 584 .pvr_mask = 0xffff0000, 585 .pvr_value = 0x00040000, 586 .cpu_name = "604", 587 .cpu_features = CPU_FTRS_604, 588 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 589 .mmu_features = MMU_FTR_HPTE_TABLE, 590 .icache_bsize = 32, 591 .dcache_bsize = 32, 592 .num_pmcs = 2, 593 .cpu_setup = __setup_cpu_604, 594 .machine_check = machine_check_generic, 595 .platform = "ppc604", 596 }, 597 { /* 604e */ 598 .pvr_mask = 0xfffff000, 599 .pvr_value = 0x00090000, 600 .cpu_name = "604e", 601 .cpu_features = CPU_FTRS_604, 602 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 603 .mmu_features = MMU_FTR_HPTE_TABLE, 604 .icache_bsize = 32, 605 .dcache_bsize = 32, 606 .num_pmcs = 4, 607 .cpu_setup = __setup_cpu_604, 608 .machine_check = machine_check_generic, 609 .platform = "ppc604", 610 }, 611 { /* 604r */ 612 .pvr_mask = 0xffff0000, 613 .pvr_value = 0x00090000, 614 .cpu_name = "604r", 615 .cpu_features = CPU_FTRS_604, 616 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 617 .mmu_features = MMU_FTR_HPTE_TABLE, 618 .icache_bsize = 32, 619 .dcache_bsize = 32, 620 .num_pmcs = 4, 621 .cpu_setup = __setup_cpu_604, 622 .machine_check = machine_check_generic, 623 .platform = "ppc604", 624 }, 625 { /* 604ev */ 626 .pvr_mask = 0xffff0000, 627 .pvr_value = 0x000a0000, 628 .cpu_name = "604ev", 629 .cpu_features = CPU_FTRS_604, 630 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 631 .mmu_features = MMU_FTR_HPTE_TABLE, 632 .icache_bsize = 32, 633 .dcache_bsize = 32, 634 .num_pmcs = 4, 635 .cpu_setup = __setup_cpu_604, 636 .machine_check = machine_check_generic, 637 .platform = "ppc604", 638 }, 639 { /* 740/750 (0x4202, don't support TAU ?) */ 640 .pvr_mask = 0xffffffff, 641 .pvr_value = 0x00084202, 642 .cpu_name = "740/750", 643 .cpu_features = CPU_FTRS_740_NOTAU, 644 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 645 .mmu_features = MMU_FTR_HPTE_TABLE, 646 .icache_bsize = 32, 647 .dcache_bsize = 32, 648 .num_pmcs = 4, 649 .cpu_setup = __setup_cpu_750, 650 .machine_check = machine_check_generic, 651 .platform = "ppc750", 652 }, 653 { /* 750CX (80100 and 8010x?) */ 654 .pvr_mask = 0xfffffff0, 655 .pvr_value = 0x00080100, 656 .cpu_name = "750CX", 657 .cpu_features = CPU_FTRS_750, 658 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 659 .mmu_features = MMU_FTR_HPTE_TABLE, 660 .icache_bsize = 32, 661 .dcache_bsize = 32, 662 .num_pmcs = 4, 663 .cpu_setup = __setup_cpu_750cx, 664 .machine_check = machine_check_generic, 665 .platform = "ppc750", 666 }, 667 { /* 750CX (82201 and 82202) */ 668 .pvr_mask = 0xfffffff0, 669 .pvr_value = 0x00082200, 670 .cpu_name = "750CX", 671 .cpu_features = CPU_FTRS_750, 672 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 673 .mmu_features = MMU_FTR_HPTE_TABLE, 674 .icache_bsize = 32, 675 .dcache_bsize = 32, 676 .num_pmcs = 4, 677 .pmc_type = PPC_PMC_IBM, 678 .cpu_setup = __setup_cpu_750cx, 679 .machine_check = machine_check_generic, 680 .platform = "ppc750", 681 }, 682 { /* 750CXe (82214) */ 683 .pvr_mask = 0xfffffff0, 684 .pvr_value = 0x00082210, 685 .cpu_name = "750CXe", 686 .cpu_features = CPU_FTRS_750, 687 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 688 .mmu_features = MMU_FTR_HPTE_TABLE, 689 .icache_bsize = 32, 690 .dcache_bsize = 32, 691 .num_pmcs = 4, 692 .pmc_type = PPC_PMC_IBM, 693 .cpu_setup = __setup_cpu_750cx, 694 .machine_check = machine_check_generic, 695 .platform = "ppc750", 696 }, 697 { /* 750CXe "Gekko" (83214) */ 698 .pvr_mask = 0xffffffff, 699 .pvr_value = 0x00083214, 700 .cpu_name = "750CXe", 701 .cpu_features = CPU_FTRS_750, 702 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 703 .mmu_features = MMU_FTR_HPTE_TABLE, 704 .icache_bsize = 32, 705 .dcache_bsize = 32, 706 .num_pmcs = 4, 707 .pmc_type = PPC_PMC_IBM, 708 .cpu_setup = __setup_cpu_750cx, 709 .machine_check = machine_check_generic, 710 .platform = "ppc750", 711 }, 712 { /* 750CL (and "Broadway") */ 713 .pvr_mask = 0xfffff0e0, 714 .pvr_value = 0x00087000, 715 .cpu_name = "750CL", 716 .cpu_features = CPU_FTRS_750CL, 717 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 718 .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 719 .icache_bsize = 32, 720 .dcache_bsize = 32, 721 .num_pmcs = 4, 722 .pmc_type = PPC_PMC_IBM, 723 .cpu_setup = __setup_cpu_750, 724 .machine_check = machine_check_generic, 725 .platform = "ppc750", 726 .oprofile_cpu_type = "ppc/750", 727 .oprofile_type = PPC_OPROFILE_G4, 728 }, 729 { /* 745/755 */ 730 .pvr_mask = 0xfffff000, 731 .pvr_value = 0x00083000, 732 .cpu_name = "745/755", 733 .cpu_features = CPU_FTRS_750, 734 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 735 .mmu_features = MMU_FTR_HPTE_TABLE, 736 .icache_bsize = 32, 737 .dcache_bsize = 32, 738 .num_pmcs = 4, 739 .pmc_type = PPC_PMC_IBM, 740 .cpu_setup = __setup_cpu_750, 741 .machine_check = machine_check_generic, 742 .platform = "ppc750", 743 }, 744 { /* 750FX rev 1.x */ 745 .pvr_mask = 0xffffff00, 746 .pvr_value = 0x70000100, 747 .cpu_name = "750FX", 748 .cpu_features = CPU_FTRS_750FX1, 749 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 750 .mmu_features = MMU_FTR_HPTE_TABLE, 751 .icache_bsize = 32, 752 .dcache_bsize = 32, 753 .num_pmcs = 4, 754 .pmc_type = PPC_PMC_IBM, 755 .cpu_setup = __setup_cpu_750, 756 .machine_check = machine_check_generic, 757 .platform = "ppc750", 758 .oprofile_cpu_type = "ppc/750", 759 .oprofile_type = PPC_OPROFILE_G4, 760 }, 761 { /* 750FX rev 2.0 must disable HID0[DPM] */ 762 .pvr_mask = 0xffffffff, 763 .pvr_value = 0x70000200, 764 .cpu_name = "750FX", 765 .cpu_features = CPU_FTRS_750FX2, 766 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 767 .mmu_features = MMU_FTR_HPTE_TABLE, 768 .icache_bsize = 32, 769 .dcache_bsize = 32, 770 .num_pmcs = 4, 771 .pmc_type = PPC_PMC_IBM, 772 .cpu_setup = __setup_cpu_750, 773 .machine_check = machine_check_generic, 774 .platform = "ppc750", 775 .oprofile_cpu_type = "ppc/750", 776 .oprofile_type = PPC_OPROFILE_G4, 777 }, 778 { /* 750FX (All revs except 2.0) */ 779 .pvr_mask = 0xffff0000, 780 .pvr_value = 0x70000000, 781 .cpu_name = "750FX", 782 .cpu_features = CPU_FTRS_750FX, 783 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 784 .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 785 .icache_bsize = 32, 786 .dcache_bsize = 32, 787 .num_pmcs = 4, 788 .pmc_type = PPC_PMC_IBM, 789 .cpu_setup = __setup_cpu_750fx, 790 .machine_check = machine_check_generic, 791 .platform = "ppc750", 792 .oprofile_cpu_type = "ppc/750", 793 .oprofile_type = PPC_OPROFILE_G4, 794 }, 795 { /* 750GX */ 796 .pvr_mask = 0xffff0000, 797 .pvr_value = 0x70020000, 798 .cpu_name = "750GX", 799 .cpu_features = CPU_FTRS_750GX, 800 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 801 .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 802 .icache_bsize = 32, 803 .dcache_bsize = 32, 804 .num_pmcs = 4, 805 .pmc_type = PPC_PMC_IBM, 806 .cpu_setup = __setup_cpu_750fx, 807 .machine_check = machine_check_generic, 808 .platform = "ppc750", 809 .oprofile_cpu_type = "ppc/750", 810 .oprofile_type = PPC_OPROFILE_G4, 811 }, 812 { /* 740/750 (L2CR bit need fixup for 740) */ 813 .pvr_mask = 0xffff0000, 814 .pvr_value = 0x00080000, 815 .cpu_name = "740/750", 816 .cpu_features = CPU_FTRS_740, 817 .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 818 .mmu_features = MMU_FTR_HPTE_TABLE, 819 .icache_bsize = 32, 820 .dcache_bsize = 32, 821 .num_pmcs = 4, 822 .pmc_type = PPC_PMC_IBM, 823 .cpu_setup = __setup_cpu_750, 824 .machine_check = machine_check_generic, 825 .platform = "ppc750", 826 }, 827 { /* 7400 rev 1.1 ? (no TAU) */ 828 .pvr_mask = 0xffffffff, 829 .pvr_value = 0x000c1101, 830 .cpu_name = "7400 (1.1)", 831 .cpu_features = CPU_FTRS_7400_NOTAU, 832 .cpu_user_features = COMMON_USER | 833 PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 834 .mmu_features = MMU_FTR_HPTE_TABLE, 835 .icache_bsize = 32, 836 .dcache_bsize = 32, 837 .num_pmcs = 4, 838 .pmc_type = PPC_PMC_G4, 839 .cpu_setup = __setup_cpu_7400, 840 .machine_check = machine_check_generic, 841 .platform = "ppc7400", 842 }, 843 { /* 7400 */ 844 .pvr_mask = 0xffff0000, 845 .pvr_value = 0x000c0000, 846 .cpu_name = "7400", 847 .cpu_features = CPU_FTRS_7400, 848 .cpu_user_features = COMMON_USER | 849 PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 850 .mmu_features = MMU_FTR_HPTE_TABLE, 851 .icache_bsize = 32, 852 .dcache_bsize = 32, 853 .num_pmcs = 4, 854 .pmc_type = PPC_PMC_G4, 855 .cpu_setup = __setup_cpu_7400, 856 .machine_check = machine_check_generic, 857 .platform = "ppc7400", 858 }, 859 { /* 7410 */ 860 .pvr_mask = 0xffff0000, 861 .pvr_value = 0x800c0000, 862 .cpu_name = "7410", 863 .cpu_features = CPU_FTRS_7400, 864 .cpu_user_features = COMMON_USER | 865 PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 866 .mmu_features = MMU_FTR_HPTE_TABLE, 867 .icache_bsize = 32, 868 .dcache_bsize = 32, 869 .num_pmcs = 4, 870 .pmc_type = PPC_PMC_G4, 871 .cpu_setup = __setup_cpu_7410, 872 .machine_check = machine_check_generic, 873 .platform = "ppc7400", 874 }, 875 { /* 7450 2.0 - no doze/nap */ 876 .pvr_mask = 0xffffffff, 877 .pvr_value = 0x80000200, 878 .cpu_name = "7450", 879 .cpu_features = CPU_FTRS_7450_20, 880 .cpu_user_features = COMMON_USER | 881 PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 882 .mmu_features = MMU_FTR_HPTE_TABLE, 883 .icache_bsize = 32, 884 .dcache_bsize = 32, 885 .num_pmcs = 6, 886 .pmc_type = PPC_PMC_G4, 887 .cpu_setup = __setup_cpu_745x, 888 .oprofile_cpu_type = "ppc/7450", 889 .oprofile_type = PPC_OPROFILE_G4, 890 .machine_check = machine_check_generic, 891 .platform = "ppc7450", 892 }, 893 { /* 7450 2.1 */ 894 .pvr_mask = 0xffffffff, 895 .pvr_value = 0x80000201, 896 .cpu_name = "7450", 897 .cpu_features = CPU_FTRS_7450_21, 898 .cpu_user_features = COMMON_USER | 899 PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 900 .mmu_features = MMU_FTR_HPTE_TABLE, 901 .icache_bsize = 32, 902 .dcache_bsize = 32, 903 .num_pmcs = 6, 904 .pmc_type = PPC_PMC_G4, 905 .cpu_setup = __setup_cpu_745x, 906 .oprofile_cpu_type = "ppc/7450", 907 .oprofile_type = PPC_OPROFILE_G4, 908 .machine_check = machine_check_generic, 909 .platform = "ppc7450", 910 }, 911 { /* 7450 2.3 and newer */ 912 .pvr_mask = 0xffff0000, 913 .pvr_value = 0x80000000, 914 .cpu_name = "7450", 915 .cpu_features = CPU_FTRS_7450_23, 916 .cpu_user_features = COMMON_USER | 917 PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 918 .mmu_features = MMU_FTR_HPTE_TABLE, 919 .icache_bsize = 32, 920 .dcache_bsize = 32, 921 .num_pmcs = 6, 922 .pmc_type = PPC_PMC_G4, 923 .cpu_setup = __setup_cpu_745x, 924 .oprofile_cpu_type = "ppc/7450", 925 .oprofile_type = PPC_OPROFILE_G4, 926 .machine_check = machine_check_generic, 927 .platform = "ppc7450", 928 }, 929 { /* 7455 rev 1.x */ 930 .pvr_mask = 0xffffff00, 931 .pvr_value = 0x80010100, 932 .cpu_name = "7455", 933 .cpu_features = CPU_FTRS_7455_1, 934 .cpu_user_features = COMMON_USER | 935 PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 936 .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 937 .icache_bsize = 32, 938 .dcache_bsize = 32, 939 .num_pmcs = 6, 940 .pmc_type = PPC_PMC_G4, 941 .cpu_setup = __setup_cpu_745x, 942 .oprofile_cpu_type = "ppc/7450", 943 .oprofile_type = PPC_OPROFILE_G4, 944 .machine_check = machine_check_generic, 945 .platform = "ppc7450", 946 }, 947 { /* 7455 rev 2.0 */ 948 .pvr_mask = 0xffffffff, 949 .pvr_value = 0x80010200, 950 .cpu_name = "7455", 951 .cpu_features = CPU_FTRS_7455_20, 952 .cpu_user_features = COMMON_USER | 953 PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 954 .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 955 .icache_bsize = 32, 956 .dcache_bsize = 32, 957 .num_pmcs = 6, 958 .pmc_type = PPC_PMC_G4, 959 .cpu_setup = __setup_cpu_745x, 960 .oprofile_cpu_type = "ppc/7450", 961 .oprofile_type = PPC_OPROFILE_G4, 962 .machine_check = machine_check_generic, 963 .platform = "ppc7450", 964 }, 965 { /* 7455 others */ 966 .pvr_mask = 0xffff0000, 967 .pvr_value = 0x80010000, 968 .cpu_name = "7455", 969 .cpu_features = CPU_FTRS_7455, 970 .cpu_user_features = COMMON_USER | 971 PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 972 .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 973 .icache_bsize = 32, 974 .dcache_bsize = 32, 975 .num_pmcs = 6, 976 .pmc_type = PPC_PMC_G4, 977 .cpu_setup = __setup_cpu_745x, 978 .oprofile_cpu_type = "ppc/7450", 979 .oprofile_type = PPC_OPROFILE_G4, 980 .machine_check = machine_check_generic, 981 .platform = "ppc7450", 982 }, 983 { /* 7447/7457 Rev 1.0 */ 984 .pvr_mask = 0xffffffff, 985 .pvr_value = 0x80020100, 986 .cpu_name = "7447/7457", 987 .cpu_features = CPU_FTRS_7447_10, 988 .cpu_user_features = COMMON_USER | 989 PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 990 .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 991 .icache_bsize = 32, 992 .dcache_bsize = 32, 993 .num_pmcs = 6, 994 .pmc_type = PPC_PMC_G4, 995 .cpu_setup = __setup_cpu_745x, 996 .oprofile_cpu_type = "ppc/7450", 997 .oprofile_type = PPC_OPROFILE_G4, 998 .machine_check = machine_check_generic, 999 .platform = "ppc7450", 1000 }, 1001 { /* 7447/7457 Rev 1.1 */ 1002 .pvr_mask = 0xffffffff, 1003 .pvr_value = 0x80020101, 1004 .cpu_name = "7447/7457", 1005 .cpu_features = CPU_FTRS_7447_10, 1006 .cpu_user_features = COMMON_USER | 1007 PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 1008 .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 1009 .icache_bsize = 32, 1010 .dcache_bsize = 32, 1011 .num_pmcs = 6, 1012 .pmc_type = PPC_PMC_G4, 1013 .cpu_setup = __setup_cpu_745x, 1014 .oprofile_cpu_type = "ppc/7450", 1015 .oprofile_type = PPC_OPROFILE_G4, 1016 .machine_check = machine_check_generic, 1017 .platform = "ppc7450", 1018 }, 1019 { /* 7447/7457 Rev 1.2 and later */ 1020 .pvr_mask = 0xffff0000, 1021 .pvr_value = 0x80020000, 1022 .cpu_name = "7447/7457", 1023 .cpu_features = CPU_FTRS_7447, 1024 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 1025 .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 1026 .icache_bsize = 32, 1027 .dcache_bsize = 32, 1028 .num_pmcs = 6, 1029 .pmc_type = PPC_PMC_G4, 1030 .cpu_setup = __setup_cpu_745x, 1031 .oprofile_cpu_type = "ppc/7450", 1032 .oprofile_type = PPC_OPROFILE_G4, 1033 .machine_check = machine_check_generic, 1034 .platform = "ppc7450", 1035 }, 1036 { /* 7447A */ 1037 .pvr_mask = 0xffff0000, 1038 .pvr_value = 0x80030000, 1039 .cpu_name = "7447A", 1040 .cpu_features = CPU_FTRS_7447A, 1041 .cpu_user_features = COMMON_USER | 1042 PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 1043 .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 1044 .icache_bsize = 32, 1045 .dcache_bsize = 32, 1046 .num_pmcs = 6, 1047 .pmc_type = PPC_PMC_G4, 1048 .cpu_setup = __setup_cpu_745x, 1049 .oprofile_cpu_type = "ppc/7450", 1050 .oprofile_type = PPC_OPROFILE_G4, 1051 .machine_check = machine_check_generic, 1052 .platform = "ppc7450", 1053 }, 1054 { /* 7448 */ 1055 .pvr_mask = 0xffff0000, 1056 .pvr_value = 0x80040000, 1057 .cpu_name = "7448", 1058 .cpu_features = CPU_FTRS_7448, 1059 .cpu_user_features = COMMON_USER | 1060 PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 1061 .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 1062 .icache_bsize = 32, 1063 .dcache_bsize = 32, 1064 .num_pmcs = 6, 1065 .pmc_type = PPC_PMC_G4, 1066 .cpu_setup = __setup_cpu_745x, 1067 .oprofile_cpu_type = "ppc/7450", 1068 .oprofile_type = PPC_OPROFILE_G4, 1069 .machine_check = machine_check_generic, 1070 .platform = "ppc7450", 1071 }, 1072 { /* 82xx (8240, 8245, 8260 are all 603e cores) */ 1073 .pvr_mask = 0x7fff0000, 1074 .pvr_value = 0x00810000, 1075 .cpu_name = "82xx", 1076 .cpu_features = CPU_FTRS_82XX, 1077 .cpu_user_features = COMMON_USER, 1078 .mmu_features = 0, 1079 .icache_bsize = 32, 1080 .dcache_bsize = 32, 1081 .cpu_setup = __setup_cpu_603, 1082 .machine_check = machine_check_generic, 1083 .platform = "ppc603", 1084 }, 1085 { /* All G2_LE (603e core, plus some) have the same pvr */ 1086 .pvr_mask = 0x7fff0000, 1087 .pvr_value = 0x00820000, 1088 .cpu_name = "G2_LE", 1089 .cpu_features = CPU_FTRS_G2_LE, 1090 .cpu_user_features = COMMON_USER, 1091 .mmu_features = MMU_FTR_USE_HIGH_BATS, 1092 .icache_bsize = 32, 1093 .dcache_bsize = 32, 1094 .cpu_setup = __setup_cpu_603, 1095 .machine_check = machine_check_generic, 1096 .platform = "ppc603", 1097 }, 1098 { /* e300c1 (a 603e core, plus some) on 83xx */ 1099 .pvr_mask = 0x7fff0000, 1100 .pvr_value = 0x00830000, 1101 .cpu_name = "e300c1", 1102 .cpu_features = CPU_FTRS_E300, 1103 .cpu_user_features = COMMON_USER, 1104 .mmu_features = MMU_FTR_USE_HIGH_BATS, 1105 .icache_bsize = 32, 1106 .dcache_bsize = 32, 1107 .cpu_setup = __setup_cpu_603, 1108 .machine_check = machine_check_generic, 1109 .platform = "ppc603", 1110 }, 1111 { /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */ 1112 .pvr_mask = 0x7fff0000, 1113 .pvr_value = 0x00840000, 1114 .cpu_name = "e300c2", 1115 .cpu_features = CPU_FTRS_E300C2, 1116 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 1117 .mmu_features = MMU_FTR_USE_HIGH_BATS | 1118 MMU_FTR_NEED_DTLB_SW_LRU, 1119 .icache_bsize = 32, 1120 .dcache_bsize = 32, 1121 .cpu_setup = __setup_cpu_603, 1122 .machine_check = machine_check_generic, 1123 .platform = "ppc603", 1124 }, 1125 { /* e300c3 (e300c1, plus one IU, half cache size) on 83xx */ 1126 .pvr_mask = 0x7fff0000, 1127 .pvr_value = 0x00850000, 1128 .cpu_name = "e300c3", 1129 .cpu_features = CPU_FTRS_E300, 1130 .cpu_user_features = COMMON_USER, 1131 .mmu_features = MMU_FTR_USE_HIGH_BATS | 1132 MMU_FTR_NEED_DTLB_SW_LRU, 1133 .icache_bsize = 32, 1134 .dcache_bsize = 32, 1135 .cpu_setup = __setup_cpu_603, 1136 .num_pmcs = 4, 1137 .oprofile_cpu_type = "ppc/e300", 1138 .oprofile_type = PPC_OPROFILE_FSL_EMB, 1139 .platform = "ppc603", 1140 }, 1141 { /* e300c4 (e300c1, plus one IU) */ 1142 .pvr_mask = 0x7fff0000, 1143 .pvr_value = 0x00860000, 1144 .cpu_name = "e300c4", 1145 .cpu_features = CPU_FTRS_E300, 1146 .cpu_user_features = COMMON_USER, 1147 .mmu_features = MMU_FTR_USE_HIGH_BATS | 1148 MMU_FTR_NEED_DTLB_SW_LRU, 1149 .icache_bsize = 32, 1150 .dcache_bsize = 32, 1151 .cpu_setup = __setup_cpu_603, 1152 .machine_check = machine_check_generic, 1153 .num_pmcs = 4, 1154 .oprofile_cpu_type = "ppc/e300", 1155 .oprofile_type = PPC_OPROFILE_FSL_EMB, 1156 .platform = "ppc603", 1157 }, 1158 { /* default match, we assume split I/D cache & TB (non-601)... */ 1159 .pvr_mask = 0x00000000, 1160 .pvr_value = 0x00000000, 1161 .cpu_name = "(generic PPC)", 1162 .cpu_features = CPU_FTRS_CLASSIC32, 1163 .cpu_user_features = COMMON_USER, 1164 .mmu_features = MMU_FTR_HPTE_TABLE, 1165 .icache_bsize = 32, 1166 .dcache_bsize = 32, 1167 .machine_check = machine_check_generic, 1168 .platform = "ppc603", 1169 }, 1170 #endif /* CONFIG_PPC_BOOK3S_32 */ 1171 #ifdef CONFIG_8xx 1172 { /* 8xx */ 1173 .pvr_mask = 0xffff0000, 1174 .pvr_value = 0x00500000, 1175 .cpu_name = "8xx", 1176 /* CPU_FTR_MAYBE_CAN_DOZE is possible, 1177 * if the 8xx code is there.... */ 1178 .cpu_features = CPU_FTRS_8XX, 1179 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 1180 .mmu_features = MMU_FTR_TYPE_8xx, 1181 .icache_bsize = 16, 1182 .dcache_bsize = 16, 1183 .platform = "ppc823", 1184 }, 1185 #endif /* CONFIG_8xx */ 1186 #ifdef CONFIG_40x 1187 { /* 403GC */ 1188 .pvr_mask = 0xffffff00, 1189 .pvr_value = 0x00200200, 1190 .cpu_name = "403GC", 1191 .cpu_features = CPU_FTRS_40X, 1192 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 1193 .mmu_features = MMU_FTR_TYPE_40x, 1194 .icache_bsize = 16, 1195 .dcache_bsize = 16, 1196 .machine_check = machine_check_4xx, 1197 .platform = "ppc403", 1198 }, 1199 { /* 403GCX */ 1200 .pvr_mask = 0xffffff00, 1201 .pvr_value = 0x00201400, 1202 .cpu_name = "403GCX", 1203 .cpu_features = CPU_FTRS_40X, 1204 .cpu_user_features = PPC_FEATURE_32 | 1205 PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB, 1206 .mmu_features = MMU_FTR_TYPE_40x, 1207 .icache_bsize = 16, 1208 .dcache_bsize = 16, 1209 .machine_check = machine_check_4xx, 1210 .platform = "ppc403", 1211 }, 1212 { /* 403G ?? */ 1213 .pvr_mask = 0xffff0000, 1214 .pvr_value = 0x00200000, 1215 .cpu_name = "403G ??", 1216 .cpu_features = CPU_FTRS_40X, 1217 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 1218 .mmu_features = MMU_FTR_TYPE_40x, 1219 .icache_bsize = 16, 1220 .dcache_bsize = 16, 1221 .machine_check = machine_check_4xx, 1222 .platform = "ppc403", 1223 }, 1224 { /* 405GP */ 1225 .pvr_mask = 0xffff0000, 1226 .pvr_value = 0x40110000, 1227 .cpu_name = "405GP", 1228 .cpu_features = CPU_FTRS_40X, 1229 .cpu_user_features = PPC_FEATURE_32 | 1230 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1231 .mmu_features = MMU_FTR_TYPE_40x, 1232 .icache_bsize = 32, 1233 .dcache_bsize = 32, 1234 .machine_check = machine_check_4xx, 1235 .platform = "ppc405", 1236 }, 1237 { /* STB 03xxx */ 1238 .pvr_mask = 0xffff0000, 1239 .pvr_value = 0x40130000, 1240 .cpu_name = "STB03xxx", 1241 .cpu_features = CPU_FTRS_40X, 1242 .cpu_user_features = PPC_FEATURE_32 | 1243 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1244 .mmu_features = MMU_FTR_TYPE_40x, 1245 .icache_bsize = 32, 1246 .dcache_bsize = 32, 1247 .machine_check = machine_check_4xx, 1248 .platform = "ppc405", 1249 }, 1250 { /* STB 04xxx */ 1251 .pvr_mask = 0xffff0000, 1252 .pvr_value = 0x41810000, 1253 .cpu_name = "STB04xxx", 1254 .cpu_features = CPU_FTRS_40X, 1255 .cpu_user_features = PPC_FEATURE_32 | 1256 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1257 .mmu_features = MMU_FTR_TYPE_40x, 1258 .icache_bsize = 32, 1259 .dcache_bsize = 32, 1260 .machine_check = machine_check_4xx, 1261 .platform = "ppc405", 1262 }, 1263 { /* NP405L */ 1264 .pvr_mask = 0xffff0000, 1265 .pvr_value = 0x41610000, 1266 .cpu_name = "NP405L", 1267 .cpu_features = CPU_FTRS_40X, 1268 .cpu_user_features = PPC_FEATURE_32 | 1269 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1270 .mmu_features = MMU_FTR_TYPE_40x, 1271 .icache_bsize = 32, 1272 .dcache_bsize = 32, 1273 .machine_check = machine_check_4xx, 1274 .platform = "ppc405", 1275 }, 1276 { /* NP4GS3 */ 1277 .pvr_mask = 0xffff0000, 1278 .pvr_value = 0x40B10000, 1279 .cpu_name = "NP4GS3", 1280 .cpu_features = CPU_FTRS_40X, 1281 .cpu_user_features = PPC_FEATURE_32 | 1282 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1283 .mmu_features = MMU_FTR_TYPE_40x, 1284 .icache_bsize = 32, 1285 .dcache_bsize = 32, 1286 .machine_check = machine_check_4xx, 1287 .platform = "ppc405", 1288 }, 1289 { /* NP405H */ 1290 .pvr_mask = 0xffff0000, 1291 .pvr_value = 0x41410000, 1292 .cpu_name = "NP405H", 1293 .cpu_features = CPU_FTRS_40X, 1294 .cpu_user_features = PPC_FEATURE_32 | 1295 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1296 .mmu_features = MMU_FTR_TYPE_40x, 1297 .icache_bsize = 32, 1298 .dcache_bsize = 32, 1299 .machine_check = machine_check_4xx, 1300 .platform = "ppc405", 1301 }, 1302 { /* 405GPr */ 1303 .pvr_mask = 0xffff0000, 1304 .pvr_value = 0x50910000, 1305 .cpu_name = "405GPr", 1306 .cpu_features = CPU_FTRS_40X, 1307 .cpu_user_features = PPC_FEATURE_32 | 1308 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1309 .mmu_features = MMU_FTR_TYPE_40x, 1310 .icache_bsize = 32, 1311 .dcache_bsize = 32, 1312 .machine_check = machine_check_4xx, 1313 .platform = "ppc405", 1314 }, 1315 { /* STBx25xx */ 1316 .pvr_mask = 0xffff0000, 1317 .pvr_value = 0x51510000, 1318 .cpu_name = "STBx25xx", 1319 .cpu_features = CPU_FTRS_40X, 1320 .cpu_user_features = PPC_FEATURE_32 | 1321 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1322 .mmu_features = MMU_FTR_TYPE_40x, 1323 .icache_bsize = 32, 1324 .dcache_bsize = 32, 1325 .machine_check = machine_check_4xx, 1326 .platform = "ppc405", 1327 }, 1328 { /* 405LP */ 1329 .pvr_mask = 0xffff0000, 1330 .pvr_value = 0x41F10000, 1331 .cpu_name = "405LP", 1332 .cpu_features = CPU_FTRS_40X, 1333 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 1334 .mmu_features = MMU_FTR_TYPE_40x, 1335 .icache_bsize = 32, 1336 .dcache_bsize = 32, 1337 .machine_check = machine_check_4xx, 1338 .platform = "ppc405", 1339 }, 1340 { /* Xilinx Virtex-II Pro */ 1341 .pvr_mask = 0xfffff000, 1342 .pvr_value = 0x20010000, 1343 .cpu_name = "Virtex-II Pro", 1344 .cpu_features = CPU_FTRS_40X, 1345 .cpu_user_features = PPC_FEATURE_32 | 1346 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1347 .mmu_features = MMU_FTR_TYPE_40x, 1348 .icache_bsize = 32, 1349 .dcache_bsize = 32, 1350 .machine_check = machine_check_4xx, 1351 .platform = "ppc405", 1352 }, 1353 { /* Xilinx Virtex-4 FX */ 1354 .pvr_mask = 0xfffff000, 1355 .pvr_value = 0x20011000, 1356 .cpu_name = "Virtex-4 FX", 1357 .cpu_features = CPU_FTRS_40X, 1358 .cpu_user_features = PPC_FEATURE_32 | 1359 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1360 .mmu_features = MMU_FTR_TYPE_40x, 1361 .icache_bsize = 32, 1362 .dcache_bsize = 32, 1363 .machine_check = machine_check_4xx, 1364 .platform = "ppc405", 1365 }, 1366 { /* 405EP */ 1367 .pvr_mask = 0xffff0000, 1368 .pvr_value = 0x51210000, 1369 .cpu_name = "405EP", 1370 .cpu_features = CPU_FTRS_40X, 1371 .cpu_user_features = PPC_FEATURE_32 | 1372 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1373 .mmu_features = MMU_FTR_TYPE_40x, 1374 .icache_bsize = 32, 1375 .dcache_bsize = 32, 1376 .machine_check = machine_check_4xx, 1377 .platform = "ppc405", 1378 }, 1379 { /* 405EX Rev. A/B with Security */ 1380 .pvr_mask = 0xffff000f, 1381 .pvr_value = 0x12910007, 1382 .cpu_name = "405EX Rev. A/B", 1383 .cpu_features = CPU_FTRS_40X, 1384 .cpu_user_features = PPC_FEATURE_32 | 1385 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1386 .mmu_features = MMU_FTR_TYPE_40x, 1387 .icache_bsize = 32, 1388 .dcache_bsize = 32, 1389 .machine_check = machine_check_4xx, 1390 .platform = "ppc405", 1391 }, 1392 { /* 405EX Rev. C without Security */ 1393 .pvr_mask = 0xffff000f, 1394 .pvr_value = 0x1291000d, 1395 .cpu_name = "405EX Rev. C", 1396 .cpu_features = CPU_FTRS_40X, 1397 .cpu_user_features = PPC_FEATURE_32 | 1398 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1399 .mmu_features = MMU_FTR_TYPE_40x, 1400 .icache_bsize = 32, 1401 .dcache_bsize = 32, 1402 .machine_check = machine_check_4xx, 1403 .platform = "ppc405", 1404 }, 1405 { /* 405EX Rev. C with Security */ 1406 .pvr_mask = 0xffff000f, 1407 .pvr_value = 0x1291000f, 1408 .cpu_name = "405EX Rev. C", 1409 .cpu_features = CPU_FTRS_40X, 1410 .cpu_user_features = PPC_FEATURE_32 | 1411 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1412 .mmu_features = MMU_FTR_TYPE_40x, 1413 .icache_bsize = 32, 1414 .dcache_bsize = 32, 1415 .machine_check = machine_check_4xx, 1416 .platform = "ppc405", 1417 }, 1418 { /* 405EX Rev. D without Security */ 1419 .pvr_mask = 0xffff000f, 1420 .pvr_value = 0x12910003, 1421 .cpu_name = "405EX Rev. D", 1422 .cpu_features = CPU_FTRS_40X, 1423 .cpu_user_features = PPC_FEATURE_32 | 1424 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1425 .mmu_features = MMU_FTR_TYPE_40x, 1426 .icache_bsize = 32, 1427 .dcache_bsize = 32, 1428 .machine_check = machine_check_4xx, 1429 .platform = "ppc405", 1430 }, 1431 { /* 405EX Rev. D with Security */ 1432 .pvr_mask = 0xffff000f, 1433 .pvr_value = 0x12910005, 1434 .cpu_name = "405EX Rev. D", 1435 .cpu_features = CPU_FTRS_40X, 1436 .cpu_user_features = PPC_FEATURE_32 | 1437 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1438 .mmu_features = MMU_FTR_TYPE_40x, 1439 .icache_bsize = 32, 1440 .dcache_bsize = 32, 1441 .machine_check = machine_check_4xx, 1442 .platform = "ppc405", 1443 }, 1444 { /* 405EXr Rev. A/B without Security */ 1445 .pvr_mask = 0xffff000f, 1446 .pvr_value = 0x12910001, 1447 .cpu_name = "405EXr Rev. A/B", 1448 .cpu_features = CPU_FTRS_40X, 1449 .cpu_user_features = PPC_FEATURE_32 | 1450 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1451 .mmu_features = MMU_FTR_TYPE_40x, 1452 .icache_bsize = 32, 1453 .dcache_bsize = 32, 1454 .machine_check = machine_check_4xx, 1455 .platform = "ppc405", 1456 }, 1457 { /* 405EXr Rev. C without Security */ 1458 .pvr_mask = 0xffff000f, 1459 .pvr_value = 0x12910009, 1460 .cpu_name = "405EXr Rev. C", 1461 .cpu_features = CPU_FTRS_40X, 1462 .cpu_user_features = PPC_FEATURE_32 | 1463 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1464 .mmu_features = MMU_FTR_TYPE_40x, 1465 .icache_bsize = 32, 1466 .dcache_bsize = 32, 1467 .machine_check = machine_check_4xx, 1468 .platform = "ppc405", 1469 }, 1470 { /* 405EXr Rev. C with Security */ 1471 .pvr_mask = 0xffff000f, 1472 .pvr_value = 0x1291000b, 1473 .cpu_name = "405EXr Rev. C", 1474 .cpu_features = CPU_FTRS_40X, 1475 .cpu_user_features = PPC_FEATURE_32 | 1476 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1477 .mmu_features = MMU_FTR_TYPE_40x, 1478 .icache_bsize = 32, 1479 .dcache_bsize = 32, 1480 .machine_check = machine_check_4xx, 1481 .platform = "ppc405", 1482 }, 1483 { /* 405EXr Rev. D without Security */ 1484 .pvr_mask = 0xffff000f, 1485 .pvr_value = 0x12910000, 1486 .cpu_name = "405EXr Rev. D", 1487 .cpu_features = CPU_FTRS_40X, 1488 .cpu_user_features = PPC_FEATURE_32 | 1489 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1490 .mmu_features = MMU_FTR_TYPE_40x, 1491 .icache_bsize = 32, 1492 .dcache_bsize = 32, 1493 .machine_check = machine_check_4xx, 1494 .platform = "ppc405", 1495 }, 1496 { /* 405EXr Rev. D with Security */ 1497 .pvr_mask = 0xffff000f, 1498 .pvr_value = 0x12910002, 1499 .cpu_name = "405EXr Rev. D", 1500 .cpu_features = CPU_FTRS_40X, 1501 .cpu_user_features = PPC_FEATURE_32 | 1502 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1503 .mmu_features = MMU_FTR_TYPE_40x, 1504 .icache_bsize = 32, 1505 .dcache_bsize = 32, 1506 .machine_check = machine_check_4xx, 1507 .platform = "ppc405", 1508 }, 1509 { 1510 /* 405EZ */ 1511 .pvr_mask = 0xffff0000, 1512 .pvr_value = 0x41510000, 1513 .cpu_name = "405EZ", 1514 .cpu_features = CPU_FTRS_40X, 1515 .cpu_user_features = PPC_FEATURE_32 | 1516 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1517 .mmu_features = MMU_FTR_TYPE_40x, 1518 .icache_bsize = 32, 1519 .dcache_bsize = 32, 1520 .machine_check = machine_check_4xx, 1521 .platform = "ppc405", 1522 }, 1523 { /* APM8018X */ 1524 .pvr_mask = 0xffff0000, 1525 .pvr_value = 0x7ff11432, 1526 .cpu_name = "APM8018X", 1527 .cpu_features = CPU_FTRS_40X, 1528 .cpu_user_features = PPC_FEATURE_32 | 1529 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1530 .mmu_features = MMU_FTR_TYPE_40x, 1531 .icache_bsize = 32, 1532 .dcache_bsize = 32, 1533 .machine_check = machine_check_4xx, 1534 .platform = "ppc405", 1535 }, 1536 { /* default match */ 1537 .pvr_mask = 0x00000000, 1538 .pvr_value = 0x00000000, 1539 .cpu_name = "(generic 40x PPC)", 1540 .cpu_features = CPU_FTRS_40X, 1541 .cpu_user_features = PPC_FEATURE_32 | 1542 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1543 .mmu_features = MMU_FTR_TYPE_40x, 1544 .icache_bsize = 32, 1545 .dcache_bsize = 32, 1546 .machine_check = machine_check_4xx, 1547 .platform = "ppc405", 1548 } 1549 1550 #endif /* CONFIG_40x */ 1551 #ifdef CONFIG_44x 1552 { 1553 .pvr_mask = 0xf0000fff, 1554 .pvr_value = 0x40000850, 1555 .cpu_name = "440GR Rev. A", 1556 .cpu_features = CPU_FTRS_44X, 1557 .cpu_user_features = COMMON_USER_BOOKE, 1558 .mmu_features = MMU_FTR_TYPE_44x, 1559 .icache_bsize = 32, 1560 .dcache_bsize = 32, 1561 .machine_check = machine_check_4xx, 1562 .platform = "ppc440", 1563 }, 1564 { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */ 1565 .pvr_mask = 0xf0000fff, 1566 .pvr_value = 0x40000858, 1567 .cpu_name = "440EP Rev. A", 1568 .cpu_features = CPU_FTRS_44X, 1569 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1570 .mmu_features = MMU_FTR_TYPE_44x, 1571 .icache_bsize = 32, 1572 .dcache_bsize = 32, 1573 .cpu_setup = __setup_cpu_440ep, 1574 .machine_check = machine_check_4xx, 1575 .platform = "ppc440", 1576 }, 1577 { 1578 .pvr_mask = 0xf0000fff, 1579 .pvr_value = 0x400008d3, 1580 .cpu_name = "440GR Rev. B", 1581 .cpu_features = CPU_FTRS_44X, 1582 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1583 .mmu_features = MMU_FTR_TYPE_44x, 1584 .icache_bsize = 32, 1585 .dcache_bsize = 32, 1586 .machine_check = machine_check_4xx, 1587 .platform = "ppc440", 1588 }, 1589 { /* Matches both physical and logical PVR for 440EP (logical pvr = pvr | 0x8) */ 1590 .pvr_mask = 0xf0000ff7, 1591 .pvr_value = 0x400008d4, 1592 .cpu_name = "440EP Rev. C", 1593 .cpu_features = CPU_FTRS_44X, 1594 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1595 .mmu_features = MMU_FTR_TYPE_44x, 1596 .icache_bsize = 32, 1597 .dcache_bsize = 32, 1598 .cpu_setup = __setup_cpu_440ep, 1599 .machine_check = machine_check_4xx, 1600 .platform = "ppc440", 1601 }, 1602 { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */ 1603 .pvr_mask = 0xf0000fff, 1604 .pvr_value = 0x400008db, 1605 .cpu_name = "440EP Rev. B", 1606 .cpu_features = CPU_FTRS_44X, 1607 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1608 .mmu_features = MMU_FTR_TYPE_44x, 1609 .icache_bsize = 32, 1610 .dcache_bsize = 32, 1611 .cpu_setup = __setup_cpu_440ep, 1612 .machine_check = machine_check_4xx, 1613 .platform = "ppc440", 1614 }, 1615 { /* 440GRX */ 1616 .pvr_mask = 0xf0000ffb, 1617 .pvr_value = 0x200008D0, 1618 .cpu_name = "440GRX", 1619 .cpu_features = CPU_FTRS_44X, 1620 .cpu_user_features = COMMON_USER_BOOKE, 1621 .mmu_features = MMU_FTR_TYPE_44x, 1622 .icache_bsize = 32, 1623 .dcache_bsize = 32, 1624 .cpu_setup = __setup_cpu_440grx, 1625 .machine_check = machine_check_440A, 1626 .platform = "ppc440", 1627 }, 1628 { /* Use logical PVR for 440EPx (logical pvr = pvr | 0x8) */ 1629 .pvr_mask = 0xf0000ffb, 1630 .pvr_value = 0x200008D8, 1631 .cpu_name = "440EPX", 1632 .cpu_features = CPU_FTRS_44X, 1633 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1634 .mmu_features = MMU_FTR_TYPE_44x, 1635 .icache_bsize = 32, 1636 .dcache_bsize = 32, 1637 .cpu_setup = __setup_cpu_440epx, 1638 .machine_check = machine_check_440A, 1639 .platform = "ppc440", 1640 }, 1641 { /* 440GP Rev. B */ 1642 .pvr_mask = 0xf0000fff, 1643 .pvr_value = 0x40000440, 1644 .cpu_name = "440GP Rev. B", 1645 .cpu_features = CPU_FTRS_44X, 1646 .cpu_user_features = COMMON_USER_BOOKE, 1647 .mmu_features = MMU_FTR_TYPE_44x, 1648 .icache_bsize = 32, 1649 .dcache_bsize = 32, 1650 .machine_check = machine_check_4xx, 1651 .platform = "ppc440gp", 1652 }, 1653 { /* 440GP Rev. C */ 1654 .pvr_mask = 0xf0000fff, 1655 .pvr_value = 0x40000481, 1656 .cpu_name = "440GP Rev. C", 1657 .cpu_features = CPU_FTRS_44X, 1658 .cpu_user_features = COMMON_USER_BOOKE, 1659 .mmu_features = MMU_FTR_TYPE_44x, 1660 .icache_bsize = 32, 1661 .dcache_bsize = 32, 1662 .machine_check = machine_check_4xx, 1663 .platform = "ppc440gp", 1664 }, 1665 { /* 440GX Rev. A */ 1666 .pvr_mask = 0xf0000fff, 1667 .pvr_value = 0x50000850, 1668 .cpu_name = "440GX Rev. A", 1669 .cpu_features = CPU_FTRS_44X, 1670 .cpu_user_features = COMMON_USER_BOOKE, 1671 .mmu_features = MMU_FTR_TYPE_44x, 1672 .icache_bsize = 32, 1673 .dcache_bsize = 32, 1674 .cpu_setup = __setup_cpu_440gx, 1675 .machine_check = machine_check_440A, 1676 .platform = "ppc440", 1677 }, 1678 { /* 440GX Rev. B */ 1679 .pvr_mask = 0xf0000fff, 1680 .pvr_value = 0x50000851, 1681 .cpu_name = "440GX Rev. B", 1682 .cpu_features = CPU_FTRS_44X, 1683 .cpu_user_features = COMMON_USER_BOOKE, 1684 .mmu_features = MMU_FTR_TYPE_44x, 1685 .icache_bsize = 32, 1686 .dcache_bsize = 32, 1687 .cpu_setup = __setup_cpu_440gx, 1688 .machine_check = machine_check_440A, 1689 .platform = "ppc440", 1690 }, 1691 { /* 440GX Rev. C */ 1692 .pvr_mask = 0xf0000fff, 1693 .pvr_value = 0x50000892, 1694 .cpu_name = "440GX Rev. C", 1695 .cpu_features = CPU_FTRS_44X, 1696 .cpu_user_features = COMMON_USER_BOOKE, 1697 .mmu_features = MMU_FTR_TYPE_44x, 1698 .icache_bsize = 32, 1699 .dcache_bsize = 32, 1700 .cpu_setup = __setup_cpu_440gx, 1701 .machine_check = machine_check_440A, 1702 .platform = "ppc440", 1703 }, 1704 { /* 440GX Rev. F */ 1705 .pvr_mask = 0xf0000fff, 1706 .pvr_value = 0x50000894, 1707 .cpu_name = "440GX Rev. F", 1708 .cpu_features = CPU_FTRS_44X, 1709 .cpu_user_features = COMMON_USER_BOOKE, 1710 .mmu_features = MMU_FTR_TYPE_44x, 1711 .icache_bsize = 32, 1712 .dcache_bsize = 32, 1713 .cpu_setup = __setup_cpu_440gx, 1714 .machine_check = machine_check_440A, 1715 .platform = "ppc440", 1716 }, 1717 { /* 440SP Rev. A */ 1718 .pvr_mask = 0xfff00fff, 1719 .pvr_value = 0x53200891, 1720 .cpu_name = "440SP Rev. A", 1721 .cpu_features = CPU_FTRS_44X, 1722 .cpu_user_features = COMMON_USER_BOOKE, 1723 .mmu_features = MMU_FTR_TYPE_44x, 1724 .icache_bsize = 32, 1725 .dcache_bsize = 32, 1726 .machine_check = machine_check_4xx, 1727 .platform = "ppc440", 1728 }, 1729 { /* 440SPe Rev. A */ 1730 .pvr_mask = 0xfff00fff, 1731 .pvr_value = 0x53400890, 1732 .cpu_name = "440SPe Rev. A", 1733 .cpu_features = CPU_FTRS_44X, 1734 .cpu_user_features = COMMON_USER_BOOKE, 1735 .mmu_features = MMU_FTR_TYPE_44x, 1736 .icache_bsize = 32, 1737 .dcache_bsize = 32, 1738 .cpu_setup = __setup_cpu_440spe, 1739 .machine_check = machine_check_440A, 1740 .platform = "ppc440", 1741 }, 1742 { /* 440SPe Rev. B */ 1743 .pvr_mask = 0xfff00fff, 1744 .pvr_value = 0x53400891, 1745 .cpu_name = "440SPe Rev. B", 1746 .cpu_features = CPU_FTRS_44X, 1747 .cpu_user_features = COMMON_USER_BOOKE, 1748 .mmu_features = MMU_FTR_TYPE_44x, 1749 .icache_bsize = 32, 1750 .dcache_bsize = 32, 1751 .cpu_setup = __setup_cpu_440spe, 1752 .machine_check = machine_check_440A, 1753 .platform = "ppc440", 1754 }, 1755 { /* 440 in Xilinx Virtex-5 FXT */ 1756 .pvr_mask = 0xfffffff0, 1757 .pvr_value = 0x7ff21910, 1758 .cpu_name = "440 in Virtex-5 FXT", 1759 .cpu_features = CPU_FTRS_44X, 1760 .cpu_user_features = COMMON_USER_BOOKE, 1761 .mmu_features = MMU_FTR_TYPE_44x, 1762 .icache_bsize = 32, 1763 .dcache_bsize = 32, 1764 .cpu_setup = __setup_cpu_440x5, 1765 .machine_check = machine_check_440A, 1766 .platform = "ppc440", 1767 }, 1768 { /* 460EX */ 1769 .pvr_mask = 0xffff0006, 1770 .pvr_value = 0x13020002, 1771 .cpu_name = "460EX", 1772 .cpu_features = CPU_FTRS_440x6, 1773 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1774 .mmu_features = MMU_FTR_TYPE_44x, 1775 .icache_bsize = 32, 1776 .dcache_bsize = 32, 1777 .cpu_setup = __setup_cpu_460ex, 1778 .machine_check = machine_check_440A, 1779 .platform = "ppc440", 1780 }, 1781 { /* 460EX Rev B */ 1782 .pvr_mask = 0xffff0007, 1783 .pvr_value = 0x13020004, 1784 .cpu_name = "460EX Rev. B", 1785 .cpu_features = CPU_FTRS_440x6, 1786 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1787 .mmu_features = MMU_FTR_TYPE_44x, 1788 .icache_bsize = 32, 1789 .dcache_bsize = 32, 1790 .cpu_setup = __setup_cpu_460ex, 1791 .machine_check = machine_check_440A, 1792 .platform = "ppc440", 1793 }, 1794 { /* 460GT */ 1795 .pvr_mask = 0xffff0006, 1796 .pvr_value = 0x13020000, 1797 .cpu_name = "460GT", 1798 .cpu_features = CPU_FTRS_440x6, 1799 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1800 .mmu_features = MMU_FTR_TYPE_44x, 1801 .icache_bsize = 32, 1802 .dcache_bsize = 32, 1803 .cpu_setup = __setup_cpu_460gt, 1804 .machine_check = machine_check_440A, 1805 .platform = "ppc440", 1806 }, 1807 { /* 460GT Rev B */ 1808 .pvr_mask = 0xffff0007, 1809 .pvr_value = 0x13020005, 1810 .cpu_name = "460GT Rev. B", 1811 .cpu_features = CPU_FTRS_440x6, 1812 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1813 .mmu_features = MMU_FTR_TYPE_44x, 1814 .icache_bsize = 32, 1815 .dcache_bsize = 32, 1816 .cpu_setup = __setup_cpu_460gt, 1817 .machine_check = machine_check_440A, 1818 .platform = "ppc440", 1819 }, 1820 { /* 460SX */ 1821 .pvr_mask = 0xffffff00, 1822 .pvr_value = 0x13541800, 1823 .cpu_name = "460SX", 1824 .cpu_features = CPU_FTRS_44X, 1825 .cpu_user_features = COMMON_USER_BOOKE, 1826 .mmu_features = MMU_FTR_TYPE_44x, 1827 .icache_bsize = 32, 1828 .dcache_bsize = 32, 1829 .cpu_setup = __setup_cpu_460sx, 1830 .machine_check = machine_check_440A, 1831 .platform = "ppc440", 1832 }, 1833 { /* 464 in APM821xx */ 1834 .pvr_mask = 0xfffffff0, 1835 .pvr_value = 0x12C41C80, 1836 .cpu_name = "APM821XX", 1837 .cpu_features = CPU_FTRS_44X, 1838 .cpu_user_features = COMMON_USER_BOOKE | 1839 PPC_FEATURE_HAS_FPU, 1840 .mmu_features = MMU_FTR_TYPE_44x, 1841 .icache_bsize = 32, 1842 .dcache_bsize = 32, 1843 .cpu_setup = __setup_cpu_apm821xx, 1844 .machine_check = machine_check_440A, 1845 .platform = "ppc440", 1846 }, 1847 { /* 476 DD2 core */ 1848 .pvr_mask = 0xffffffff, 1849 .pvr_value = 0x11a52080, 1850 .cpu_name = "476", 1851 .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD2, 1852 .cpu_user_features = COMMON_USER_BOOKE | 1853 PPC_FEATURE_HAS_FPU, 1854 .mmu_features = MMU_FTR_TYPE_47x | 1855 MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL, 1856 .icache_bsize = 32, 1857 .dcache_bsize = 128, 1858 .machine_check = machine_check_47x, 1859 .platform = "ppc470", 1860 }, 1861 { /* 476fpe */ 1862 .pvr_mask = 0xffff0000, 1863 .pvr_value = 0x7ff50000, 1864 .cpu_name = "476fpe", 1865 .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD2, 1866 .cpu_user_features = COMMON_USER_BOOKE | 1867 PPC_FEATURE_HAS_FPU, 1868 .mmu_features = MMU_FTR_TYPE_47x | 1869 MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL, 1870 .icache_bsize = 32, 1871 .dcache_bsize = 128, 1872 .machine_check = machine_check_47x, 1873 .platform = "ppc470", 1874 }, 1875 { /* 476 iss */ 1876 .pvr_mask = 0xffff0000, 1877 .pvr_value = 0x00050000, 1878 .cpu_name = "476", 1879 .cpu_features = CPU_FTRS_47X, 1880 .cpu_user_features = COMMON_USER_BOOKE | 1881 PPC_FEATURE_HAS_FPU, 1882 .mmu_features = MMU_FTR_TYPE_47x | 1883 MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL, 1884 .icache_bsize = 32, 1885 .dcache_bsize = 128, 1886 .machine_check = machine_check_47x, 1887 .platform = "ppc470", 1888 }, 1889 { /* 476 others */ 1890 .pvr_mask = 0xffff0000, 1891 .pvr_value = 0x11a50000, 1892 .cpu_name = "476", 1893 .cpu_features = CPU_FTRS_47X, 1894 .cpu_user_features = COMMON_USER_BOOKE | 1895 PPC_FEATURE_HAS_FPU, 1896 .mmu_features = MMU_FTR_TYPE_47x | 1897 MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL, 1898 .icache_bsize = 32, 1899 .dcache_bsize = 128, 1900 .machine_check = machine_check_47x, 1901 .platform = "ppc470", 1902 }, 1903 { /* default match */ 1904 .pvr_mask = 0x00000000, 1905 .pvr_value = 0x00000000, 1906 .cpu_name = "(generic 44x PPC)", 1907 .cpu_features = CPU_FTRS_44X, 1908 .cpu_user_features = COMMON_USER_BOOKE, 1909 .mmu_features = MMU_FTR_TYPE_44x, 1910 .icache_bsize = 32, 1911 .dcache_bsize = 32, 1912 .machine_check = machine_check_4xx, 1913 .platform = "ppc440", 1914 } 1915 #endif /* CONFIG_44x */ 1916 #ifdef CONFIG_E200 1917 { /* e200z5 */ 1918 .pvr_mask = 0xfff00000, 1919 .pvr_value = 0x81000000, 1920 .cpu_name = "e200z5", 1921 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ 1922 .cpu_features = CPU_FTRS_E200, 1923 .cpu_user_features = COMMON_USER_BOOKE | 1924 PPC_FEATURE_HAS_EFP_SINGLE | 1925 PPC_FEATURE_UNIFIED_CACHE, 1926 .mmu_features = MMU_FTR_TYPE_FSL_E, 1927 .dcache_bsize = 32, 1928 .machine_check = machine_check_e200, 1929 .platform = "ppc5554", 1930 }, 1931 { /* e200z6 */ 1932 .pvr_mask = 0xfff00000, 1933 .pvr_value = 0x81100000, 1934 .cpu_name = "e200z6", 1935 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ 1936 .cpu_features = CPU_FTRS_E200, 1937 .cpu_user_features = COMMON_USER_BOOKE | 1938 PPC_FEATURE_HAS_SPE_COMP | 1939 PPC_FEATURE_HAS_EFP_SINGLE_COMP | 1940 PPC_FEATURE_UNIFIED_CACHE, 1941 .mmu_features = MMU_FTR_TYPE_FSL_E, 1942 .dcache_bsize = 32, 1943 .machine_check = machine_check_e200, 1944 .platform = "ppc5554", 1945 }, 1946 { /* default match */ 1947 .pvr_mask = 0x00000000, 1948 .pvr_value = 0x00000000, 1949 .cpu_name = "(generic E200 PPC)", 1950 .cpu_features = CPU_FTRS_E200, 1951 .cpu_user_features = COMMON_USER_BOOKE | 1952 PPC_FEATURE_HAS_EFP_SINGLE | 1953 PPC_FEATURE_UNIFIED_CACHE, 1954 .mmu_features = MMU_FTR_TYPE_FSL_E, 1955 .dcache_bsize = 32, 1956 .cpu_setup = __setup_cpu_e200, 1957 .machine_check = machine_check_e200, 1958 .platform = "ppc5554", 1959 } 1960 #endif /* CONFIG_E200 */ 1961 #endif /* CONFIG_PPC32 */ 1962 #ifdef CONFIG_E500 1963 #ifdef CONFIG_PPC32 1964 #ifndef CONFIG_PPC_E500MC 1965 { /* e500 */ 1966 .pvr_mask = 0xffff0000, 1967 .pvr_value = 0x80200000, 1968 .cpu_name = "e500", 1969 .cpu_features = CPU_FTRS_E500, 1970 .cpu_user_features = COMMON_USER_BOOKE | 1971 PPC_FEATURE_HAS_SPE_COMP | 1972 PPC_FEATURE_HAS_EFP_SINGLE_COMP, 1973 .cpu_user_features2 = PPC_FEATURE2_ISEL, 1974 .mmu_features = MMU_FTR_TYPE_FSL_E, 1975 .icache_bsize = 32, 1976 .dcache_bsize = 32, 1977 .num_pmcs = 4, 1978 .oprofile_cpu_type = "ppc/e500", 1979 .oprofile_type = PPC_OPROFILE_FSL_EMB, 1980 .cpu_setup = __setup_cpu_e500v1, 1981 .machine_check = machine_check_e500, 1982 .platform = "ppc8540", 1983 }, 1984 { /* e500v2 */ 1985 .pvr_mask = 0xffff0000, 1986 .pvr_value = 0x80210000, 1987 .cpu_name = "e500v2", 1988 .cpu_features = CPU_FTRS_E500_2, 1989 .cpu_user_features = COMMON_USER_BOOKE | 1990 PPC_FEATURE_HAS_SPE_COMP | 1991 PPC_FEATURE_HAS_EFP_SINGLE_COMP | 1992 PPC_FEATURE_HAS_EFP_DOUBLE_COMP, 1993 .cpu_user_features2 = PPC_FEATURE2_ISEL, 1994 .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS, 1995 .icache_bsize = 32, 1996 .dcache_bsize = 32, 1997 .num_pmcs = 4, 1998 .oprofile_cpu_type = "ppc/e500", 1999 .oprofile_type = PPC_OPROFILE_FSL_EMB, 2000 .cpu_setup = __setup_cpu_e500v2, 2001 .machine_check = machine_check_e500, 2002 .platform = "ppc8548", 2003 }, 2004 #else 2005 { /* e500mc */ 2006 .pvr_mask = 0xffff0000, 2007 .pvr_value = 0x80230000, 2008 .cpu_name = "e500mc", 2009 .cpu_features = CPU_FTRS_E500MC, 2010 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 2011 .cpu_user_features2 = PPC_FEATURE2_ISEL, 2012 .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | 2013 MMU_FTR_USE_TLBILX, 2014 .icache_bsize = 64, 2015 .dcache_bsize = 64, 2016 .num_pmcs = 4, 2017 .oprofile_cpu_type = "ppc/e500mc", 2018 .oprofile_type = PPC_OPROFILE_FSL_EMB, 2019 .cpu_setup = __setup_cpu_e500mc, 2020 .machine_check = machine_check_e500mc, 2021 .platform = "ppce500mc", 2022 }, 2023 #endif /* CONFIG_PPC_E500MC */ 2024 #endif /* CONFIG_PPC32 */ 2025 #ifdef CONFIG_PPC_E500MC 2026 { /* e5500 */ 2027 .pvr_mask = 0xffff0000, 2028 .pvr_value = 0x80240000, 2029 .cpu_name = "e5500", 2030 .cpu_features = CPU_FTRS_E5500, 2031 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 2032 .cpu_user_features2 = PPC_FEATURE2_ISEL, 2033 .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | 2034 MMU_FTR_USE_TLBILX, 2035 .icache_bsize = 64, 2036 .dcache_bsize = 64, 2037 .num_pmcs = 4, 2038 .oprofile_cpu_type = "ppc/e500mc", 2039 .oprofile_type = PPC_OPROFILE_FSL_EMB, 2040 .cpu_setup = __setup_cpu_e5500, 2041 #ifndef CONFIG_PPC32 2042 .cpu_restore = __restore_cpu_e5500, 2043 #endif 2044 .machine_check = machine_check_e500mc, 2045 .platform = "ppce5500", 2046 }, 2047 { /* e6500 */ 2048 .pvr_mask = 0xffff0000, 2049 .pvr_value = 0x80400000, 2050 .cpu_name = "e6500", 2051 .cpu_features = CPU_FTRS_E6500, 2052 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU | 2053 PPC_FEATURE_HAS_ALTIVEC_COMP, 2054 .cpu_user_features2 = PPC_FEATURE2_ISEL, 2055 .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | 2056 MMU_FTR_USE_TLBILX, 2057 .icache_bsize = 64, 2058 .dcache_bsize = 64, 2059 .num_pmcs = 6, 2060 .oprofile_cpu_type = "ppc/e6500", 2061 .oprofile_type = PPC_OPROFILE_FSL_EMB, 2062 .cpu_setup = __setup_cpu_e6500, 2063 #ifndef CONFIG_PPC32 2064 .cpu_restore = __restore_cpu_e6500, 2065 #endif 2066 .machine_check = machine_check_e500mc, 2067 .platform = "ppce6500", 2068 }, 2069 #endif /* CONFIG_PPC_E500MC */ 2070 #ifdef CONFIG_PPC32 2071 { /* default match */ 2072 .pvr_mask = 0x00000000, 2073 .pvr_value = 0x00000000, 2074 .cpu_name = "(generic E500 PPC)", 2075 .cpu_features = CPU_FTRS_E500, 2076 .cpu_user_features = COMMON_USER_BOOKE | 2077 PPC_FEATURE_HAS_SPE_COMP | 2078 PPC_FEATURE_HAS_EFP_SINGLE_COMP, 2079 .mmu_features = MMU_FTR_TYPE_FSL_E, 2080 .icache_bsize = 32, 2081 .dcache_bsize = 32, 2082 .machine_check = machine_check_e500, 2083 .platform = "powerpc", 2084 } 2085 #endif /* CONFIG_PPC32 */ 2086 #endif /* CONFIG_E500 */ 2087 }; 2088 2089 static struct cpu_spec the_cpu_spec; 2090 2091 static struct cpu_spec * __init setup_cpu_spec(unsigned long offset, 2092 struct cpu_spec *s) 2093 { 2094 struct cpu_spec *t = &the_cpu_spec; 2095 struct cpu_spec old; 2096 2097 t = PTRRELOC(t); 2098 old = *t; 2099 2100 /* Copy everything, then do fixups */ 2101 *t = *s; 2102 2103 /* 2104 * If we are overriding a previous value derived from the real 2105 * PVR with a new value obtained using a logical PVR value, 2106 * don't modify the performance monitor fields. 2107 */ 2108 if (old.num_pmcs && !s->num_pmcs) { 2109 t->num_pmcs = old.num_pmcs; 2110 t->pmc_type = old.pmc_type; 2111 t->oprofile_type = old.oprofile_type; 2112 t->oprofile_mmcra_sihv = old.oprofile_mmcra_sihv; 2113 t->oprofile_mmcra_sipr = old.oprofile_mmcra_sipr; 2114 t->oprofile_mmcra_clear = old.oprofile_mmcra_clear; 2115 2116 /* 2117 * If we have passed through this logic once before and 2118 * have pulled the default case because the real PVR was 2119 * not found inside cpu_specs[], then we are possibly 2120 * running in compatibility mode. In that case, let the 2121 * oprofiler know which set of compatibility counters to 2122 * pull from by making sure the oprofile_cpu_type string 2123 * is set to that of compatibility mode. If the 2124 * oprofile_cpu_type already has a value, then we are 2125 * possibly overriding a real PVR with a logical one, 2126 * and, in that case, keep the current value for 2127 * oprofile_cpu_type. 2128 */ 2129 if (old.oprofile_cpu_type != NULL) { 2130 t->oprofile_cpu_type = old.oprofile_cpu_type; 2131 t->oprofile_type = old.oprofile_type; 2132 } 2133 } 2134 2135 *PTRRELOC(&cur_cpu_spec) = &the_cpu_spec; 2136 2137 /* 2138 * Set the base platform string once; assumes 2139 * we're called with real pvr first. 2140 */ 2141 if (*PTRRELOC(&powerpc_base_platform) == NULL) 2142 *PTRRELOC(&powerpc_base_platform) = t->platform; 2143 2144 #if defined(CONFIG_PPC64) || defined(CONFIG_BOOKE) 2145 /* ppc64 and booke expect identify_cpu to also call setup_cpu for 2146 * that processor. I will consolidate that at a later time, for now, 2147 * just use #ifdef. We also don't need to PTRRELOC the function 2148 * pointer on ppc64 and booke as we are running at 0 in real mode 2149 * on ppc64 and reloc_offset is always 0 on booke. 2150 */ 2151 if (t->cpu_setup) { 2152 t->cpu_setup(offset, t); 2153 } 2154 #endif /* CONFIG_PPC64 || CONFIG_BOOKE */ 2155 2156 return t; 2157 } 2158 2159 struct cpu_spec * __init identify_cpu(unsigned long offset, unsigned int pvr) 2160 { 2161 struct cpu_spec *s = cpu_specs; 2162 int i; 2163 2164 s = PTRRELOC(s); 2165 2166 for (i = 0; i < ARRAY_SIZE(cpu_specs); i++,s++) { 2167 if ((pvr & s->pvr_mask) == s->pvr_value) 2168 return setup_cpu_spec(offset, s); 2169 } 2170 2171 BUG(); 2172 2173 return NULL; 2174 } 2175