1/* 2 * This file contains low level CPU setup functions. 3 * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org) 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 8 * 2 of the License, or (at your option) any later version. 9 * 10 */ 11 12#include <asm/processor.h> 13#include <asm/page.h> 14#include <asm/cputable.h> 15#include <asm/ppc_asm.h> 16#include <asm/asm-offsets.h> 17#include <asm/cache.h> 18#include <asm/mmu.h> 19#include <asm/feature-fixups.h> 20 21_GLOBAL(__setup_cpu_603) 22 mflr r5 23BEGIN_MMU_FTR_SECTION 24 li r10,0 25 mtspr SPRN_SPRG_603_LRU,r10 /* init SW LRU tracking */ 26END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU) 27 28BEGIN_FTR_SECTION 29 bl __init_fpu_registers 30END_FTR_SECTION_IFCLR(CPU_FTR_FPU_UNAVAILABLE) 31 bl setup_common_caches 32 mtlr r5 33 blr 34_GLOBAL(__setup_cpu_604) 35 mflr r5 36 bl setup_common_caches 37 bl setup_604_hid0 38 mtlr r5 39 blr 40_GLOBAL(__setup_cpu_750) 41 mflr r5 42 bl __init_fpu_registers 43 bl setup_common_caches 44 bl setup_750_7400_hid0 45 mtlr r5 46 blr 47_GLOBAL(__setup_cpu_750cx) 48 mflr r5 49 bl __init_fpu_registers 50 bl setup_common_caches 51 bl setup_750_7400_hid0 52 bl setup_750cx 53 mtlr r5 54 blr 55_GLOBAL(__setup_cpu_750fx) 56 mflr r5 57 bl __init_fpu_registers 58 bl setup_common_caches 59 bl setup_750_7400_hid0 60 bl setup_750fx 61 mtlr r5 62 blr 63_GLOBAL(__setup_cpu_7400) 64 mflr r5 65 bl __init_fpu_registers 66 bl setup_7400_workarounds 67 bl setup_common_caches 68 bl setup_750_7400_hid0 69 mtlr r5 70 blr 71_GLOBAL(__setup_cpu_7410) 72 mflr r5 73 bl __init_fpu_registers 74 bl setup_7410_workarounds 75 bl setup_common_caches 76 bl setup_750_7400_hid0 77 li r3,0 78 mtspr SPRN_L2CR2,r3 79 mtlr r5 80 blr 81_GLOBAL(__setup_cpu_745x) 82 mflr r5 83 bl setup_common_caches 84 bl setup_745x_specifics 85 mtlr r5 86 blr 87 88/* Enable caches for 603's, 604, 750 & 7400 */ 89setup_common_caches: 90 mfspr r11,SPRN_HID0 91 andi. r0,r11,HID0_DCE 92 ori r11,r11,HID0_ICE|HID0_DCE 93 ori r8,r11,HID0_ICFI 94 bne 1f /* don't invalidate the D-cache */ 95 ori r8,r8,HID0_DCI /* unless it wasn't enabled */ 961: sync 97 mtspr SPRN_HID0,r8 /* enable and invalidate caches */ 98 sync 99 mtspr SPRN_HID0,r11 /* enable caches */ 100 sync 101 isync 102 blr 103 104/* 604, 604e, 604ev, ... 105 * Enable superscalar execution & branch history table 106 */ 107setup_604_hid0: 108 mfspr r11,SPRN_HID0 109 ori r11,r11,HID0_SIED|HID0_BHTE 110 ori r8,r11,HID0_BTCD 111 sync 112 mtspr SPRN_HID0,r8 /* flush branch target address cache */ 113 sync /* on 604e/604r */ 114 mtspr SPRN_HID0,r11 115 sync 116 isync 117 blr 118 119/* 7400 <= rev 2.7 and 7410 rev = 1.0 suffer from some 120 * erratas we work around here. 121 * Moto MPC710CE.pdf describes them, those are errata 122 * #3, #4 and #5 123 * Note that we assume the firmware didn't choose to 124 * apply other workarounds (there are other ones documented 125 * in the .pdf). It appear that Apple firmware only works 126 * around #3 and with the same fix we use. We may want to 127 * check if the CPU is using 60x bus mode in which case 128 * the workaround for errata #4 is useless. Also, we may 129 * want to explicitly clear HID0_NOPDST as this is not 130 * needed once we have applied workaround #5 (though it's 131 * not set by Apple's firmware at least). 132 */ 133setup_7400_workarounds: 134 mfpvr r3 135 rlwinm r3,r3,0,20,31 136 cmpwi 0,r3,0x0207 137 ble 1f 138 blr 139setup_7410_workarounds: 140 mfpvr r3 141 rlwinm r3,r3,0,20,31 142 cmpwi 0,r3,0x0100 143 bnelr 1441: 145 mfspr r11,SPRN_MSSSR0 146 /* Errata #3: Set L1OPQ_SIZE to 0x10 */ 147 rlwinm r11,r11,0,9,6 148 oris r11,r11,0x0100 149 /* Errata #4: Set L2MQ_SIZE to 1 (check for MPX mode first ?) */ 150 oris r11,r11,0x0002 151 /* Errata #5: Set DRLT_SIZE to 0x01 */ 152 rlwinm r11,r11,0,5,2 153 oris r11,r11,0x0800 154 sync 155 mtspr SPRN_MSSSR0,r11 156 sync 157 isync 158 blr 159 160/* 740/750/7400/7410 161 * Enable Store Gathering (SGE), Address Broadcast (ABE), 162 * Branch History Table (BHTE), Branch Target ICache (BTIC) 163 * Dynamic Power Management (DPM), Speculative (SPD) 164 * Clear Instruction cache throttling (ICTC) 165 */ 166setup_750_7400_hid0: 167 mfspr r11,SPRN_HID0 168 ori r11,r11,HID0_SGE | HID0_ABE | HID0_BHTE | HID0_BTIC 169 oris r11,r11,HID0_DPM@h 170BEGIN_FTR_SECTION 171 xori r11,r11,HID0_BTIC 172END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC) 173BEGIN_FTR_SECTION 174 xoris r11,r11,HID0_DPM@h /* disable dynamic power mgmt */ 175END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM) 176 li r3,HID0_SPD 177 andc r11,r11,r3 /* clear SPD: enable speculative */ 178 li r3,0 179 mtspr SPRN_ICTC,r3 /* Instruction Cache Throttling off */ 180 isync 181 mtspr SPRN_HID0,r11 182 sync 183 isync 184 blr 185 186/* 750cx specific 187 * Looks like we have to disable NAP feature for some PLL settings... 188 * (waiting for confirmation) 189 */ 190setup_750cx: 191 mfspr r10, SPRN_HID1 192 rlwinm r10,r10,4,28,31 193 cmpwi cr0,r10,7 194 cmpwi cr1,r10,9 195 cmpwi cr2,r10,11 196 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq 197 cror 4*cr0+eq,4*cr0+eq,4*cr2+eq 198 bnelr 199 lwz r6,CPU_SPEC_FEATURES(r4) 200 li r7,CPU_FTR_CAN_NAP 201 andc r6,r6,r7 202 stw r6,CPU_SPEC_FEATURES(r4) 203 blr 204 205/* 750fx specific 206 */ 207setup_750fx: 208 blr 209 210/* MPC 745x 211 * Enable Store Gathering (SGE), Branch Folding (FOLD) 212 * Branch History Table (BHTE), Branch Target ICache (BTIC) 213 * Dynamic Power Management (DPM), Speculative (SPD) 214 * Ensure our data cache instructions really operate. 215 * Timebase has to be running or we wouldn't have made it here, 216 * just ensure we don't disable it. 217 * Clear Instruction cache throttling (ICTC) 218 * Enable L2 HW prefetch 219 */ 220setup_745x_specifics: 221 /* We check for the presence of an L3 cache setup by 222 * the firmware. If any, we disable NAP capability as 223 * it's known to be bogus on rev 2.1 and earlier 224 */ 225BEGIN_FTR_SECTION 226 mfspr r11,SPRN_L3CR 227 andis. r11,r11,L3CR_L3E@h 228 beq 1f 229END_FTR_SECTION_IFSET(CPU_FTR_L3CR) 230 lwz r6,CPU_SPEC_FEATURES(r4) 231 andis. r0,r6,CPU_FTR_L3_DISABLE_NAP@h 232 beq 1f 233 li r7,CPU_FTR_CAN_NAP 234 andc r6,r6,r7 235 stw r6,CPU_SPEC_FEATURES(r4) 2361: 237 mfspr r11,SPRN_HID0 238 239 /* All of the bits we have to set..... 240 */ 241 ori r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE 242 ori r11,r11,HID0_LRSTK | HID0_BTIC 243 oris r11,r11,HID0_DPM@h 244BEGIN_MMU_FTR_SECTION 245 oris r11,r11,HID0_HIGH_BAT@h 246END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS) 247BEGIN_FTR_SECTION 248 xori r11,r11,HID0_BTIC 249END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC) 250BEGIN_FTR_SECTION 251 xoris r11,r11,HID0_DPM@h /* disable dynamic power mgmt */ 252END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM) 253 254 /* All of the bits we have to clear.... 255 */ 256 li r3,HID0_SPD | HID0_NOPDST | HID0_NOPTI 257 andc r11,r11,r3 /* clear SPD: enable speculative */ 258 li r3,0 259 260 mtspr SPRN_ICTC,r3 /* Instruction Cache Throttling off */ 261 isync 262 mtspr SPRN_HID0,r11 263 sync 264 isync 265 266 /* Enable L2 HW prefetch, if L2 is enabled 267 */ 268 mfspr r3,SPRN_L2CR 269 andis. r3,r3,L2CR_L2E@h 270 beqlr 271 mfspr r3,SPRN_MSSCR0 272 ori r3,r3,3 273 sync 274 mtspr SPRN_MSSCR0,r3 275 sync 276 isync 277 blr 278 279/* 280 * Initialize the FPU registers. This is needed to work around an errata 281 * in some 750 cpus where using a not yet initialized FPU register after 282 * power on reset may hang the CPU 283 */ 284_GLOBAL(__init_fpu_registers) 285 mfmsr r10 286 ori r11,r10,MSR_FP 287 mtmsr r11 288 isync 289 addis r9,r3,empty_zero_page@ha 290 addi r9,r9,empty_zero_page@l 291 REST_32FPRS(0,r9) 292 sync 293 mtmsr r10 294 isync 295 blr 296 297 298/* Definitions for the table use to save CPU states */ 299#define CS_HID0 0 300#define CS_HID1 4 301#define CS_HID2 8 302#define CS_MSSCR0 12 303#define CS_MSSSR0 16 304#define CS_ICTRL 20 305#define CS_LDSTCR 24 306#define CS_LDSTDB 28 307#define CS_SIZE 32 308 309 .data 310 .balign L1_CACHE_BYTES 311cpu_state_storage: 312 .space CS_SIZE 313 .balign L1_CACHE_BYTES,0 314 .text 315 316/* Called in normal context to backup CPU 0 state. This 317 * does not include cache settings. This function is also 318 * called for machine sleep. This does not include the MMU 319 * setup, BATs, etc... but rather the "special" registers 320 * like HID0, HID1, MSSCR0, etc... 321 */ 322_GLOBAL(__save_cpu_setup) 323 /* Some CR fields are volatile, we back it up all */ 324 mfcr r7 325 326 /* Get storage ptr */ 327 lis r5,cpu_state_storage@h 328 ori r5,r5,cpu_state_storage@l 329 330 /* Save HID0 (common to all CONFIG_PPC_BOOK3S_32 cpus) */ 331 mfspr r3,SPRN_HID0 332 stw r3,CS_HID0(r5) 333 334 /* Now deal with CPU type dependent registers */ 335 mfspr r3,SPRN_PVR 336 srwi r3,r3,16 337 cmplwi cr0,r3,0x8000 /* 7450 */ 338 cmplwi cr1,r3,0x000c /* 7400 */ 339 cmplwi cr2,r3,0x800c /* 7410 */ 340 cmplwi cr3,r3,0x8001 /* 7455 */ 341 cmplwi cr4,r3,0x8002 /* 7457 */ 342 cmplwi cr5,r3,0x8003 /* 7447A */ 343 cmplwi cr6,r3,0x7000 /* 750FX */ 344 cmplwi cr7,r3,0x8004 /* 7448 */ 345 /* cr1 is 7400 || 7410 */ 346 cror 4*cr1+eq,4*cr1+eq,4*cr2+eq 347 /* cr0 is 74xx */ 348 cror 4*cr0+eq,4*cr0+eq,4*cr3+eq 349 cror 4*cr0+eq,4*cr0+eq,4*cr4+eq 350 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq 351 cror 4*cr0+eq,4*cr0+eq,4*cr5+eq 352 cror 4*cr0+eq,4*cr0+eq,4*cr7+eq 353 bne 1f 354 /* Backup 74xx specific regs */ 355 mfspr r4,SPRN_MSSCR0 356 stw r4,CS_MSSCR0(r5) 357 mfspr r4,SPRN_MSSSR0 358 stw r4,CS_MSSSR0(r5) 359 beq cr1,1f 360 /* Backup 745x specific registers */ 361 mfspr r4,SPRN_HID1 362 stw r4,CS_HID1(r5) 363 mfspr r4,SPRN_ICTRL 364 stw r4,CS_ICTRL(r5) 365 mfspr r4,SPRN_LDSTCR 366 stw r4,CS_LDSTCR(r5) 367 mfspr r4,SPRN_LDSTDB 368 stw r4,CS_LDSTDB(r5) 3691: 370 bne cr6,1f 371 /* Backup 750FX specific registers */ 372 mfspr r4,SPRN_HID1 373 stw r4,CS_HID1(r5) 374 /* If rev 2.x, backup HID2 */ 375 mfspr r3,SPRN_PVR 376 andi. r3,r3,0xff00 377 cmpwi cr0,r3,0x0200 378 bne 1f 379 mfspr r4,SPRN_HID2 380 stw r4,CS_HID2(r5) 3811: 382 mtcr r7 383 blr 384 385/* Called with no MMU context (typically MSR:IR/DR off) to 386 * restore CPU state as backed up by the previous 387 * function. This does not include cache setting 388 */ 389_GLOBAL(__restore_cpu_setup) 390 /* Some CR fields are volatile, we back it up all */ 391 mfcr r7 392 393 /* Get storage ptr */ 394 lis r5,(cpu_state_storage-KERNELBASE)@h 395 ori r5,r5,cpu_state_storage@l 396 397 /* Restore HID0 */ 398 lwz r3,CS_HID0(r5) 399 sync 400 isync 401 mtspr SPRN_HID0,r3 402 sync 403 isync 404 405 /* Now deal with CPU type dependent registers */ 406 mfspr r3,SPRN_PVR 407 srwi r3,r3,16 408 cmplwi cr0,r3,0x8000 /* 7450 */ 409 cmplwi cr1,r3,0x000c /* 7400 */ 410 cmplwi cr2,r3,0x800c /* 7410 */ 411 cmplwi cr3,r3,0x8001 /* 7455 */ 412 cmplwi cr4,r3,0x8002 /* 7457 */ 413 cmplwi cr5,r3,0x8003 /* 7447A */ 414 cmplwi cr6,r3,0x7000 /* 750FX */ 415 cmplwi cr7,r3,0x8004 /* 7448 */ 416 /* cr1 is 7400 || 7410 */ 417 cror 4*cr1+eq,4*cr1+eq,4*cr2+eq 418 /* cr0 is 74xx */ 419 cror 4*cr0+eq,4*cr0+eq,4*cr3+eq 420 cror 4*cr0+eq,4*cr0+eq,4*cr4+eq 421 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq 422 cror 4*cr0+eq,4*cr0+eq,4*cr5+eq 423 cror 4*cr0+eq,4*cr0+eq,4*cr7+eq 424 bne 2f 425 /* Restore 74xx specific regs */ 426 lwz r4,CS_MSSCR0(r5) 427 sync 428 mtspr SPRN_MSSCR0,r4 429 sync 430 isync 431 lwz r4,CS_MSSSR0(r5) 432 sync 433 mtspr SPRN_MSSSR0,r4 434 sync 435 isync 436 bne cr2,1f 437 /* Clear 7410 L2CR2 */ 438 li r4,0 439 mtspr SPRN_L2CR2,r4 4401: beq cr1,2f 441 /* Restore 745x specific registers */ 442 lwz r4,CS_HID1(r5) 443 sync 444 mtspr SPRN_HID1,r4 445 isync 446 sync 447 lwz r4,CS_ICTRL(r5) 448 sync 449 mtspr SPRN_ICTRL,r4 450 isync 451 sync 452 lwz r4,CS_LDSTCR(r5) 453 sync 454 mtspr SPRN_LDSTCR,r4 455 isync 456 sync 457 lwz r4,CS_LDSTDB(r5) 458 sync 459 mtspr SPRN_LDSTDB,r4 460 isync 461 sync 4622: bne cr6,1f 463 /* Restore 750FX specific registers 464 * that is restore HID2 on rev 2.x and PLL config & switch 465 * to PLL 0 on all 466 */ 467 /* If rev 2.x, restore HID2 with low voltage bit cleared */ 468 mfspr r3,SPRN_PVR 469 andi. r3,r3,0xff00 470 cmpwi cr0,r3,0x0200 471 bne 4f 472 lwz r4,CS_HID2(r5) 473 rlwinm r4,r4,0,19,17 474 mtspr SPRN_HID2,r4 475 sync 4764: 477 lwz r4,CS_HID1(r5) 478 rlwinm r5,r4,0,16,14 479 mtspr SPRN_HID1,r5 480 /* Wait for PLL to stabilize */ 481 mftbl r5 4823: mftbl r6 483 sub r6,r6,r5 484 cmplwi cr0,r6,10000 485 ble 3b 486 /* Setup final PLL */ 487 mtspr SPRN_HID1,r4 4881: 489 mtcr r7 490 blr 491 492