1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * This program is used to generate definitions needed by
4  * assembly language modules.
5  *
6  * We use the technique used in the OSF Mach kernel code:
7  * generate asm statements containing #defines,
8  * compile this file to assembler, and then extract the
9  * #defines from the assembly-language output.
10  */
11 
12 #include <linux/compat.h>
13 #include <linux/signal.h>
14 #include <linux/sched.h>
15 #include <linux/kernel.h>
16 #include <linux/errno.h>
17 #include <linux/string.h>
18 #include <linux/types.h>
19 #include <linux/mman.h>
20 #include <linux/mm.h>
21 #include <linux/suspend.h>
22 #include <linux/hrtimer.h>
23 #ifdef CONFIG_PPC64
24 #include <linux/time.h>
25 #include <linux/hardirq.h>
26 #endif
27 #include <linux/kbuild.h>
28 
29 #include <asm/io.h>
30 #include <asm/page.h>
31 #include <asm/processor.h>
32 #include <asm/cputable.h>
33 #include <asm/thread_info.h>
34 #include <asm/rtas.h>
35 #include <asm/vdso_datapage.h>
36 #include <asm/dbell.h>
37 #ifdef CONFIG_PPC64
38 #include <asm/paca.h>
39 #include <asm/lppaca.h>
40 #include <asm/cache.h>
41 #include <asm/mmu.h>
42 #include <asm/hvcall.h>
43 #include <asm/xics.h>
44 #endif
45 #ifdef CONFIG_PPC_POWERNV
46 #include <asm/opal.h>
47 #endif
48 #if defined(CONFIG_KVM) || defined(CONFIG_KVM_GUEST)
49 #include <linux/kvm_host.h>
50 #endif
51 #if defined(CONFIG_KVM) && defined(CONFIG_PPC_BOOK3S)
52 #include <asm/kvm_book3s.h>
53 #include <asm/kvm_ppc.h>
54 #endif
55 
56 #ifdef CONFIG_PPC32
57 #ifdef CONFIG_BOOKE_OR_40x
58 #include "head_booke.h"
59 #endif
60 #endif
61 
62 #if defined(CONFIG_PPC_E500)
63 #include "../mm/mmu_decl.h"
64 #endif
65 
66 #ifdef CONFIG_PPC_8xx
67 #include <asm/fixmap.h>
68 #endif
69 
70 #ifdef CONFIG_XMON
71 #include "../xmon/xmon_bpts.h"
72 #endif
73 
74 #define STACK_PT_REGS_OFFSET(sym, val)	\
75 	DEFINE(sym, STACK_INT_FRAME_REGS + offsetof(struct pt_regs, val))
76 
77 int main(void)
78 {
79 	OFFSET(THREAD, task_struct, thread);
80 	OFFSET(MM, task_struct, mm);
81 #ifdef CONFIG_STACKPROTECTOR
82 	OFFSET(TASK_CANARY, task_struct, stack_canary);
83 #ifdef CONFIG_PPC64
84 	OFFSET(PACA_CANARY, paca_struct, canary);
85 #endif
86 #endif
87 #ifdef CONFIG_PPC32
88 #ifdef CONFIG_PPC_RTAS
89 	OFFSET(RTAS_SP, thread_struct, rtas_sp);
90 #endif
91 #endif /* CONFIG_PPC64 */
92 	OFFSET(TASK_STACK, task_struct, stack);
93 #ifdef CONFIG_SMP
94 	OFFSET(TASK_CPU, task_struct, thread_info.cpu);
95 #endif
96 
97 #ifdef CONFIG_LIVEPATCH_64
98 	OFFSET(TI_livepatch_sp, thread_info, livepatch_sp);
99 #endif
100 
101 	OFFSET(KSP, thread_struct, ksp);
102 	OFFSET(PT_REGS, thread_struct, regs);
103 #ifdef CONFIG_BOOKE
104 	OFFSET(THREAD_NORMSAVES, thread_struct, normsave[0]);
105 #endif
106 #ifdef CONFIG_PPC_FPU
107 	OFFSET(THREAD_FPEXC_MODE, thread_struct, fpexc_mode);
108 	OFFSET(THREAD_FPSTATE, thread_struct, fp_state.fpr);
109 	OFFSET(THREAD_FPSAVEAREA, thread_struct, fp_save_area);
110 #endif
111 	OFFSET(FPSTATE_FPSCR, thread_fp_state, fpscr);
112 	OFFSET(THREAD_LOAD_FP, thread_struct, load_fp);
113 #ifdef CONFIG_ALTIVEC
114 	OFFSET(THREAD_VRSTATE, thread_struct, vr_state.vr);
115 	OFFSET(THREAD_VRSAVEAREA, thread_struct, vr_save_area);
116 	OFFSET(THREAD_USED_VR, thread_struct, used_vr);
117 	OFFSET(VRSTATE_VSCR, thread_vr_state, vscr);
118 	OFFSET(THREAD_LOAD_VEC, thread_struct, load_vec);
119 #endif /* CONFIG_ALTIVEC */
120 #ifdef CONFIG_VSX
121 	OFFSET(THREAD_USED_VSR, thread_struct, used_vsr);
122 #endif /* CONFIG_VSX */
123 #ifdef CONFIG_PPC64
124 	OFFSET(KSP_VSID, thread_struct, ksp_vsid);
125 #else /* CONFIG_PPC64 */
126 	OFFSET(PGDIR, thread_struct, pgdir);
127 	OFFSET(SRR0, thread_struct, srr0);
128 	OFFSET(SRR1, thread_struct, srr1);
129 	OFFSET(DAR, thread_struct, dar);
130 	OFFSET(DSISR, thread_struct, dsisr);
131 #ifdef CONFIG_PPC_BOOK3S_32
132 	OFFSET(THR0, thread_struct, r0);
133 	OFFSET(THR3, thread_struct, r3);
134 	OFFSET(THR4, thread_struct, r4);
135 	OFFSET(THR5, thread_struct, r5);
136 	OFFSET(THR6, thread_struct, r6);
137 	OFFSET(THR8, thread_struct, r8);
138 	OFFSET(THR9, thread_struct, r9);
139 	OFFSET(THR11, thread_struct, r11);
140 	OFFSET(THLR, thread_struct, lr);
141 	OFFSET(THCTR, thread_struct, ctr);
142 	OFFSET(THSR0, thread_struct, sr0);
143 #endif
144 #ifdef CONFIG_SPE
145 	OFFSET(THREAD_EVR0, thread_struct, evr[0]);
146 	OFFSET(THREAD_ACC, thread_struct, acc);
147 	OFFSET(THREAD_USED_SPE, thread_struct, used_spe);
148 #endif /* CONFIG_SPE */
149 #endif /* CONFIG_PPC64 */
150 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER
151 	OFFSET(THREAD_KVM_SVCPU, thread_struct, kvm_shadow_vcpu);
152 #endif
153 #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
154 	OFFSET(THREAD_KVM_VCPU, thread_struct, kvm_vcpu);
155 #endif
156 
157 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
158 	OFFSET(PACATMSCRATCH, paca_struct, tm_scratch);
159 	OFFSET(THREAD_TM_TFHAR, thread_struct, tm_tfhar);
160 	OFFSET(THREAD_TM_TEXASR, thread_struct, tm_texasr);
161 	OFFSET(THREAD_TM_TFIAR, thread_struct, tm_tfiar);
162 	OFFSET(THREAD_TM_TAR, thread_struct, tm_tar);
163 	OFFSET(THREAD_TM_PPR, thread_struct, tm_ppr);
164 	OFFSET(THREAD_TM_DSCR, thread_struct, tm_dscr);
165 	OFFSET(THREAD_TM_AMR, thread_struct, tm_amr);
166 	OFFSET(PT_CKPT_REGS, thread_struct, ckpt_regs);
167 	OFFSET(THREAD_CKVRSTATE, thread_struct, ckvr_state.vr);
168 	OFFSET(THREAD_CKVRSAVE, thread_struct, ckvrsave);
169 	OFFSET(THREAD_CKFPSTATE, thread_struct, ckfp_state.fpr);
170 	/* Local pt_regs on stack in int frame form, plus 16 bytes for TM */
171 	DEFINE(TM_FRAME_SIZE, STACK_INT_FRAME_SIZE + 16);
172 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
173 
174 	OFFSET(TI_LOCAL_FLAGS, thread_info, local_flags);
175 
176 #ifdef CONFIG_PPC64
177 	OFFSET(DCACHEL1BLOCKSIZE, ppc64_caches, l1d.block_size);
178 	OFFSET(DCACHEL1LOGBLOCKSIZE, ppc64_caches, l1d.log_block_size);
179 	/* paca */
180 	OFFSET(PACAPACAINDEX, paca_struct, paca_index);
181 	OFFSET(PACAPROCSTART, paca_struct, cpu_start);
182 	OFFSET(PACAKSAVE, paca_struct, kstack);
183 	OFFSET(PACACURRENT, paca_struct, __current);
184 	DEFINE(PACA_THREAD_INFO, offsetof(struct paca_struct, __current) +
185 				 offsetof(struct task_struct, thread_info));
186 	OFFSET(PACASAVEDMSR, paca_struct, saved_msr);
187 	OFFSET(PACAR1, paca_struct, saved_r1);
188 #ifndef CONFIG_PPC_KERNEL_PCREL
189 	OFFSET(PACATOC, paca_struct, kernel_toc);
190 #endif
191 	OFFSET(PACAKBASE, paca_struct, kernelbase);
192 	OFFSET(PACAKMSR, paca_struct, kernel_msr);
193 #ifdef CONFIG_PPC_BOOK3S_64
194 	OFFSET(PACAHSRR_VALID, paca_struct, hsrr_valid);
195 	OFFSET(PACASRR_VALID, paca_struct, srr_valid);
196 #endif
197 	OFFSET(PACAIRQSOFTMASK, paca_struct, irq_soft_mask);
198 	OFFSET(PACAIRQHAPPENED, paca_struct, irq_happened);
199 	OFFSET(PACA_FTRACE_ENABLED, paca_struct, ftrace_enabled);
200 
201 #ifdef CONFIG_PPC_BOOK3E_64
202 	OFFSET(PACAPGD, paca_struct, pgd);
203 	OFFSET(PACA_KERNELPGD, paca_struct, kernel_pgd);
204 	OFFSET(PACA_EXGEN, paca_struct, exgen);
205 	OFFSET(PACA_EXTLB, paca_struct, extlb);
206 	OFFSET(PACA_EXMC, paca_struct, exmc);
207 	OFFSET(PACA_EXCRIT, paca_struct, excrit);
208 	OFFSET(PACA_EXDBG, paca_struct, exdbg);
209 	OFFSET(PACA_MC_STACK, paca_struct, mc_kstack);
210 	OFFSET(PACA_CRIT_STACK, paca_struct, crit_kstack);
211 	OFFSET(PACA_DBG_STACK, paca_struct, dbg_kstack);
212 	OFFSET(PACA_TCD_PTR, paca_struct, tcd_ptr);
213 
214 	OFFSET(TCD_ESEL_NEXT, tlb_core_data, esel_next);
215 	OFFSET(TCD_ESEL_MAX, tlb_core_data, esel_max);
216 	OFFSET(TCD_ESEL_FIRST, tlb_core_data, esel_first);
217 #endif /* CONFIG_PPC_BOOK3E_64 */
218 
219 #ifdef CONFIG_PPC_BOOK3S_64
220 	OFFSET(PACA_EXGEN, paca_struct, exgen);
221 	OFFSET(PACA_EXMC, paca_struct, exmc);
222 	OFFSET(PACA_EXNMI, paca_struct, exnmi);
223 #ifdef CONFIG_PPC_64S_HASH_MMU
224 	OFFSET(PACA_SLBSHADOWPTR, paca_struct, slb_shadow_ptr);
225 	OFFSET(SLBSHADOW_STACKVSID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid);
226 	OFFSET(SLBSHADOW_STACKESID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].esid);
227 	OFFSET(SLBSHADOW_SAVEAREA, slb_shadow, save_area);
228 #endif
229 	OFFSET(LPPACA_PMCINUSE, lppaca, pmcregs_in_use);
230 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
231 	OFFSET(PACA_PMCINUSE, paca_struct, pmcregs_in_use);
232 #endif
233 	OFFSET(LPPACA_YIELDCOUNT, lppaca, yield_count);
234 #endif /* CONFIG_PPC_BOOK3S_64 */
235 	OFFSET(PACAEMERGSP, paca_struct, emergency_sp);
236 #ifdef CONFIG_PPC_BOOK3S_64
237 	OFFSET(PACAMCEMERGSP, paca_struct, mc_emergency_sp);
238 	OFFSET(PACA_NMI_EMERG_SP, paca_struct, nmi_emergency_sp);
239 	OFFSET(PACA_IN_MCE, paca_struct, in_mce);
240 	OFFSET(PACA_IN_NMI, paca_struct, in_nmi);
241 	OFFSET(PACA_RFI_FLUSH_FALLBACK_AREA, paca_struct, rfi_flush_fallback_area);
242 	OFFSET(PACA_EXRFI, paca_struct, exrfi);
243 	OFFSET(PACA_L1D_FLUSH_SIZE, paca_struct, l1d_flush_size);
244 
245 #endif
246 	OFFSET(PACAHWCPUID, paca_struct, hw_cpu_id);
247 	OFFSET(PACAKEXECSTATE, paca_struct, kexec_state);
248 	OFFSET(PACA_DSCR_DEFAULT, paca_struct, dscr_default);
249 #ifdef CONFIG_PPC64
250 	OFFSET(PACA_EXIT_SAVE_R1, paca_struct, exit_save_r1);
251 #endif
252 #ifdef CONFIG_PPC_BOOK3E_64
253 	OFFSET(PACA_TRAP_SAVE, paca_struct, trap_save);
254 #endif
255 	OFFSET(PACA_SPRG_VDSO, paca_struct, sprg_vdso);
256 #else /* CONFIG_PPC64 */
257 #endif /* CONFIG_PPC64 */
258 
259 	/* RTAS */
260 	OFFSET(RTASBASE, rtas_t, base);
261 	OFFSET(RTASENTRY, rtas_t, entry);
262 
263 	/* Interrupt register frame */
264 	DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE);
265 	DEFINE(SWITCH_FRAME_SIZE, STACK_SWITCH_FRAME_SIZE);
266 	STACK_PT_REGS_OFFSET(GPR0, gpr[0]);
267 	STACK_PT_REGS_OFFSET(GPR1, gpr[1]);
268 	STACK_PT_REGS_OFFSET(GPR2, gpr[2]);
269 	STACK_PT_REGS_OFFSET(GPR3, gpr[3]);
270 	STACK_PT_REGS_OFFSET(GPR4, gpr[4]);
271 	STACK_PT_REGS_OFFSET(GPR5, gpr[5]);
272 	STACK_PT_REGS_OFFSET(GPR6, gpr[6]);
273 	STACK_PT_REGS_OFFSET(GPR7, gpr[7]);
274 	STACK_PT_REGS_OFFSET(GPR8, gpr[8]);
275 	STACK_PT_REGS_OFFSET(GPR9, gpr[9]);
276 	STACK_PT_REGS_OFFSET(GPR10, gpr[10]);
277 	STACK_PT_REGS_OFFSET(GPR11, gpr[11]);
278 	STACK_PT_REGS_OFFSET(GPR12, gpr[12]);
279 	STACK_PT_REGS_OFFSET(GPR13, gpr[13]);
280 	/*
281 	 * Note: these symbols include _ because they overlap with special
282 	 * register names
283 	 */
284 	STACK_PT_REGS_OFFSET(_NIP, nip);
285 	STACK_PT_REGS_OFFSET(_MSR, msr);
286 	STACK_PT_REGS_OFFSET(_CTR, ctr);
287 	STACK_PT_REGS_OFFSET(_LINK, link);
288 	STACK_PT_REGS_OFFSET(_CCR, ccr);
289 	STACK_PT_REGS_OFFSET(_XER, xer);
290 	STACK_PT_REGS_OFFSET(_DAR, dar);
291 	STACK_PT_REGS_OFFSET(_DEAR, dear);
292 	STACK_PT_REGS_OFFSET(_DSISR, dsisr);
293 	STACK_PT_REGS_OFFSET(_ESR, esr);
294 	STACK_PT_REGS_OFFSET(ORIG_GPR3, orig_gpr3);
295 	STACK_PT_REGS_OFFSET(RESULT, result);
296 	STACK_PT_REGS_OFFSET(_TRAP, trap);
297 #ifdef CONFIG_PPC64
298 	STACK_PT_REGS_OFFSET(SOFTE, softe);
299 	STACK_PT_REGS_OFFSET(_PPR, ppr);
300 #endif
301 
302 #ifdef CONFIG_PPC_PKEY
303 	STACK_PT_REGS_OFFSET(STACK_REGS_AMR, amr);
304 	STACK_PT_REGS_OFFSET(STACK_REGS_IAMR, iamr);
305 #endif
306 
307 #if defined(CONFIG_PPC32) && defined(CONFIG_BOOKE)
308 	STACK_PT_REGS_OFFSET(MAS0, mas0);
309 	/* we overload MMUCR for 44x on MAS0 since they are mutually exclusive */
310 	STACK_PT_REGS_OFFSET(MMUCR, mas0);
311 	STACK_PT_REGS_OFFSET(MAS1, mas1);
312 	STACK_PT_REGS_OFFSET(MAS2, mas2);
313 	STACK_PT_REGS_OFFSET(MAS3, mas3);
314 	STACK_PT_REGS_OFFSET(MAS6, mas6);
315 	STACK_PT_REGS_OFFSET(MAS7, mas7);
316 	STACK_PT_REGS_OFFSET(_SRR0, srr0);
317 	STACK_PT_REGS_OFFSET(_SRR1, srr1);
318 	STACK_PT_REGS_OFFSET(_CSRR0, csrr0);
319 	STACK_PT_REGS_OFFSET(_CSRR1, csrr1);
320 	STACK_PT_REGS_OFFSET(_DSRR0, dsrr0);
321 	STACK_PT_REGS_OFFSET(_DSRR1, dsrr1);
322 #endif
323 
324 	/* About the CPU features table */
325 	OFFSET(CPU_SPEC_FEATURES, cpu_spec, cpu_features);
326 	OFFSET(CPU_SPEC_SETUP, cpu_spec, cpu_setup);
327 	OFFSET(CPU_SPEC_RESTORE, cpu_spec, cpu_restore);
328 
329 	OFFSET(pbe_address, pbe, address);
330 	OFFSET(pbe_orig_address, pbe, orig_address);
331 	OFFSET(pbe_next, pbe, next);
332 
333 #ifndef CONFIG_PPC64
334 	DEFINE(TASK_SIZE, TASK_SIZE);
335 	DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28);
336 #endif /* ! CONFIG_PPC64 */
337 
338 	/* datapage offsets for use by vdso */
339 	OFFSET(VDSO_DATA_OFFSET, vdso_arch_data, data);
340 	OFFSET(CFG_TB_TICKS_PER_SEC, vdso_arch_data, tb_ticks_per_sec);
341 #ifdef CONFIG_PPC64
342 	OFFSET(CFG_ICACHE_BLOCKSZ, vdso_arch_data, icache_block_size);
343 	OFFSET(CFG_DCACHE_BLOCKSZ, vdso_arch_data, dcache_block_size);
344 	OFFSET(CFG_ICACHE_LOGBLOCKSZ, vdso_arch_data, icache_log_block_size);
345 	OFFSET(CFG_DCACHE_LOGBLOCKSZ, vdso_arch_data, dcache_log_block_size);
346 	OFFSET(CFG_SYSCALL_MAP64, vdso_arch_data, syscall_map);
347 	OFFSET(CFG_SYSCALL_MAP32, vdso_arch_data, compat_syscall_map);
348 #else
349 	OFFSET(CFG_SYSCALL_MAP32, vdso_arch_data, syscall_map);
350 #endif
351 
352 #ifdef CONFIG_BUG
353 	DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry));
354 #endif
355 
356 #ifdef CONFIG_KVM
357 	OFFSET(VCPU_HOST_STACK, kvm_vcpu, arch.host_stack);
358 	OFFSET(VCPU_HOST_PID, kvm_vcpu, arch.host_pid);
359 	OFFSET(VCPU_GUEST_PID, kvm_vcpu, arch.pid);
360 	OFFSET(VCPU_GPRS, kvm_vcpu, arch.regs.gpr);
361 	OFFSET(VCPU_VRSAVE, kvm_vcpu, arch.vrsave);
362 	OFFSET(VCPU_FPRS, kvm_vcpu, arch.fp.fpr);
363 #ifdef CONFIG_ALTIVEC
364 	OFFSET(VCPU_VRS, kvm_vcpu, arch.vr.vr);
365 #endif
366 	OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer);
367 	OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr);
368 	OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link);
369 #ifdef CONFIG_PPC_BOOK3S
370 	OFFSET(VCPU_TAR, kvm_vcpu, arch.tar);
371 #endif
372 	OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr);
373 	OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip);
374 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
375 	OFFSET(VCPU_MSR, kvm_vcpu, arch.shregs.msr);
376 	OFFSET(VCPU_SRR0, kvm_vcpu, arch.shregs.srr0);
377 	OFFSET(VCPU_SRR1, kvm_vcpu, arch.shregs.srr1);
378 	OFFSET(VCPU_SPRG0, kvm_vcpu, arch.shregs.sprg0);
379 	OFFSET(VCPU_SPRG1, kvm_vcpu, arch.shregs.sprg1);
380 	OFFSET(VCPU_SPRG2, kvm_vcpu, arch.shregs.sprg2);
381 	OFFSET(VCPU_SPRG3, kvm_vcpu, arch.shregs.sprg3);
382 #endif
383 #ifdef CONFIG_KVM_BOOK3S_HV_P8_TIMING
384 	OFFSET(VCPU_TB_RMENTRY, kvm_vcpu, arch.rm_entry);
385 	OFFSET(VCPU_TB_RMINTR, kvm_vcpu, arch.rm_intr);
386 	OFFSET(VCPU_TB_RMEXIT, kvm_vcpu, arch.rm_exit);
387 	OFFSET(VCPU_TB_GUEST, kvm_vcpu, arch.guest_time);
388 	OFFSET(VCPU_TB_CEDE, kvm_vcpu, arch.cede_time);
389 	OFFSET(VCPU_CUR_ACTIVITY, kvm_vcpu, arch.cur_activity);
390 	OFFSET(VCPU_ACTIVITY_START, kvm_vcpu, arch.cur_tb_start);
391 	OFFSET(TAS_SEQCOUNT, kvmhv_tb_accumulator, seqcount);
392 	OFFSET(TAS_TOTAL, kvmhv_tb_accumulator, tb_total);
393 	OFFSET(TAS_MIN, kvmhv_tb_accumulator, tb_min);
394 	OFFSET(TAS_MAX, kvmhv_tb_accumulator, tb_max);
395 #endif
396 	OFFSET(VCPU_SHARED_SPRG3, kvm_vcpu_arch_shared, sprg3);
397 	OFFSET(VCPU_SHARED_SPRG4, kvm_vcpu_arch_shared, sprg4);
398 	OFFSET(VCPU_SHARED_SPRG5, kvm_vcpu_arch_shared, sprg5);
399 	OFFSET(VCPU_SHARED_SPRG6, kvm_vcpu_arch_shared, sprg6);
400 	OFFSET(VCPU_SHARED_SPRG7, kvm_vcpu_arch_shared, sprg7);
401 	OFFSET(VCPU_SHADOW_PID, kvm_vcpu, arch.shadow_pid);
402 	OFFSET(VCPU_SHADOW_PID1, kvm_vcpu, arch.shadow_pid1);
403 	OFFSET(VCPU_SHARED, kvm_vcpu, arch.shared);
404 	OFFSET(VCPU_SHARED_MSR, kvm_vcpu_arch_shared, msr);
405 	OFFSET(VCPU_SHADOW_MSR, kvm_vcpu, arch.shadow_msr);
406 #if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_KVM_BOOK3S_PR_POSSIBLE)
407 	OFFSET(VCPU_SHAREDBE, kvm_vcpu, arch.shared_big_endian);
408 #endif
409 
410 	OFFSET(VCPU_SHARED_MAS0, kvm_vcpu_arch_shared, mas0);
411 	OFFSET(VCPU_SHARED_MAS1, kvm_vcpu_arch_shared, mas1);
412 	OFFSET(VCPU_SHARED_MAS2, kvm_vcpu_arch_shared, mas2);
413 	OFFSET(VCPU_SHARED_MAS7_3, kvm_vcpu_arch_shared, mas7_3);
414 	OFFSET(VCPU_SHARED_MAS4, kvm_vcpu_arch_shared, mas4);
415 	OFFSET(VCPU_SHARED_MAS6, kvm_vcpu_arch_shared, mas6);
416 
417 	OFFSET(VCPU_KVM, kvm_vcpu, kvm);
418 	OFFSET(KVM_LPID, kvm, arch.lpid);
419 
420 	/* book3s */
421 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
422 	OFFSET(KVM_SDR1, kvm, arch.sdr1);
423 	OFFSET(KVM_HOST_LPID, kvm, arch.host_lpid);
424 	OFFSET(KVM_HOST_LPCR, kvm, arch.host_lpcr);
425 	OFFSET(KVM_HOST_SDR1, kvm, arch.host_sdr1);
426 	OFFSET(KVM_ENABLED_HCALLS, kvm, arch.enabled_hcalls);
427 	OFFSET(KVM_VRMA_SLB_V, kvm, arch.vrma_slb_v);
428 	OFFSET(KVM_SECURE_GUEST, kvm, arch.secure_guest);
429 	OFFSET(VCPU_DSISR, kvm_vcpu, arch.shregs.dsisr);
430 	OFFSET(VCPU_DAR, kvm_vcpu, arch.shregs.dar);
431 	OFFSET(VCPU_VPA, kvm_vcpu, arch.vpa.pinned_addr);
432 	OFFSET(VCPU_VPA_DIRTY, kvm_vcpu, arch.vpa.dirty);
433 	OFFSET(VCPU_HEIR, kvm_vcpu, arch.emul_inst);
434 	OFFSET(VCPU_CPU, kvm_vcpu, cpu);
435 	OFFSET(VCPU_THREAD_CPU, kvm_vcpu, arch.thread_cpu);
436 #endif
437 #ifdef CONFIG_PPC_BOOK3S
438 	OFFSET(VCPU_PURR, kvm_vcpu, arch.purr);
439 	OFFSET(VCPU_SPURR, kvm_vcpu, arch.spurr);
440 	OFFSET(VCPU_IC, kvm_vcpu, arch.ic);
441 	OFFSET(VCPU_DSCR, kvm_vcpu, arch.dscr);
442 	OFFSET(VCPU_AMR, kvm_vcpu, arch.amr);
443 	OFFSET(VCPU_UAMOR, kvm_vcpu, arch.uamor);
444 	OFFSET(VCPU_IAMR, kvm_vcpu, arch.iamr);
445 	OFFSET(VCPU_CTRL, kvm_vcpu, arch.ctrl);
446 	OFFSET(VCPU_DABR, kvm_vcpu, arch.dabr);
447 	OFFSET(VCPU_DABRX, kvm_vcpu, arch.dabrx);
448 	OFFSET(VCPU_DAWR0, kvm_vcpu, arch.dawr0);
449 	OFFSET(VCPU_DAWRX0, kvm_vcpu, arch.dawrx0);
450 	OFFSET(VCPU_CIABR, kvm_vcpu, arch.ciabr);
451 	OFFSET(VCPU_HFLAGS, kvm_vcpu, arch.hflags);
452 	OFFSET(VCPU_DEC_EXPIRES, kvm_vcpu, arch.dec_expires);
453 	OFFSET(VCPU_PENDING_EXC, kvm_vcpu, arch.pending_exceptions);
454 	OFFSET(VCPU_CEDED, kvm_vcpu, arch.ceded);
455 	OFFSET(VCPU_PRODDED, kvm_vcpu, arch.prodded);
456 	OFFSET(VCPU_MMCR, kvm_vcpu, arch.mmcr);
457 	OFFSET(VCPU_MMCRA, kvm_vcpu, arch.mmcra);
458 	OFFSET(VCPU_MMCRS, kvm_vcpu, arch.mmcrs);
459 	OFFSET(VCPU_PMC, kvm_vcpu, arch.pmc);
460 	OFFSET(VCPU_SIAR, kvm_vcpu, arch.siar);
461 	OFFSET(VCPU_SDAR, kvm_vcpu, arch.sdar);
462 	OFFSET(VCPU_SIER, kvm_vcpu, arch.sier);
463 	OFFSET(VCPU_SLB, kvm_vcpu, arch.slb);
464 	OFFSET(VCPU_SLB_MAX, kvm_vcpu, arch.slb_max);
465 	OFFSET(VCPU_SLB_NR, kvm_vcpu, arch.slb_nr);
466 	OFFSET(VCPU_FAULT_DSISR, kvm_vcpu, arch.fault_dsisr);
467 	OFFSET(VCPU_FAULT_DAR, kvm_vcpu, arch.fault_dar);
468 	OFFSET(VCPU_INTR_MSR, kvm_vcpu, arch.intr_msr);
469 	OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
470 	OFFSET(VCPU_TRAP, kvm_vcpu, arch.trap);
471 	OFFSET(VCPU_CFAR, kvm_vcpu, arch.cfar);
472 	OFFSET(VCPU_PPR, kvm_vcpu, arch.ppr);
473 	OFFSET(VCPU_FSCR, kvm_vcpu, arch.fscr);
474 	OFFSET(VCPU_PSPB, kvm_vcpu, arch.pspb);
475 	OFFSET(VCPU_EBBHR, kvm_vcpu, arch.ebbhr);
476 	OFFSET(VCPU_EBBRR, kvm_vcpu, arch.ebbrr);
477 	OFFSET(VCPU_BESCR, kvm_vcpu, arch.bescr);
478 	OFFSET(VCPU_CSIGR, kvm_vcpu, arch.csigr);
479 	OFFSET(VCPU_TACR, kvm_vcpu, arch.tacr);
480 	OFFSET(VCPU_TCSCR, kvm_vcpu, arch.tcscr);
481 	OFFSET(VCPU_ACOP, kvm_vcpu, arch.acop);
482 	OFFSET(VCPU_WORT, kvm_vcpu, arch.wort);
483 	OFFSET(VCPU_HFSCR, kvm_vcpu, arch.hfscr);
484 	OFFSET(VCORE_ENTRY_EXIT, kvmppc_vcore, entry_exit_map);
485 	OFFSET(VCORE_IN_GUEST, kvmppc_vcore, in_guest);
486 	OFFSET(VCORE_NAPPING_THREADS, kvmppc_vcore, napping_threads);
487 	OFFSET(VCORE_KVM, kvmppc_vcore, kvm);
488 	OFFSET(VCORE_TB_OFFSET, kvmppc_vcore, tb_offset);
489 	OFFSET(VCORE_TB_OFFSET_APPL, kvmppc_vcore, tb_offset_applied);
490 	OFFSET(VCORE_LPCR, kvmppc_vcore, lpcr);
491 	OFFSET(VCORE_PCR, kvmppc_vcore, pcr);
492 	OFFSET(VCORE_DPDES, kvmppc_vcore, dpdes);
493 	OFFSET(VCORE_VTB, kvmppc_vcore, vtb);
494 	OFFSET(VCPU_SLB_E, kvmppc_slb, orige);
495 	OFFSET(VCPU_SLB_V, kvmppc_slb, origv);
496 	DEFINE(VCPU_SLB_SIZE, sizeof(struct kvmppc_slb));
497 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
498 	OFFSET(VCPU_TFHAR, kvm_vcpu, arch.tfhar);
499 	OFFSET(VCPU_TFIAR, kvm_vcpu, arch.tfiar);
500 	OFFSET(VCPU_TEXASR, kvm_vcpu, arch.texasr);
501 	OFFSET(VCPU_ORIG_TEXASR, kvm_vcpu, arch.orig_texasr);
502 	OFFSET(VCPU_GPR_TM, kvm_vcpu, arch.gpr_tm);
503 	OFFSET(VCPU_FPRS_TM, kvm_vcpu, arch.fp_tm.fpr);
504 	OFFSET(VCPU_VRS_TM, kvm_vcpu, arch.vr_tm.vr);
505 	OFFSET(VCPU_VRSAVE_TM, kvm_vcpu, arch.vrsave_tm);
506 	OFFSET(VCPU_CR_TM, kvm_vcpu, arch.cr_tm);
507 	OFFSET(VCPU_XER_TM, kvm_vcpu, arch.xer_tm);
508 	OFFSET(VCPU_LR_TM, kvm_vcpu, arch.lr_tm);
509 	OFFSET(VCPU_CTR_TM, kvm_vcpu, arch.ctr_tm);
510 	OFFSET(VCPU_AMR_TM, kvm_vcpu, arch.amr_tm);
511 	OFFSET(VCPU_PPR_TM, kvm_vcpu, arch.ppr_tm);
512 	OFFSET(VCPU_DSCR_TM, kvm_vcpu, arch.dscr_tm);
513 	OFFSET(VCPU_TAR_TM, kvm_vcpu, arch.tar_tm);
514 #endif
515 
516 #ifdef CONFIG_PPC_BOOK3S_64
517 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
518 	OFFSET(PACA_SVCPU, paca_struct, shadow_vcpu);
519 # define SVCPU_FIELD(x, f)	DEFINE(x, offsetof(struct paca_struct, shadow_vcpu.f))
520 #else
521 # define SVCPU_FIELD(x, f)
522 #endif
523 # define HSTATE_FIELD(x, f)	DEFINE(x, offsetof(struct paca_struct, kvm_hstate.f))
524 #else	/* 32-bit */
525 # define SVCPU_FIELD(x, f)	DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, f))
526 # define HSTATE_FIELD(x, f)	DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, hstate.f))
527 #endif
528 
529 	SVCPU_FIELD(SVCPU_CR, cr);
530 	SVCPU_FIELD(SVCPU_XER, xer);
531 	SVCPU_FIELD(SVCPU_CTR, ctr);
532 	SVCPU_FIELD(SVCPU_LR, lr);
533 	SVCPU_FIELD(SVCPU_PC, pc);
534 	SVCPU_FIELD(SVCPU_R0, gpr[0]);
535 	SVCPU_FIELD(SVCPU_R1, gpr[1]);
536 	SVCPU_FIELD(SVCPU_R2, gpr[2]);
537 	SVCPU_FIELD(SVCPU_R3, gpr[3]);
538 	SVCPU_FIELD(SVCPU_R4, gpr[4]);
539 	SVCPU_FIELD(SVCPU_R5, gpr[5]);
540 	SVCPU_FIELD(SVCPU_R6, gpr[6]);
541 	SVCPU_FIELD(SVCPU_R7, gpr[7]);
542 	SVCPU_FIELD(SVCPU_R8, gpr[8]);
543 	SVCPU_FIELD(SVCPU_R9, gpr[9]);
544 	SVCPU_FIELD(SVCPU_R10, gpr[10]);
545 	SVCPU_FIELD(SVCPU_R11, gpr[11]);
546 	SVCPU_FIELD(SVCPU_R12, gpr[12]);
547 	SVCPU_FIELD(SVCPU_R13, gpr[13]);
548 	SVCPU_FIELD(SVCPU_FAULT_DSISR, fault_dsisr);
549 	SVCPU_FIELD(SVCPU_FAULT_DAR, fault_dar);
550 	SVCPU_FIELD(SVCPU_LAST_INST, last_inst);
551 	SVCPU_FIELD(SVCPU_SHADOW_SRR1, shadow_srr1);
552 #ifdef CONFIG_PPC_BOOK3S_32
553 	SVCPU_FIELD(SVCPU_SR, sr);
554 #endif
555 #ifdef CONFIG_PPC64
556 	SVCPU_FIELD(SVCPU_SLB, slb);
557 	SVCPU_FIELD(SVCPU_SLB_MAX, slb_max);
558 	SVCPU_FIELD(SVCPU_SHADOW_FSCR, shadow_fscr);
559 #endif
560 
561 	HSTATE_FIELD(HSTATE_HOST_R1, host_r1);
562 	HSTATE_FIELD(HSTATE_HOST_R2, host_r2);
563 	HSTATE_FIELD(HSTATE_HOST_MSR, host_msr);
564 	HSTATE_FIELD(HSTATE_VMHANDLER, vmhandler);
565 	HSTATE_FIELD(HSTATE_SCRATCH0, scratch0);
566 	HSTATE_FIELD(HSTATE_SCRATCH1, scratch1);
567 	HSTATE_FIELD(HSTATE_SCRATCH2, scratch2);
568 	HSTATE_FIELD(HSTATE_IN_GUEST, in_guest);
569 	HSTATE_FIELD(HSTATE_RESTORE_HID5, restore_hid5);
570 	HSTATE_FIELD(HSTATE_NAPPING, napping);
571 
572 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
573 	HSTATE_FIELD(HSTATE_HWTHREAD_REQ, hwthread_req);
574 	HSTATE_FIELD(HSTATE_HWTHREAD_STATE, hwthread_state);
575 	HSTATE_FIELD(HSTATE_KVM_VCPU, kvm_vcpu);
576 	HSTATE_FIELD(HSTATE_KVM_VCORE, kvm_vcore);
577 	HSTATE_FIELD(HSTATE_HOST_IPI, host_ipi);
578 	HSTATE_FIELD(HSTATE_PTID, ptid);
579 	HSTATE_FIELD(HSTATE_FAKE_SUSPEND, fake_suspend);
580 	HSTATE_FIELD(HSTATE_MMCR0, host_mmcr[0]);
581 	HSTATE_FIELD(HSTATE_MMCR1, host_mmcr[1]);
582 	HSTATE_FIELD(HSTATE_MMCRA, host_mmcr[2]);
583 	HSTATE_FIELD(HSTATE_SIAR, host_mmcr[3]);
584 	HSTATE_FIELD(HSTATE_SDAR, host_mmcr[4]);
585 	HSTATE_FIELD(HSTATE_MMCR2, host_mmcr[5]);
586 	HSTATE_FIELD(HSTATE_SIER, host_mmcr[6]);
587 	HSTATE_FIELD(HSTATE_PMC1, host_pmc[0]);
588 	HSTATE_FIELD(HSTATE_PMC2, host_pmc[1]);
589 	HSTATE_FIELD(HSTATE_PMC3, host_pmc[2]);
590 	HSTATE_FIELD(HSTATE_PMC4, host_pmc[3]);
591 	HSTATE_FIELD(HSTATE_PMC5, host_pmc[4]);
592 	HSTATE_FIELD(HSTATE_PMC6, host_pmc[5]);
593 	HSTATE_FIELD(HSTATE_PURR, host_purr);
594 	HSTATE_FIELD(HSTATE_SPURR, host_spurr);
595 	HSTATE_FIELD(HSTATE_DSCR, host_dscr);
596 	HSTATE_FIELD(HSTATE_DABR, dabr);
597 	HSTATE_FIELD(HSTATE_DECEXP, dec_expires);
598 	HSTATE_FIELD(HSTATE_SPLIT_MODE, kvm_split_mode);
599 	DEFINE(IPI_PRIORITY, IPI_PRIORITY);
600 	OFFSET(KVM_SPLIT_RPR, kvm_split_mode, rpr);
601 	OFFSET(KVM_SPLIT_PMMAR, kvm_split_mode, pmmar);
602 	OFFSET(KVM_SPLIT_LDBAR, kvm_split_mode, ldbar);
603 	OFFSET(KVM_SPLIT_DO_NAP, kvm_split_mode, do_nap);
604 	OFFSET(KVM_SPLIT_NAPPED, kvm_split_mode, napped);
605 #endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
606 
607 #ifdef CONFIG_PPC_BOOK3S_64
608 	HSTATE_FIELD(HSTATE_CFAR, cfar);
609 	HSTATE_FIELD(HSTATE_PPR, ppr);
610 	HSTATE_FIELD(HSTATE_HOST_FSCR, host_fscr);
611 #endif /* CONFIG_PPC_BOOK3S_64 */
612 
613 #else /* CONFIG_PPC_BOOK3S */
614 	OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr);
615 	OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer);
616 	OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link);
617 	OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr);
618 	OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip);
619 	OFFSET(VCPU_SPRG9, kvm_vcpu, arch.sprg9);
620 	OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
621 	OFFSET(VCPU_FAULT_DEAR, kvm_vcpu, arch.fault_dear);
622 	OFFSET(VCPU_FAULT_ESR, kvm_vcpu, arch.fault_esr);
623 	OFFSET(VCPU_CRIT_SAVE, kvm_vcpu, arch.crit_save);
624 #endif /* CONFIG_PPC_BOOK3S */
625 #endif /* CONFIG_KVM */
626 
627 #ifdef CONFIG_KVM_GUEST
628 	OFFSET(KVM_MAGIC_SCRATCH1, kvm_vcpu_arch_shared, scratch1);
629 	OFFSET(KVM_MAGIC_SCRATCH2, kvm_vcpu_arch_shared, scratch2);
630 	OFFSET(KVM_MAGIC_SCRATCH3, kvm_vcpu_arch_shared, scratch3);
631 	OFFSET(KVM_MAGIC_INT, kvm_vcpu_arch_shared, int_pending);
632 	OFFSET(KVM_MAGIC_MSR, kvm_vcpu_arch_shared, msr);
633 	OFFSET(KVM_MAGIC_CRITICAL, kvm_vcpu_arch_shared, critical);
634 	OFFSET(KVM_MAGIC_SR, kvm_vcpu_arch_shared, sr);
635 #endif
636 
637 #ifdef CONFIG_44x
638 	DEFINE(PGD_T_LOG2, PGD_T_LOG2);
639 	DEFINE(PTE_T_LOG2, PTE_T_LOG2);
640 #endif
641 #ifdef CONFIG_PPC_E500
642 	DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
643 	OFFSET(TLBCAM_MAS0, tlbcam, MAS0);
644 	OFFSET(TLBCAM_MAS1, tlbcam, MAS1);
645 	OFFSET(TLBCAM_MAS2, tlbcam, MAS2);
646 	OFFSET(TLBCAM_MAS3, tlbcam, MAS3);
647 	OFFSET(TLBCAM_MAS7, tlbcam, MAS7);
648 #endif
649 
650 #if defined(CONFIG_KVM) && defined(CONFIG_SPE)
651 	OFFSET(VCPU_EVR, kvm_vcpu, arch.evr[0]);
652 	OFFSET(VCPU_ACC, kvm_vcpu, arch.acc);
653 	OFFSET(VCPU_SPEFSCR, kvm_vcpu, arch.spefscr);
654 	OFFSET(VCPU_HOST_SPEFSCR, kvm_vcpu, arch.host_spefscr);
655 #endif
656 
657 #ifdef CONFIG_KVM_BOOKE_HV
658 	OFFSET(VCPU_HOST_MAS4, kvm_vcpu, arch.host_mas4);
659 	OFFSET(VCPU_HOST_MAS6, kvm_vcpu, arch.host_mas6);
660 #endif
661 
662 #ifdef CONFIG_KVM_EXIT_TIMING
663 	OFFSET(VCPU_TIMING_EXIT_TBU, kvm_vcpu, arch.timing_exit.tv32.tbu);
664 	OFFSET(VCPU_TIMING_EXIT_TBL, kvm_vcpu, arch.timing_exit.tv32.tbl);
665 	OFFSET(VCPU_TIMING_LAST_ENTER_TBU, kvm_vcpu, arch.timing_last_enter.tv32.tbu);
666 	OFFSET(VCPU_TIMING_LAST_ENTER_TBL, kvm_vcpu, arch.timing_last_enter.tv32.tbl);
667 #endif
668 
669 	DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER);
670 
671 #ifdef CONFIG_PPC_8xx
672 	DEFINE(VIRT_IMMR_BASE, (u64)__fix_to_virt(FIX_IMMR_BASE));
673 #endif
674 
675 #ifdef CONFIG_XMON
676 	DEFINE(BPT_SIZE, BPT_SIZE);
677 #endif
678 
679 	return 0;
680 }
681