1 /* align.c - handle alignment exceptions for the Power PC. 2 * 3 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> 4 * Copyright (c) 1998-1999 TiVo, Inc. 5 * PowerPC 403GCX modifications. 6 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> 7 * PowerPC 403GCX/405GP modifications. 8 * Copyright (c) 2001-2002 PPC64 team, IBM Corp 9 * 64-bit and Power4 support 10 * Copyright (c) 2005 Benjamin Herrenschmidt, IBM Corp 11 * <benh@kernel.crashing.org> 12 * Merge ppc32 and ppc64 implementations 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License 16 * as published by the Free Software Foundation; either version 17 * 2 of the License, or (at your option) any later version. 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/mm.h> 22 #include <asm/processor.h> 23 #include <asm/uaccess.h> 24 #include <asm/cache.h> 25 #include <asm/cputable.h> 26 #include <asm/emulated_ops.h> 27 #include <asm/switch_to.h> 28 29 struct aligninfo { 30 unsigned char len; 31 unsigned char flags; 32 }; 33 34 #define IS_XFORM(inst) (((inst) >> 26) == 31) 35 #define IS_DSFORM(inst) (((inst) >> 26) >= 56) 36 37 #define INVALID { 0, 0 } 38 39 /* Bits in the flags field */ 40 #define LD 0 /* load */ 41 #define ST 1 /* store */ 42 #define SE 2 /* sign-extend value, or FP ld/st as word */ 43 #define F 4 /* to/from fp regs */ 44 #define U 8 /* update index register */ 45 #define M 0x10 /* multiple load/store */ 46 #define SW 0x20 /* byte swap */ 47 #define S 0x40 /* single-precision fp or... */ 48 #define SX 0x40 /* ... byte count in XER */ 49 #define HARD 0x80 /* string, stwcx. */ 50 #define E4 0x40 /* SPE endianness is word */ 51 #define E8 0x80 /* SPE endianness is double word */ 52 #define SPLT 0x80 /* VSX SPLAT load */ 53 54 /* DSISR bits reported for a DCBZ instruction: */ 55 #define DCBZ 0x5f /* 8xx/82xx dcbz faults when cache not enabled */ 56 57 /* 58 * The PowerPC stores certain bits of the instruction that caused the 59 * alignment exception in the DSISR register. This array maps those 60 * bits to information about the operand length and what the 61 * instruction would do. 62 */ 63 static struct aligninfo aligninfo[128] = { 64 { 4, LD }, /* 00 0 0000: lwz / lwarx */ 65 INVALID, /* 00 0 0001 */ 66 { 4, ST }, /* 00 0 0010: stw */ 67 INVALID, /* 00 0 0011 */ 68 { 2, LD }, /* 00 0 0100: lhz */ 69 { 2, LD+SE }, /* 00 0 0101: lha */ 70 { 2, ST }, /* 00 0 0110: sth */ 71 { 4, LD+M }, /* 00 0 0111: lmw */ 72 { 4, LD+F+S }, /* 00 0 1000: lfs */ 73 { 8, LD+F }, /* 00 0 1001: lfd */ 74 { 4, ST+F+S }, /* 00 0 1010: stfs */ 75 { 8, ST+F }, /* 00 0 1011: stfd */ 76 INVALID, /* 00 0 1100 */ 77 { 8, LD }, /* 00 0 1101: ld/ldu/lwa */ 78 INVALID, /* 00 0 1110 */ 79 { 8, ST }, /* 00 0 1111: std/stdu */ 80 { 4, LD+U }, /* 00 1 0000: lwzu */ 81 INVALID, /* 00 1 0001 */ 82 { 4, ST+U }, /* 00 1 0010: stwu */ 83 INVALID, /* 00 1 0011 */ 84 { 2, LD+U }, /* 00 1 0100: lhzu */ 85 { 2, LD+SE+U }, /* 00 1 0101: lhau */ 86 { 2, ST+U }, /* 00 1 0110: sthu */ 87 { 4, ST+M }, /* 00 1 0111: stmw */ 88 { 4, LD+F+S+U }, /* 00 1 1000: lfsu */ 89 { 8, LD+F+U }, /* 00 1 1001: lfdu */ 90 { 4, ST+F+S+U }, /* 00 1 1010: stfsu */ 91 { 8, ST+F+U }, /* 00 1 1011: stfdu */ 92 { 16, LD+F }, /* 00 1 1100: lfdp */ 93 INVALID, /* 00 1 1101 */ 94 { 16, ST+F }, /* 00 1 1110: stfdp */ 95 INVALID, /* 00 1 1111 */ 96 { 8, LD }, /* 01 0 0000: ldx */ 97 INVALID, /* 01 0 0001 */ 98 { 8, ST }, /* 01 0 0010: stdx */ 99 INVALID, /* 01 0 0011 */ 100 INVALID, /* 01 0 0100 */ 101 { 4, LD+SE }, /* 01 0 0101: lwax */ 102 INVALID, /* 01 0 0110 */ 103 INVALID, /* 01 0 0111 */ 104 { 4, LD+M+HARD+SX }, /* 01 0 1000: lswx */ 105 { 4, LD+M+HARD }, /* 01 0 1001: lswi */ 106 { 4, ST+M+HARD+SX }, /* 01 0 1010: stswx */ 107 { 4, ST+M+HARD }, /* 01 0 1011: stswi */ 108 INVALID, /* 01 0 1100 */ 109 { 8, LD+U }, /* 01 0 1101: ldu */ 110 INVALID, /* 01 0 1110 */ 111 { 8, ST+U }, /* 01 0 1111: stdu */ 112 { 8, LD+U }, /* 01 1 0000: ldux */ 113 INVALID, /* 01 1 0001 */ 114 { 8, ST+U }, /* 01 1 0010: stdux */ 115 INVALID, /* 01 1 0011 */ 116 INVALID, /* 01 1 0100 */ 117 { 4, LD+SE+U }, /* 01 1 0101: lwaux */ 118 INVALID, /* 01 1 0110 */ 119 INVALID, /* 01 1 0111 */ 120 INVALID, /* 01 1 1000 */ 121 INVALID, /* 01 1 1001 */ 122 INVALID, /* 01 1 1010 */ 123 INVALID, /* 01 1 1011 */ 124 INVALID, /* 01 1 1100 */ 125 INVALID, /* 01 1 1101 */ 126 INVALID, /* 01 1 1110 */ 127 INVALID, /* 01 1 1111 */ 128 INVALID, /* 10 0 0000 */ 129 INVALID, /* 10 0 0001 */ 130 INVALID, /* 10 0 0010: stwcx. */ 131 INVALID, /* 10 0 0011 */ 132 INVALID, /* 10 0 0100 */ 133 INVALID, /* 10 0 0101 */ 134 INVALID, /* 10 0 0110 */ 135 INVALID, /* 10 0 0111 */ 136 { 4, LD+SW }, /* 10 0 1000: lwbrx */ 137 INVALID, /* 10 0 1001 */ 138 { 4, ST+SW }, /* 10 0 1010: stwbrx */ 139 INVALID, /* 10 0 1011 */ 140 { 2, LD+SW }, /* 10 0 1100: lhbrx */ 141 { 4, LD+SE }, /* 10 0 1101 lwa */ 142 { 2, ST+SW }, /* 10 0 1110: sthbrx */ 143 INVALID, /* 10 0 1111 */ 144 INVALID, /* 10 1 0000 */ 145 INVALID, /* 10 1 0001 */ 146 INVALID, /* 10 1 0010 */ 147 INVALID, /* 10 1 0011 */ 148 INVALID, /* 10 1 0100 */ 149 INVALID, /* 10 1 0101 */ 150 INVALID, /* 10 1 0110 */ 151 INVALID, /* 10 1 0111 */ 152 INVALID, /* 10 1 1000 */ 153 INVALID, /* 10 1 1001 */ 154 INVALID, /* 10 1 1010 */ 155 INVALID, /* 10 1 1011 */ 156 INVALID, /* 10 1 1100 */ 157 INVALID, /* 10 1 1101 */ 158 INVALID, /* 10 1 1110 */ 159 { 0, ST+HARD }, /* 10 1 1111: dcbz */ 160 { 4, LD }, /* 11 0 0000: lwzx */ 161 INVALID, /* 11 0 0001 */ 162 { 4, ST }, /* 11 0 0010: stwx */ 163 INVALID, /* 11 0 0011 */ 164 { 2, LD }, /* 11 0 0100: lhzx */ 165 { 2, LD+SE }, /* 11 0 0101: lhax */ 166 { 2, ST }, /* 11 0 0110: sthx */ 167 INVALID, /* 11 0 0111 */ 168 { 4, LD+F+S }, /* 11 0 1000: lfsx */ 169 { 8, LD+F }, /* 11 0 1001: lfdx */ 170 { 4, ST+F+S }, /* 11 0 1010: stfsx */ 171 { 8, ST+F }, /* 11 0 1011: stfdx */ 172 { 16, LD+F }, /* 11 0 1100: lfdpx */ 173 { 4, LD+F+SE }, /* 11 0 1101: lfiwax */ 174 { 16, ST+F }, /* 11 0 1110: stfdpx */ 175 { 4, ST+F }, /* 11 0 1111: stfiwx */ 176 { 4, LD+U }, /* 11 1 0000: lwzux */ 177 INVALID, /* 11 1 0001 */ 178 { 4, ST+U }, /* 11 1 0010: stwux */ 179 INVALID, /* 11 1 0011 */ 180 { 2, LD+U }, /* 11 1 0100: lhzux */ 181 { 2, LD+SE+U }, /* 11 1 0101: lhaux */ 182 { 2, ST+U }, /* 11 1 0110: sthux */ 183 INVALID, /* 11 1 0111 */ 184 { 4, LD+F+S+U }, /* 11 1 1000: lfsux */ 185 { 8, LD+F+U }, /* 11 1 1001: lfdux */ 186 { 4, ST+F+S+U }, /* 11 1 1010: stfsux */ 187 { 8, ST+F+U }, /* 11 1 1011: stfdux */ 188 INVALID, /* 11 1 1100 */ 189 { 4, LD+F }, /* 11 1 1101: lfiwzx */ 190 INVALID, /* 11 1 1110 */ 191 INVALID, /* 11 1 1111 */ 192 }; 193 194 /* 195 * Create a DSISR value from the instruction 196 */ 197 static inline unsigned make_dsisr(unsigned instr) 198 { 199 unsigned dsisr; 200 201 202 /* bits 6:15 --> 22:31 */ 203 dsisr = (instr & 0x03ff0000) >> 16; 204 205 if (IS_XFORM(instr)) { 206 /* bits 29:30 --> 15:16 */ 207 dsisr |= (instr & 0x00000006) << 14; 208 /* bit 25 --> 17 */ 209 dsisr |= (instr & 0x00000040) << 8; 210 /* bits 21:24 --> 18:21 */ 211 dsisr |= (instr & 0x00000780) << 3; 212 } else { 213 /* bit 5 --> 17 */ 214 dsisr |= (instr & 0x04000000) >> 12; 215 /* bits 1: 4 --> 18:21 */ 216 dsisr |= (instr & 0x78000000) >> 17; 217 /* bits 30:31 --> 12:13 */ 218 if (IS_DSFORM(instr)) 219 dsisr |= (instr & 0x00000003) << 18; 220 } 221 222 return dsisr; 223 } 224 225 /* 226 * The dcbz (data cache block zero) instruction 227 * gives an alignment fault if used on non-cacheable 228 * memory. We handle the fault mainly for the 229 * case when we are running with the cache disabled 230 * for debugging. 231 */ 232 static int emulate_dcbz(struct pt_regs *regs, unsigned char __user *addr) 233 { 234 long __user *p; 235 int i, size; 236 237 #ifdef __powerpc64__ 238 size = ppc64_caches.dline_size; 239 #else 240 size = L1_CACHE_BYTES; 241 #endif 242 p = (long __user *) (regs->dar & -size); 243 if (user_mode(regs) && !access_ok(VERIFY_WRITE, p, size)) 244 return -EFAULT; 245 for (i = 0; i < size / sizeof(long); ++i) 246 if (__put_user_inatomic(0, p+i)) 247 return -EFAULT; 248 return 1; 249 } 250 251 /* 252 * Emulate load & store multiple instructions 253 * On 64-bit machines, these instructions only affect/use the 254 * bottom 4 bytes of each register, and the loads clear the 255 * top 4 bytes of the affected register. 256 */ 257 #ifdef __BIG_ENDIAN__ 258 #ifdef CONFIG_PPC64 259 #define REG_BYTE(rp, i) *((u8 *)((rp) + ((i) >> 2)) + ((i) & 3) + 4) 260 #else 261 #define REG_BYTE(rp, i) *((u8 *)(rp) + (i)) 262 #endif 263 #endif 264 265 #ifdef __LITTLE_ENDIAN__ 266 #define REG_BYTE(rp, i) (*(((u8 *)((rp) + ((i)>>2)) + ((i)&3)))) 267 #endif 268 269 #define SWIZ_PTR(p) ((unsigned char __user *)((p) ^ swiz)) 270 271 static int emulate_multiple(struct pt_regs *regs, unsigned char __user *addr, 272 unsigned int reg, unsigned int nb, 273 unsigned int flags, unsigned int instr, 274 unsigned long swiz) 275 { 276 unsigned long *rptr; 277 unsigned int nb0, i, bswiz; 278 unsigned long p; 279 280 /* 281 * We do not try to emulate 8 bytes multiple as they aren't really 282 * available in our operating environments and we don't try to 283 * emulate multiples operations in kernel land as they should never 284 * be used/generated there at least not on unaligned boundaries 285 */ 286 if (unlikely((nb > 4) || !user_mode(regs))) 287 return 0; 288 289 /* lmw, stmw, lswi/x, stswi/x */ 290 nb0 = 0; 291 if (flags & HARD) { 292 if (flags & SX) { 293 nb = regs->xer & 127; 294 if (nb == 0) 295 return 1; 296 } else { 297 unsigned long pc = regs->nip ^ (swiz & 4); 298 299 if (__get_user_inatomic(instr, 300 (unsigned int __user *)pc)) 301 return -EFAULT; 302 if (swiz == 0 && (flags & SW)) 303 instr = cpu_to_le32(instr); 304 nb = (instr >> 11) & 0x1f; 305 if (nb == 0) 306 nb = 32; 307 } 308 if (nb + reg * 4 > 128) { 309 nb0 = nb + reg * 4 - 128; 310 nb = 128 - reg * 4; 311 } 312 #ifdef __LITTLE_ENDIAN__ 313 /* 314 * String instructions are endian neutral but the code 315 * below is not. Force byte swapping on so that the 316 * effects of swizzling are undone in the load/store 317 * loops below. 318 */ 319 flags ^= SW; 320 #endif 321 } else { 322 /* lwm, stmw */ 323 nb = (32 - reg) * 4; 324 } 325 326 if (!access_ok((flags & ST ? VERIFY_WRITE: VERIFY_READ), addr, nb+nb0)) 327 return -EFAULT; /* bad address */ 328 329 rptr = ®s->gpr[reg]; 330 p = (unsigned long) addr; 331 bswiz = (flags & SW)? 3: 0; 332 333 if (!(flags & ST)) { 334 /* 335 * This zeroes the top 4 bytes of the affected registers 336 * in 64-bit mode, and also zeroes out any remaining 337 * bytes of the last register for lsw*. 338 */ 339 memset(rptr, 0, ((nb + 3) / 4) * sizeof(unsigned long)); 340 if (nb0 > 0) 341 memset(®s->gpr[0], 0, 342 ((nb0 + 3) / 4) * sizeof(unsigned long)); 343 344 for (i = 0; i < nb; ++i, ++p) 345 if (__get_user_inatomic(REG_BYTE(rptr, i ^ bswiz), 346 SWIZ_PTR(p))) 347 return -EFAULT; 348 if (nb0 > 0) { 349 rptr = ®s->gpr[0]; 350 addr += nb; 351 for (i = 0; i < nb0; ++i, ++p) 352 if (__get_user_inatomic(REG_BYTE(rptr, 353 i ^ bswiz), 354 SWIZ_PTR(p))) 355 return -EFAULT; 356 } 357 358 } else { 359 for (i = 0; i < nb; ++i, ++p) 360 if (__put_user_inatomic(REG_BYTE(rptr, i ^ bswiz), 361 SWIZ_PTR(p))) 362 return -EFAULT; 363 if (nb0 > 0) { 364 rptr = ®s->gpr[0]; 365 addr += nb; 366 for (i = 0; i < nb0; ++i, ++p) 367 if (__put_user_inatomic(REG_BYTE(rptr, 368 i ^ bswiz), 369 SWIZ_PTR(p))) 370 return -EFAULT; 371 } 372 } 373 return 1; 374 } 375 376 /* 377 * Emulate floating-point pair loads and stores. 378 * Only POWER6 has these instructions, and it does true little-endian, 379 * so we don't need the address swizzling. 380 */ 381 static int emulate_fp_pair(unsigned char __user *addr, unsigned int reg, 382 unsigned int flags) 383 { 384 char *ptr0 = (char *) ¤t->thread.TS_FPR(reg); 385 char *ptr1 = (char *) ¤t->thread.TS_FPR(reg+1); 386 int i, ret, sw = 0; 387 388 if (!(flags & F)) 389 return 0; 390 if (reg & 1) 391 return 0; /* invalid form: FRS/FRT must be even */ 392 if (flags & SW) 393 sw = 7; 394 ret = 0; 395 for (i = 0; i < 8; ++i) { 396 if (!(flags & ST)) { 397 ret |= __get_user(ptr0[i^sw], addr + i); 398 ret |= __get_user(ptr1[i^sw], addr + i + 8); 399 } else { 400 ret |= __put_user(ptr0[i^sw], addr + i); 401 ret |= __put_user(ptr1[i^sw], addr + i + 8); 402 } 403 } 404 if (ret) 405 return -EFAULT; 406 return 1; /* exception handled and fixed up */ 407 } 408 409 #ifdef CONFIG_SPE 410 411 static struct aligninfo spe_aligninfo[32] = { 412 { 8, LD+E8 }, /* 0 00 00: evldd[x] */ 413 { 8, LD+E4 }, /* 0 00 01: evldw[x] */ 414 { 8, LD }, /* 0 00 10: evldh[x] */ 415 INVALID, /* 0 00 11 */ 416 { 2, LD }, /* 0 01 00: evlhhesplat[x] */ 417 INVALID, /* 0 01 01 */ 418 { 2, LD }, /* 0 01 10: evlhhousplat[x] */ 419 { 2, LD+SE }, /* 0 01 11: evlhhossplat[x] */ 420 { 4, LD }, /* 0 10 00: evlwhe[x] */ 421 INVALID, /* 0 10 01 */ 422 { 4, LD }, /* 0 10 10: evlwhou[x] */ 423 { 4, LD+SE }, /* 0 10 11: evlwhos[x] */ 424 { 4, LD+E4 }, /* 0 11 00: evlwwsplat[x] */ 425 INVALID, /* 0 11 01 */ 426 { 4, LD }, /* 0 11 10: evlwhsplat[x] */ 427 INVALID, /* 0 11 11 */ 428 429 { 8, ST+E8 }, /* 1 00 00: evstdd[x] */ 430 { 8, ST+E4 }, /* 1 00 01: evstdw[x] */ 431 { 8, ST }, /* 1 00 10: evstdh[x] */ 432 INVALID, /* 1 00 11 */ 433 INVALID, /* 1 01 00 */ 434 INVALID, /* 1 01 01 */ 435 INVALID, /* 1 01 10 */ 436 INVALID, /* 1 01 11 */ 437 { 4, ST }, /* 1 10 00: evstwhe[x] */ 438 INVALID, /* 1 10 01 */ 439 { 4, ST }, /* 1 10 10: evstwho[x] */ 440 INVALID, /* 1 10 11 */ 441 { 4, ST+E4 }, /* 1 11 00: evstwwe[x] */ 442 INVALID, /* 1 11 01 */ 443 { 4, ST+E4 }, /* 1 11 10: evstwwo[x] */ 444 INVALID, /* 1 11 11 */ 445 }; 446 447 #define EVLDD 0x00 448 #define EVLDW 0x01 449 #define EVLDH 0x02 450 #define EVLHHESPLAT 0x04 451 #define EVLHHOUSPLAT 0x06 452 #define EVLHHOSSPLAT 0x07 453 #define EVLWHE 0x08 454 #define EVLWHOU 0x0A 455 #define EVLWHOS 0x0B 456 #define EVLWWSPLAT 0x0C 457 #define EVLWHSPLAT 0x0E 458 #define EVSTDD 0x10 459 #define EVSTDW 0x11 460 #define EVSTDH 0x12 461 #define EVSTWHE 0x18 462 #define EVSTWHO 0x1A 463 #define EVSTWWE 0x1C 464 #define EVSTWWO 0x1E 465 466 /* 467 * Emulate SPE loads and stores. 468 * Only Book-E has these instructions, and it does true little-endian, 469 * so we don't need the address swizzling. 470 */ 471 static int emulate_spe(struct pt_regs *regs, unsigned int reg, 472 unsigned int instr) 473 { 474 int ret; 475 union { 476 u64 ll; 477 u32 w[2]; 478 u16 h[4]; 479 u8 v[8]; 480 } data, temp; 481 unsigned char __user *p, *addr; 482 unsigned long *evr = ¤t->thread.evr[reg]; 483 unsigned int nb, flags; 484 485 instr = (instr >> 1) & 0x1f; 486 487 /* DAR has the operand effective address */ 488 addr = (unsigned char __user *)regs->dar; 489 490 nb = spe_aligninfo[instr].len; 491 flags = spe_aligninfo[instr].flags; 492 493 /* Verify the address of the operand */ 494 if (unlikely(user_mode(regs) && 495 !access_ok((flags & ST ? VERIFY_WRITE : VERIFY_READ), 496 addr, nb))) 497 return -EFAULT; 498 499 /* userland only */ 500 if (unlikely(!user_mode(regs))) 501 return 0; 502 503 flush_spe_to_thread(current); 504 505 /* If we are loading, get the data from user space, else 506 * get it from register values 507 */ 508 if (flags & ST) { 509 data.ll = 0; 510 switch (instr) { 511 case EVSTDD: 512 case EVSTDW: 513 case EVSTDH: 514 data.w[0] = *evr; 515 data.w[1] = regs->gpr[reg]; 516 break; 517 case EVSTWHE: 518 data.h[2] = *evr >> 16; 519 data.h[3] = regs->gpr[reg] >> 16; 520 break; 521 case EVSTWHO: 522 data.h[2] = *evr & 0xffff; 523 data.h[3] = regs->gpr[reg] & 0xffff; 524 break; 525 case EVSTWWE: 526 data.w[1] = *evr; 527 break; 528 case EVSTWWO: 529 data.w[1] = regs->gpr[reg]; 530 break; 531 default: 532 return -EINVAL; 533 } 534 } else { 535 temp.ll = data.ll = 0; 536 ret = 0; 537 p = addr; 538 539 switch (nb) { 540 case 8: 541 ret |= __get_user_inatomic(temp.v[0], p++); 542 ret |= __get_user_inatomic(temp.v[1], p++); 543 ret |= __get_user_inatomic(temp.v[2], p++); 544 ret |= __get_user_inatomic(temp.v[3], p++); 545 case 4: 546 ret |= __get_user_inatomic(temp.v[4], p++); 547 ret |= __get_user_inatomic(temp.v[5], p++); 548 case 2: 549 ret |= __get_user_inatomic(temp.v[6], p++); 550 ret |= __get_user_inatomic(temp.v[7], p++); 551 if (unlikely(ret)) 552 return -EFAULT; 553 } 554 555 switch (instr) { 556 case EVLDD: 557 case EVLDW: 558 case EVLDH: 559 data.ll = temp.ll; 560 break; 561 case EVLHHESPLAT: 562 data.h[0] = temp.h[3]; 563 data.h[2] = temp.h[3]; 564 break; 565 case EVLHHOUSPLAT: 566 case EVLHHOSSPLAT: 567 data.h[1] = temp.h[3]; 568 data.h[3] = temp.h[3]; 569 break; 570 case EVLWHE: 571 data.h[0] = temp.h[2]; 572 data.h[2] = temp.h[3]; 573 break; 574 case EVLWHOU: 575 case EVLWHOS: 576 data.h[1] = temp.h[2]; 577 data.h[3] = temp.h[3]; 578 break; 579 case EVLWWSPLAT: 580 data.w[0] = temp.w[1]; 581 data.w[1] = temp.w[1]; 582 break; 583 case EVLWHSPLAT: 584 data.h[0] = temp.h[2]; 585 data.h[1] = temp.h[2]; 586 data.h[2] = temp.h[3]; 587 data.h[3] = temp.h[3]; 588 break; 589 default: 590 return -EINVAL; 591 } 592 } 593 594 if (flags & SW) { 595 switch (flags & 0xf0) { 596 case E8: 597 data.ll = swab64(data.ll); 598 break; 599 case E4: 600 data.w[0] = swab32(data.w[0]); 601 data.w[1] = swab32(data.w[1]); 602 break; 603 /* Its half word endian */ 604 default: 605 data.h[0] = swab16(data.h[0]); 606 data.h[1] = swab16(data.h[1]); 607 data.h[2] = swab16(data.h[2]); 608 data.h[3] = swab16(data.h[3]); 609 break; 610 } 611 } 612 613 if (flags & SE) { 614 data.w[0] = (s16)data.h[1]; 615 data.w[1] = (s16)data.h[3]; 616 } 617 618 /* Store result to memory or update registers */ 619 if (flags & ST) { 620 ret = 0; 621 p = addr; 622 switch (nb) { 623 case 8: 624 ret |= __put_user_inatomic(data.v[0], p++); 625 ret |= __put_user_inatomic(data.v[1], p++); 626 ret |= __put_user_inatomic(data.v[2], p++); 627 ret |= __put_user_inatomic(data.v[3], p++); 628 case 4: 629 ret |= __put_user_inatomic(data.v[4], p++); 630 ret |= __put_user_inatomic(data.v[5], p++); 631 case 2: 632 ret |= __put_user_inatomic(data.v[6], p++); 633 ret |= __put_user_inatomic(data.v[7], p++); 634 } 635 if (unlikely(ret)) 636 return -EFAULT; 637 } else { 638 *evr = data.w[0]; 639 regs->gpr[reg] = data.w[1]; 640 } 641 642 return 1; 643 } 644 #endif /* CONFIG_SPE */ 645 646 #ifdef CONFIG_VSX 647 /* 648 * Emulate VSX instructions... 649 */ 650 static int emulate_vsx(unsigned char __user *addr, unsigned int reg, 651 unsigned int areg, struct pt_regs *regs, 652 unsigned int flags, unsigned int length, 653 unsigned int elsize) 654 { 655 char *ptr; 656 unsigned long *lptr; 657 int ret = 0; 658 int sw = 0; 659 int i, j; 660 661 /* userland only */ 662 if (unlikely(!user_mode(regs))) 663 return 0; 664 665 flush_vsx_to_thread(current); 666 667 if (reg < 32) 668 ptr = (char *) ¤t->thread.fp_state.fpr[reg][0]; 669 else 670 ptr = (char *) ¤t->thread.vr_state.vr[reg - 32]; 671 672 lptr = (unsigned long *) ptr; 673 674 #ifdef __LITTLE_ENDIAN__ 675 if (flags & SW) { 676 elsize = length; 677 sw = length-1; 678 } else { 679 /* 680 * The elements are BE ordered, even in LE mode, so process 681 * them in reverse order. 682 */ 683 addr += length - elsize; 684 685 /* 8 byte memory accesses go in the top 8 bytes of the VR */ 686 if (length == 8) 687 ptr += 8; 688 } 689 #else 690 if (flags & SW) 691 sw = elsize-1; 692 #endif 693 694 for (j = 0; j < length; j += elsize) { 695 for (i = 0; i < elsize; ++i) { 696 if (flags & ST) 697 ret |= __put_user(ptr[i^sw], addr + i); 698 else 699 ret |= __get_user(ptr[i^sw], addr + i); 700 } 701 ptr += elsize; 702 #ifdef __LITTLE_ENDIAN__ 703 addr -= elsize; 704 #else 705 addr += elsize; 706 #endif 707 } 708 709 #ifdef __BIG_ENDIAN__ 710 #define VSX_HI 0 711 #define VSX_LO 1 712 #else 713 #define VSX_HI 1 714 #define VSX_LO 0 715 #endif 716 717 if (!ret) { 718 if (flags & U) 719 regs->gpr[areg] = regs->dar; 720 721 /* Splat load copies the same data to top and bottom 8 bytes */ 722 if (flags & SPLT) 723 lptr[VSX_LO] = lptr[VSX_HI]; 724 /* For 8 byte loads, zero the low 8 bytes */ 725 else if (!(flags & ST) && (8 == length)) 726 lptr[VSX_LO] = 0; 727 } else 728 return -EFAULT; 729 730 return 1; 731 } 732 #endif 733 734 /* 735 * Called on alignment exception. Attempts to fixup 736 * 737 * Return 1 on success 738 * Return 0 if unable to handle the interrupt 739 * Return -EFAULT if data address is bad 740 */ 741 742 int fix_alignment(struct pt_regs *regs) 743 { 744 unsigned int instr, nb, flags, instruction = 0; 745 unsigned int reg, areg; 746 unsigned int dsisr; 747 unsigned char __user *addr; 748 unsigned long p, swiz; 749 int ret, i; 750 union data { 751 u64 ll; 752 double dd; 753 unsigned char v[8]; 754 struct { 755 #ifdef __LITTLE_ENDIAN__ 756 int low32; 757 unsigned hi32; 758 #else 759 unsigned hi32; 760 int low32; 761 #endif 762 } x32; 763 struct { 764 #ifdef __LITTLE_ENDIAN__ 765 short low16; 766 unsigned char hi48[6]; 767 #else 768 unsigned char hi48[6]; 769 short low16; 770 #endif 771 } x16; 772 } data; 773 774 /* 775 * We require a complete register set, if not, then our assembly 776 * is broken 777 */ 778 CHECK_FULL_REGS(regs); 779 780 dsisr = regs->dsisr; 781 782 /* Some processors don't provide us with a DSISR we can use here, 783 * let's make one up from the instruction 784 */ 785 if (cpu_has_feature(CPU_FTR_NODSISRALIGN)) { 786 unsigned long pc = regs->nip; 787 788 if (cpu_has_feature(CPU_FTR_PPC_LE) && (regs->msr & MSR_LE)) 789 pc ^= 4; 790 if (unlikely(__get_user_inatomic(instr, 791 (unsigned int __user *)pc))) 792 return -EFAULT; 793 if (cpu_has_feature(CPU_FTR_REAL_LE) && (regs->msr & MSR_LE)) 794 instr = cpu_to_le32(instr); 795 dsisr = make_dsisr(instr); 796 instruction = instr; 797 } 798 799 /* extract the operation and registers from the dsisr */ 800 reg = (dsisr >> 5) & 0x1f; /* source/dest register */ 801 areg = dsisr & 0x1f; /* register to update */ 802 803 #ifdef CONFIG_SPE 804 if ((instr >> 26) == 0x4) { 805 PPC_WARN_ALIGNMENT(spe, regs); 806 return emulate_spe(regs, reg, instr); 807 } 808 #endif 809 810 instr = (dsisr >> 10) & 0x7f; 811 instr |= (dsisr >> 13) & 0x60; 812 813 /* Lookup the operation in our table */ 814 nb = aligninfo[instr].len; 815 flags = aligninfo[instr].flags; 816 817 /* ldbrx/stdbrx overlap lfs/stfs in the DSISR unfortunately */ 818 if (IS_XFORM(instruction) && ((instruction >> 1) & 0x3ff) == 532) { 819 nb = 8; 820 flags = LD+SW; 821 } else if (IS_XFORM(instruction) && 822 ((instruction >> 1) & 0x3ff) == 660) { 823 nb = 8; 824 flags = ST+SW; 825 } 826 827 /* Byteswap little endian loads and stores */ 828 swiz = 0; 829 if ((regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE)) { 830 flags ^= SW; 831 #ifdef __BIG_ENDIAN__ 832 /* 833 * So-called "PowerPC little endian" mode works by 834 * swizzling addresses rather than by actually doing 835 * any byte-swapping. To emulate this, we XOR each 836 * byte address with 7. We also byte-swap, because 837 * the processor's address swizzling depends on the 838 * operand size (it xors the address with 7 for bytes, 839 * 6 for halfwords, 4 for words, 0 for doublewords) but 840 * we will xor with 7 and load/store each byte separately. 841 */ 842 if (cpu_has_feature(CPU_FTR_PPC_LE)) 843 swiz = 7; 844 #endif 845 } 846 847 /* DAR has the operand effective address */ 848 addr = (unsigned char __user *)regs->dar; 849 850 #ifdef CONFIG_VSX 851 if ((instruction & 0xfc00003e) == 0x7c000018) { 852 unsigned int elsize; 853 854 /* Additional register addressing bit (64 VSX vs 32 FPR/GPR) */ 855 reg |= (instruction & 0x1) << 5; 856 /* Simple inline decoder instead of a table */ 857 /* VSX has only 8 and 16 byte memory accesses */ 858 nb = 8; 859 if (instruction & 0x200) 860 nb = 16; 861 862 /* Vector stores in little-endian mode swap individual 863 elements, so process them separately */ 864 elsize = 4; 865 if (instruction & 0x80) 866 elsize = 8; 867 868 flags = 0; 869 if ((regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE)) 870 flags |= SW; 871 if (instruction & 0x100) 872 flags |= ST; 873 if (instruction & 0x040) 874 flags |= U; 875 /* splat load needs a special decoder */ 876 if ((instruction & 0x400) == 0){ 877 flags |= SPLT; 878 nb = 8; 879 } 880 PPC_WARN_ALIGNMENT(vsx, regs); 881 return emulate_vsx(addr, reg, areg, regs, flags, nb, elsize); 882 } 883 #endif 884 /* A size of 0 indicates an instruction we don't support, with 885 * the exception of DCBZ which is handled as a special case here 886 */ 887 if (instr == DCBZ) { 888 PPC_WARN_ALIGNMENT(dcbz, regs); 889 return emulate_dcbz(regs, addr); 890 } 891 if (unlikely(nb == 0)) 892 return 0; 893 894 /* Load/Store Multiple instructions are handled in their own 895 * function 896 */ 897 if (flags & M) { 898 PPC_WARN_ALIGNMENT(multiple, regs); 899 return emulate_multiple(regs, addr, reg, nb, 900 flags, instr, swiz); 901 } 902 903 /* Verify the address of the operand */ 904 if (unlikely(user_mode(regs) && 905 !access_ok((flags & ST ? VERIFY_WRITE : VERIFY_READ), 906 addr, nb))) 907 return -EFAULT; 908 909 /* Force the fprs into the save area so we can reference them */ 910 if (flags & F) { 911 /* userland only */ 912 if (unlikely(!user_mode(regs))) 913 return 0; 914 flush_fp_to_thread(current); 915 } 916 917 /* Special case for 16-byte FP loads and stores */ 918 if (nb == 16) { 919 PPC_WARN_ALIGNMENT(fp_pair, regs); 920 return emulate_fp_pair(addr, reg, flags); 921 } 922 923 PPC_WARN_ALIGNMENT(unaligned, regs); 924 925 /* If we are loading, get the data from user space, else 926 * get it from register values 927 */ 928 if (!(flags & ST)) { 929 unsigned int start = 0; 930 931 switch (nb) { 932 case 4: 933 start = offsetof(union data, x32.low32); 934 break; 935 case 2: 936 start = offsetof(union data, x16.low16); 937 break; 938 } 939 940 data.ll = 0; 941 ret = 0; 942 p = (unsigned long)addr; 943 944 for (i = 0; i < nb; i++) 945 ret |= __get_user_inatomic(data.v[start + i], 946 SWIZ_PTR(p++)); 947 948 if (unlikely(ret)) 949 return -EFAULT; 950 951 } else if (flags & F) { 952 data.ll = current->thread.TS_FPR(reg); 953 if (flags & S) { 954 /* Single-precision FP store requires conversion... */ 955 #ifdef CONFIG_PPC_FPU 956 preempt_disable(); 957 enable_kernel_fp(); 958 cvt_df(&data.dd, (float *)&data.x32.low32); 959 preempt_enable(); 960 #else 961 return 0; 962 #endif 963 } 964 } else 965 data.ll = regs->gpr[reg]; 966 967 if (flags & SW) { 968 switch (nb) { 969 case 8: 970 data.ll = swab64(data.ll); 971 break; 972 case 4: 973 data.x32.low32 = swab32(data.x32.low32); 974 break; 975 case 2: 976 data.x16.low16 = swab16(data.x16.low16); 977 break; 978 } 979 } 980 981 /* Perform other misc operations like sign extension 982 * or floating point single precision conversion 983 */ 984 switch (flags & ~(U|SW)) { 985 case LD+SE: /* sign extending integer loads */ 986 case LD+F+SE: /* sign extend for lfiwax */ 987 if ( nb == 2 ) 988 data.ll = data.x16.low16; 989 else /* nb must be 4 */ 990 data.ll = data.x32.low32; 991 break; 992 993 /* Single-precision FP load requires conversion... */ 994 case LD+F+S: 995 #ifdef CONFIG_PPC_FPU 996 preempt_disable(); 997 enable_kernel_fp(); 998 cvt_fd((float *)&data.x32.low32, &data.dd); 999 preempt_enable(); 1000 #else 1001 return 0; 1002 #endif 1003 break; 1004 } 1005 1006 /* Store result to memory or update registers */ 1007 if (flags & ST) { 1008 unsigned int start = 0; 1009 1010 switch (nb) { 1011 case 4: 1012 start = offsetof(union data, x32.low32); 1013 break; 1014 case 2: 1015 start = offsetof(union data, x16.low16); 1016 break; 1017 } 1018 1019 ret = 0; 1020 p = (unsigned long)addr; 1021 1022 for (i = 0; i < nb; i++) 1023 ret |= __put_user_inatomic(data.v[start + i], 1024 SWIZ_PTR(p++)); 1025 1026 if (unlikely(ret)) 1027 return -EFAULT; 1028 } else if (flags & F) 1029 current->thread.TS_FPR(reg) = data.ll; 1030 else 1031 regs->gpr[reg] = data.ll; 1032 1033 /* Update RA as needed */ 1034 if (flags & U) 1035 regs->gpr[areg] = regs->dar; 1036 1037 return 1; 1038 } 1039