1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* align.c - handle alignment exceptions for the Power PC. 3 * 4 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> 5 * Copyright (c) 1998-1999 TiVo, Inc. 6 * PowerPC 403GCX modifications. 7 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> 8 * PowerPC 403GCX/405GP modifications. 9 * Copyright (c) 2001-2002 PPC64 team, IBM Corp 10 * 64-bit and Power4 support 11 * Copyright (c) 2005 Benjamin Herrenschmidt, IBM Corp 12 * <benh@kernel.crashing.org> 13 * Merge ppc32 and ppc64 implementations 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/mm.h> 18 #include <asm/processor.h> 19 #include <linux/uaccess.h> 20 #include <asm/cache.h> 21 #include <asm/cputable.h> 22 #include <asm/emulated_ops.h> 23 #include <asm/switch_to.h> 24 #include <asm/disassemble.h> 25 #include <asm/cpu_has_feature.h> 26 #include <asm/sstep.h> 27 28 struct aligninfo { 29 unsigned char len; 30 unsigned char flags; 31 }; 32 33 34 #define INVALID { 0, 0 } 35 36 /* Bits in the flags field */ 37 #define LD 0 /* load */ 38 #define ST 1 /* store */ 39 #define SE 2 /* sign-extend value, or FP ld/st as word */ 40 #define SW 0x20 /* byte swap */ 41 #define E4 0x40 /* SPE endianness is word */ 42 #define E8 0x80 /* SPE endianness is double word */ 43 44 #ifdef CONFIG_SPE 45 46 static struct aligninfo spe_aligninfo[32] = { 47 { 8, LD+E8 }, /* 0 00 00: evldd[x] */ 48 { 8, LD+E4 }, /* 0 00 01: evldw[x] */ 49 { 8, LD }, /* 0 00 10: evldh[x] */ 50 INVALID, /* 0 00 11 */ 51 { 2, LD }, /* 0 01 00: evlhhesplat[x] */ 52 INVALID, /* 0 01 01 */ 53 { 2, LD }, /* 0 01 10: evlhhousplat[x] */ 54 { 2, LD+SE }, /* 0 01 11: evlhhossplat[x] */ 55 { 4, LD }, /* 0 10 00: evlwhe[x] */ 56 INVALID, /* 0 10 01 */ 57 { 4, LD }, /* 0 10 10: evlwhou[x] */ 58 { 4, LD+SE }, /* 0 10 11: evlwhos[x] */ 59 { 4, LD+E4 }, /* 0 11 00: evlwwsplat[x] */ 60 INVALID, /* 0 11 01 */ 61 { 4, LD }, /* 0 11 10: evlwhsplat[x] */ 62 INVALID, /* 0 11 11 */ 63 64 { 8, ST+E8 }, /* 1 00 00: evstdd[x] */ 65 { 8, ST+E4 }, /* 1 00 01: evstdw[x] */ 66 { 8, ST }, /* 1 00 10: evstdh[x] */ 67 INVALID, /* 1 00 11 */ 68 INVALID, /* 1 01 00 */ 69 INVALID, /* 1 01 01 */ 70 INVALID, /* 1 01 10 */ 71 INVALID, /* 1 01 11 */ 72 { 4, ST }, /* 1 10 00: evstwhe[x] */ 73 INVALID, /* 1 10 01 */ 74 { 4, ST }, /* 1 10 10: evstwho[x] */ 75 INVALID, /* 1 10 11 */ 76 { 4, ST+E4 }, /* 1 11 00: evstwwe[x] */ 77 INVALID, /* 1 11 01 */ 78 { 4, ST+E4 }, /* 1 11 10: evstwwo[x] */ 79 INVALID, /* 1 11 11 */ 80 }; 81 82 #define EVLDD 0x00 83 #define EVLDW 0x01 84 #define EVLDH 0x02 85 #define EVLHHESPLAT 0x04 86 #define EVLHHOUSPLAT 0x06 87 #define EVLHHOSSPLAT 0x07 88 #define EVLWHE 0x08 89 #define EVLWHOU 0x0A 90 #define EVLWHOS 0x0B 91 #define EVLWWSPLAT 0x0C 92 #define EVLWHSPLAT 0x0E 93 #define EVSTDD 0x10 94 #define EVSTDW 0x11 95 #define EVSTDH 0x12 96 #define EVSTWHE 0x18 97 #define EVSTWHO 0x1A 98 #define EVSTWWE 0x1C 99 #define EVSTWWO 0x1E 100 101 /* 102 * Emulate SPE loads and stores. 103 * Only Book-E has these instructions, and it does true little-endian, 104 * so we don't need the address swizzling. 105 */ 106 static int emulate_spe(struct pt_regs *regs, unsigned int reg, 107 unsigned int instr) 108 { 109 int ret; 110 union { 111 u64 ll; 112 u32 w[2]; 113 u16 h[4]; 114 u8 v[8]; 115 } data, temp; 116 unsigned char __user *p, *addr; 117 unsigned long *evr = ¤t->thread.evr[reg]; 118 unsigned int nb, flags; 119 120 instr = (instr >> 1) & 0x1f; 121 122 /* DAR has the operand effective address */ 123 addr = (unsigned char __user *)regs->dar; 124 125 nb = spe_aligninfo[instr].len; 126 flags = spe_aligninfo[instr].flags; 127 128 /* Verify the address of the operand */ 129 if (unlikely(user_mode(regs) && 130 !access_ok(addr, nb))) 131 return -EFAULT; 132 133 /* userland only */ 134 if (unlikely(!user_mode(regs))) 135 return 0; 136 137 flush_spe_to_thread(current); 138 139 /* If we are loading, get the data from user space, else 140 * get it from register values 141 */ 142 if (flags & ST) { 143 data.ll = 0; 144 switch (instr) { 145 case EVSTDD: 146 case EVSTDW: 147 case EVSTDH: 148 data.w[0] = *evr; 149 data.w[1] = regs->gpr[reg]; 150 break; 151 case EVSTWHE: 152 data.h[2] = *evr >> 16; 153 data.h[3] = regs->gpr[reg] >> 16; 154 break; 155 case EVSTWHO: 156 data.h[2] = *evr & 0xffff; 157 data.h[3] = regs->gpr[reg] & 0xffff; 158 break; 159 case EVSTWWE: 160 data.w[1] = *evr; 161 break; 162 case EVSTWWO: 163 data.w[1] = regs->gpr[reg]; 164 break; 165 default: 166 return -EINVAL; 167 } 168 } else { 169 temp.ll = data.ll = 0; 170 ret = 0; 171 p = addr; 172 173 switch (nb) { 174 case 8: 175 ret |= __get_user_inatomic(temp.v[0], p++); 176 ret |= __get_user_inatomic(temp.v[1], p++); 177 ret |= __get_user_inatomic(temp.v[2], p++); 178 ret |= __get_user_inatomic(temp.v[3], p++); 179 case 4: 180 ret |= __get_user_inatomic(temp.v[4], p++); 181 ret |= __get_user_inatomic(temp.v[5], p++); 182 case 2: 183 ret |= __get_user_inatomic(temp.v[6], p++); 184 ret |= __get_user_inatomic(temp.v[7], p++); 185 if (unlikely(ret)) 186 return -EFAULT; 187 } 188 189 switch (instr) { 190 case EVLDD: 191 case EVLDW: 192 case EVLDH: 193 data.ll = temp.ll; 194 break; 195 case EVLHHESPLAT: 196 data.h[0] = temp.h[3]; 197 data.h[2] = temp.h[3]; 198 break; 199 case EVLHHOUSPLAT: 200 case EVLHHOSSPLAT: 201 data.h[1] = temp.h[3]; 202 data.h[3] = temp.h[3]; 203 break; 204 case EVLWHE: 205 data.h[0] = temp.h[2]; 206 data.h[2] = temp.h[3]; 207 break; 208 case EVLWHOU: 209 case EVLWHOS: 210 data.h[1] = temp.h[2]; 211 data.h[3] = temp.h[3]; 212 break; 213 case EVLWWSPLAT: 214 data.w[0] = temp.w[1]; 215 data.w[1] = temp.w[1]; 216 break; 217 case EVLWHSPLAT: 218 data.h[0] = temp.h[2]; 219 data.h[1] = temp.h[2]; 220 data.h[2] = temp.h[3]; 221 data.h[3] = temp.h[3]; 222 break; 223 default: 224 return -EINVAL; 225 } 226 } 227 228 if (flags & SW) { 229 switch (flags & 0xf0) { 230 case E8: 231 data.ll = swab64(data.ll); 232 break; 233 case E4: 234 data.w[0] = swab32(data.w[0]); 235 data.w[1] = swab32(data.w[1]); 236 break; 237 /* Its half word endian */ 238 default: 239 data.h[0] = swab16(data.h[0]); 240 data.h[1] = swab16(data.h[1]); 241 data.h[2] = swab16(data.h[2]); 242 data.h[3] = swab16(data.h[3]); 243 break; 244 } 245 } 246 247 if (flags & SE) { 248 data.w[0] = (s16)data.h[1]; 249 data.w[1] = (s16)data.h[3]; 250 } 251 252 /* Store result to memory or update registers */ 253 if (flags & ST) { 254 ret = 0; 255 p = addr; 256 switch (nb) { 257 case 8: 258 ret |= __put_user_inatomic(data.v[0], p++); 259 ret |= __put_user_inatomic(data.v[1], p++); 260 ret |= __put_user_inatomic(data.v[2], p++); 261 ret |= __put_user_inatomic(data.v[3], p++); 262 case 4: 263 ret |= __put_user_inatomic(data.v[4], p++); 264 ret |= __put_user_inatomic(data.v[5], p++); 265 case 2: 266 ret |= __put_user_inatomic(data.v[6], p++); 267 ret |= __put_user_inatomic(data.v[7], p++); 268 } 269 if (unlikely(ret)) 270 return -EFAULT; 271 } else { 272 *evr = data.w[0]; 273 regs->gpr[reg] = data.w[1]; 274 } 275 276 return 1; 277 } 278 #endif /* CONFIG_SPE */ 279 280 /* 281 * Called on alignment exception. Attempts to fixup 282 * 283 * Return 1 on success 284 * Return 0 if unable to handle the interrupt 285 * Return -EFAULT if data address is bad 286 * Other negative return values indicate that the instruction can't 287 * be emulated, and the process should be given a SIGBUS. 288 */ 289 290 int fix_alignment(struct pt_regs *regs) 291 { 292 unsigned int instr; 293 struct instruction_op op; 294 int r, type; 295 296 /* 297 * We require a complete register set, if not, then our assembly 298 * is broken 299 */ 300 CHECK_FULL_REGS(regs); 301 302 if (unlikely(__get_user(instr, (unsigned int __user *)regs->nip))) 303 return -EFAULT; 304 if ((regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE)) { 305 /* We don't handle PPC little-endian any more... */ 306 if (cpu_has_feature(CPU_FTR_PPC_LE)) 307 return -EIO; 308 instr = swab32(instr); 309 } 310 311 #ifdef CONFIG_SPE 312 if ((instr >> 26) == 0x4) { 313 int reg = (instr >> 21) & 0x1f; 314 PPC_WARN_ALIGNMENT(spe, regs); 315 return emulate_spe(regs, reg, instr); 316 } 317 #endif 318 319 320 /* 321 * ISA 3.0 (such as P9) copy, copy_first, paste and paste_last alignment 322 * check. 323 * 324 * Send a SIGBUS to the process that caused the fault. 325 * 326 * We do not emulate these because paste may contain additional metadata 327 * when pasting to a co-processor. Furthermore, paste_last is the 328 * synchronisation point for preceding copy/paste sequences. 329 */ 330 if ((instr & 0xfc0006fe) == (PPC_INST_COPY & 0xfc0006fe)) 331 return -EIO; 332 333 r = analyse_instr(&op, regs, instr); 334 if (r < 0) 335 return -EINVAL; 336 337 type = GETTYPE(op.type); 338 if (!OP_IS_LOAD_STORE(type)) { 339 if (op.type != CACHEOP + DCBZ) 340 return -EINVAL; 341 PPC_WARN_ALIGNMENT(dcbz, regs); 342 r = emulate_dcbz(op.ea, regs); 343 } else { 344 if (type == LARX || type == STCX) 345 return -EIO; 346 PPC_WARN_ALIGNMENT(unaligned, regs); 347 r = emulate_loadstore(regs, &op); 348 } 349 350 if (!r) 351 return 1; 352 return r; 353 } 354