1e2be04c7SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
2c3617f72SDavid Howells #ifndef _ASM_POWERPC_SIGCONTEXT_H
3c3617f72SDavid Howells #define _ASM_POWERPC_SIGCONTEXT_H
4c3617f72SDavid Howells 
5c3617f72SDavid Howells /*
6c3617f72SDavid Howells  * This program is free software; you can redistribute it and/or
7c3617f72SDavid Howells  * modify it under the terms of the GNU General Public License
8c3617f72SDavid Howells  * as published by the Free Software Foundation; either version
9c3617f72SDavid Howells  * 2 of the License, or (at your option) any later version.
10c3617f72SDavid Howells  */
11c3617f72SDavid Howells #include <linux/compiler.h>
12c3617f72SDavid Howells #include <asm/ptrace.h>
13c3617f72SDavid Howells #ifdef __powerpc64__
14c3617f72SDavid Howells #include <asm/elf.h>
15c3617f72SDavid Howells #endif
16c3617f72SDavid Howells 
17c3617f72SDavid Howells struct sigcontext {
18c3617f72SDavid Howells 	unsigned long	_unused[4];
19c3617f72SDavid Howells 	int		signal;
20c3617f72SDavid Howells #ifdef __powerpc64__
21c3617f72SDavid Howells 	int		_pad0;
22c3617f72SDavid Howells #endif
23c3617f72SDavid Howells 	unsigned long	handler;
24c3617f72SDavid Howells 	unsigned long	oldmask;
2522a3d03dSMichael Ellerman #ifdef __KERNEL__
2622a3d03dSMichael Ellerman 	struct user_pt_regs __user *regs;
2722a3d03dSMichael Ellerman #else
2822a3d03dSMichael Ellerman 	struct pt_regs	*regs;
2922a3d03dSMichael Ellerman #endif
30c3617f72SDavid Howells #ifdef __powerpc64__
31c3617f72SDavid Howells 	elf_gregset_t	gp_regs;
32c3617f72SDavid Howells 	elf_fpregset_t	fp_regs;
33c3617f72SDavid Howells /*
34c3617f72SDavid Howells  * To maintain compatibility with current implementations the sigcontext is
35c3617f72SDavid Howells  * extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t)
364c576229SAnshuman Khandual  * followed by an unstructured (vmx_reserve) field of 101 doublewords. This
37c3617f72SDavid Howells  * allows the array of vector registers to be quadword aligned independent of
38c3617f72SDavid Howells  * the alignment of the containing sigcontext or ucontext. It is the
39c3617f72SDavid Howells  * responsibility of the code setting the sigcontext to set this pointer to
40c3617f72SDavid Howells  * either NULL (if this processor does not support the VMX feature) or the
41c3617f72SDavid Howells  * address of the first quadword within the allocated (vmx_reserve) area.
42c3617f72SDavid Howells  *
43c3617f72SDavid Howells  * The pointer (v_regs) of vector type (elf_vrreg_t) is type compatible with
44c3617f72SDavid Howells  * an array of 34 quadword entries (elf_vrregset_t).  The entries with
45c3617f72SDavid Howells  * indexes 0-31 contain the corresponding vector registers.  The entry with
46c3617f72SDavid Howells  * index 32 contains the vscr as the last word (offset 12) within the
47c3617f72SDavid Howells  * quadword.  This allows the vscr to be stored as either a quadword (since
48c3617f72SDavid Howells  * it must be copied via a vector register to/from storage) or as a word.
49c3617f72SDavid Howells  * The entry with index 33 contains the vrsave as the first word (offset 0)
50c3617f72SDavid Howells  * within the quadword.
51c3617f72SDavid Howells  *
52c3617f72SDavid Howells  * Part of the VSX data is stored here also by extending vmx_restore
53c3617f72SDavid Howells  * by an additional 32 double words.  Architecturally the layout of
54c3617f72SDavid Howells  * the VSR registers and how they overlap on top of the legacy FPR and
55c3617f72SDavid Howells  * VR registers is shown below:
56c3617f72SDavid Howells  *
57c3617f72SDavid Howells  *                    VSR doubleword 0               VSR doubleword 1
58c3617f72SDavid Howells  *           ----------------------------------------------------------------
59c3617f72SDavid Howells  *   VSR[0]  |             FPR[0]            |                              |
60c3617f72SDavid Howells  *           ----------------------------------------------------------------
61c3617f72SDavid Howells  *   VSR[1]  |             FPR[1]            |                              |
62c3617f72SDavid Howells  *           ----------------------------------------------------------------
63c3617f72SDavid Howells  *           |              ...              |                              |
64c3617f72SDavid Howells  *           |              ...              |                              |
65c3617f72SDavid Howells  *           ----------------------------------------------------------------
66c3617f72SDavid Howells  *   VSR[30] |             FPR[30]           |                              |
67c3617f72SDavid Howells  *           ----------------------------------------------------------------
68c3617f72SDavid Howells  *   VSR[31] |             FPR[31]           |                              |
69c3617f72SDavid Howells  *           ----------------------------------------------------------------
70c3617f72SDavid Howells  *   VSR[32] |                             VR[0]                            |
71c3617f72SDavid Howells  *           ----------------------------------------------------------------
72c3617f72SDavid Howells  *   VSR[33] |                             VR[1]                            |
73c3617f72SDavid Howells  *           ----------------------------------------------------------------
74c3617f72SDavid Howells  *           |                              ...                             |
75c3617f72SDavid Howells  *           |                              ...                             |
76c3617f72SDavid Howells  *           ----------------------------------------------------------------
77c3617f72SDavid Howells  *   VSR[62] |                             VR[30]                           |
78c3617f72SDavid Howells  *           ----------------------------------------------------------------
79c3617f72SDavid Howells  *   VSR[63] |                             VR[31]                           |
80c3617f72SDavid Howells  *           ----------------------------------------------------------------
81c3617f72SDavid Howells  *
82c3617f72SDavid Howells  * FPR/VSR 0-31 doubleword 0 is stored in fp_regs, and VMX/VSR 32-63
83c3617f72SDavid Howells  * is stored at the start of vmx_reserve.  vmx_reserve is extended for
84c3617f72SDavid Howells  * backwards compatility to store VSR 0-31 doubleword 1 after the VMX
85c3617f72SDavid Howells  * registers and vscr/vrsave.
86c3617f72SDavid Howells  */
87c3617f72SDavid Howells 	elf_vrreg_t	__user *v_regs;
884c576229SAnshuman Khandual 	long		vmx_reserve[ELF_NVRREG + ELF_NVRREG + 1 + 32];
89c3617f72SDavid Howells #endif
90c3617f72SDavid Howells };
91c3617f72SDavid Howells 
92c3617f72SDavid Howells #endif /* _ASM_POWERPC_SIGCONTEXT_H */
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