1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright 2016,2017 IBM Corporation. 4 */ 5 #ifndef _ASM_POWERPC_XIVE_H 6 #define _ASM_POWERPC_XIVE_H 7 8 #define XIVE_INVALID_VP 0xffffffff 9 10 #ifdef CONFIG_PPC_XIVE 11 12 /* 13 * Thread Interrupt Management Area (TIMA) 14 * 15 * This is a global MMIO region divided in 4 pages of varying access 16 * permissions, providing access to per-cpu interrupt management 17 * functions. It always identifies the CPU doing the access based 18 * on the PowerBus initiator ID, thus we always access via the 19 * same offset regardless of where the code is executing 20 */ 21 extern void __iomem *xive_tima; 22 extern unsigned long xive_tima_os; 23 24 /* 25 * Offset in the TM area of our current execution level (provided by 26 * the backend) 27 */ 28 extern u32 xive_tima_offset; 29 30 /* 31 * Per-irq data (irq_get_handler_data for normal IRQs), IPIs 32 * have it stored in the xive_cpu structure. We also cache 33 * for normal interrupts the current target CPU. 34 * 35 * This structure is setup by the backend for each interrupt. 36 */ 37 struct xive_irq_data { 38 u64 flags; 39 u64 eoi_page; 40 void __iomem *eoi_mmio; 41 u64 trig_page; 42 void __iomem *trig_mmio; 43 u32 esb_shift; 44 int src_chip; 45 u32 hw_irq; 46 47 /* Setup/used by frontend */ 48 int target; 49 bool saved_p; 50 }; 51 #define XIVE_IRQ_FLAG_STORE_EOI 0x01 52 #define XIVE_IRQ_FLAG_LSI 0x02 53 #define XIVE_IRQ_FLAG_SHIFT_BUG 0x04 54 #define XIVE_IRQ_FLAG_MASK_FW 0x08 55 #define XIVE_IRQ_FLAG_EOI_FW 0x10 56 #define XIVE_IRQ_FLAG_H_INT_ESB 0x20 57 58 /* Special flag set by KVM for excalation interrupts */ 59 #define XIVE_IRQ_NO_EOI 0x80 60 61 #define XIVE_INVALID_CHIP_ID -1 62 63 /* A queue tracking structure in a CPU */ 64 struct xive_q { 65 __be32 *qpage; 66 u32 msk; 67 u32 idx; 68 u32 toggle; 69 u64 eoi_phys; 70 u32 esc_irq; 71 atomic_t count; 72 atomic_t pending_count; 73 u64 guest_qaddr; 74 u32 guest_qshift; 75 }; 76 77 /* Global enable flags for the XIVE support */ 78 extern bool __xive_enabled; 79 80 static inline bool xive_enabled(void) { return __xive_enabled; } 81 82 extern bool xive_spapr_init(void); 83 extern bool xive_native_init(void); 84 extern void xive_smp_probe(void); 85 extern int xive_smp_prepare_cpu(unsigned int cpu); 86 extern void xive_smp_setup_cpu(void); 87 extern void xive_smp_disable_cpu(void); 88 extern void xive_teardown_cpu(void); 89 extern void xive_shutdown(void); 90 extern void xive_flush_interrupt(void); 91 92 /* xmon hook */ 93 extern void xmon_xive_do_dump(int cpu); 94 95 /* APIs used by KVM */ 96 extern u32 xive_native_default_eq_shift(void); 97 extern u32 xive_native_alloc_vp_block(u32 max_vcpus); 98 extern void xive_native_free_vp_block(u32 vp_base); 99 extern int xive_native_populate_irq_data(u32 hw_irq, 100 struct xive_irq_data *data); 101 extern void xive_cleanup_irq_data(struct xive_irq_data *xd); 102 extern u32 xive_native_alloc_irq(void); 103 extern void xive_native_free_irq(u32 irq); 104 extern int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq); 105 106 extern int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio, 107 __be32 *qpage, u32 order, bool can_escalate); 108 extern void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio); 109 110 extern void xive_native_sync_source(u32 hw_irq); 111 extern void xive_native_sync_queue(u32 hw_irq); 112 extern bool is_xive_irq(struct irq_chip *chip); 113 extern int xive_native_enable_vp(u32 vp_id, bool single_escalation); 114 extern int xive_native_disable_vp(u32 vp_id); 115 extern int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id); 116 extern bool xive_native_has_single_escalation(void); 117 118 extern int xive_native_get_queue_info(u32 vp_id, uint32_t prio, 119 u64 *out_qpage, 120 u64 *out_qsize, 121 u64 *out_qeoi_page, 122 u32 *out_escalate_irq, 123 u64 *out_qflags); 124 125 extern int xive_native_get_queue_state(u32 vp_id, uint32_t prio, u32 *qtoggle, 126 u32 *qindex); 127 extern int xive_native_set_queue_state(u32 vp_id, uint32_t prio, u32 qtoggle, 128 u32 qindex); 129 extern int xive_native_get_vp_state(u32 vp_id, u64 *out_state); 130 131 #else 132 133 static inline bool xive_enabled(void) { return false; } 134 135 static inline bool xive_spapr_init(void) { return false; } 136 static inline bool xive_native_init(void) { return false; } 137 static inline void xive_smp_probe(void) { } 138 static inline int xive_smp_prepare_cpu(unsigned int cpu) { return -EINVAL; } 139 static inline void xive_smp_setup_cpu(void) { } 140 static inline void xive_smp_disable_cpu(void) { } 141 static inline void xive_kexec_teardown_cpu(int secondary) { } 142 static inline void xive_shutdown(void) { } 143 static inline void xive_flush_interrupt(void) { } 144 145 static inline u32 xive_native_alloc_vp_block(u32 max_vcpus) { return XIVE_INVALID_VP; } 146 static inline void xive_native_free_vp_block(u32 vp_base) { } 147 148 #endif 149 150 #endif /* _ASM_POWERPC_XIVE_H */ 151