1 /* 2 * Copyright 2016,2017 IBM Corporation. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 */ 9 #ifndef _ASM_POWERPC_XIVE_H 10 #define _ASM_POWERPC_XIVE_H 11 12 #define XIVE_INVALID_VP 0xffffffff 13 14 #ifdef CONFIG_PPC_XIVE 15 16 /* 17 * Thread Interrupt Management Area (TIMA) 18 * 19 * This is a global MMIO region divided in 4 pages of varying access 20 * permissions, providing access to per-cpu interrupt management 21 * functions. It always identifies the CPU doing the access based 22 * on the PowerBus initiator ID, thus we always access via the 23 * same offset regardless of where the code is executing 24 */ 25 extern void __iomem *xive_tima; 26 extern unsigned long xive_tima_os; 27 28 /* 29 * Offset in the TM area of our current execution level (provided by 30 * the backend) 31 */ 32 extern u32 xive_tima_offset; 33 34 /* 35 * Per-irq data (irq_get_handler_data for normal IRQs), IPIs 36 * have it stored in the xive_cpu structure. We also cache 37 * for normal interrupts the current target CPU. 38 * 39 * This structure is setup by the backend for each interrupt. 40 */ 41 struct xive_irq_data { 42 u64 flags; 43 u64 eoi_page; 44 void __iomem *eoi_mmio; 45 u64 trig_page; 46 void __iomem *trig_mmio; 47 u32 esb_shift; 48 int src_chip; 49 u32 hw_irq; 50 51 /* Setup/used by frontend */ 52 int target; 53 bool saved_p; 54 }; 55 #define XIVE_IRQ_FLAG_STORE_EOI 0x01 56 #define XIVE_IRQ_FLAG_LSI 0x02 57 #define XIVE_IRQ_FLAG_SHIFT_BUG 0x04 58 #define XIVE_IRQ_FLAG_MASK_FW 0x08 59 #define XIVE_IRQ_FLAG_EOI_FW 0x10 60 #define XIVE_IRQ_FLAG_H_INT_ESB 0x20 61 62 /* Special flag set by KVM for excalation interrupts */ 63 #define XIVE_IRQ_NO_EOI 0x80 64 65 #define XIVE_INVALID_CHIP_ID -1 66 67 /* A queue tracking structure in a CPU */ 68 struct xive_q { 69 __be32 *qpage; 70 u32 msk; 71 u32 idx; 72 u32 toggle; 73 u64 eoi_phys; 74 u32 esc_irq; 75 atomic_t count; 76 atomic_t pending_count; 77 u64 guest_qaddr; 78 u32 guest_qshift; 79 }; 80 81 /* Global enable flags for the XIVE support */ 82 extern bool __xive_enabled; 83 84 static inline bool xive_enabled(void) { return __xive_enabled; } 85 86 extern bool xive_spapr_init(void); 87 extern bool xive_native_init(void); 88 extern void xive_smp_probe(void); 89 extern int xive_smp_prepare_cpu(unsigned int cpu); 90 extern void xive_smp_setup_cpu(void); 91 extern void xive_smp_disable_cpu(void); 92 extern void xive_teardown_cpu(void); 93 extern void xive_shutdown(void); 94 extern void xive_flush_interrupt(void); 95 96 /* xmon hook */ 97 extern void xmon_xive_do_dump(int cpu); 98 99 /* APIs used by KVM */ 100 extern u32 xive_native_default_eq_shift(void); 101 extern u32 xive_native_alloc_vp_block(u32 max_vcpus); 102 extern void xive_native_free_vp_block(u32 vp_base); 103 extern int xive_native_populate_irq_data(u32 hw_irq, 104 struct xive_irq_data *data); 105 extern void xive_cleanup_irq_data(struct xive_irq_data *xd); 106 extern u32 xive_native_alloc_irq(void); 107 extern void xive_native_free_irq(u32 irq); 108 extern int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq); 109 110 extern int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio, 111 __be32 *qpage, u32 order, bool can_escalate); 112 extern void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio); 113 114 extern void xive_native_sync_source(u32 hw_irq); 115 extern void xive_native_sync_queue(u32 hw_irq); 116 extern bool is_xive_irq(struct irq_chip *chip); 117 extern int xive_native_enable_vp(u32 vp_id, bool single_escalation); 118 extern int xive_native_disable_vp(u32 vp_id); 119 extern int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id); 120 extern bool xive_native_has_single_escalation(void); 121 122 extern int xive_native_get_queue_info(u32 vp_id, uint32_t prio, 123 u64 *out_qpage, 124 u64 *out_qsize, 125 u64 *out_qeoi_page, 126 u32 *out_escalate_irq, 127 u64 *out_qflags); 128 129 extern int xive_native_get_queue_state(u32 vp_id, uint32_t prio, u32 *qtoggle, 130 u32 *qindex); 131 extern int xive_native_set_queue_state(u32 vp_id, uint32_t prio, u32 qtoggle, 132 u32 qindex); 133 extern int xive_native_get_vp_state(u32 vp_id, u64 *out_state); 134 135 #else 136 137 static inline bool xive_enabled(void) { return false; } 138 139 static inline bool xive_spapr_init(void) { return false; } 140 static inline bool xive_native_init(void) { return false; } 141 static inline void xive_smp_probe(void) { } 142 static inline int xive_smp_prepare_cpu(unsigned int cpu) { return -EINVAL; } 143 static inline void xive_smp_setup_cpu(void) { } 144 static inline void xive_smp_disable_cpu(void) { } 145 static inline void xive_kexec_teardown_cpu(int secondary) { } 146 static inline void xive_shutdown(void) { } 147 static inline void xive_flush_interrupt(void) { } 148 149 static inline u32 xive_native_alloc_vp_block(u32 max_vcpus) { return XIVE_INVALID_VP; } 150 static inline void xive_native_free_vp_block(u32 vp_base) { } 151 152 #endif 153 154 #endif /* _ASM_POWERPC_XIVE_H */ 155