12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2243e2511SBenjamin Herrenschmidt /* 3243e2511SBenjamin Herrenschmidt * Copyright 2016,2017 IBM Corporation. 4243e2511SBenjamin Herrenschmidt */ 5243e2511SBenjamin Herrenschmidt #ifndef _ASM_POWERPC_XIVE_H 6243e2511SBenjamin Herrenschmidt #define _ASM_POWERPC_XIVE_H 7243e2511SBenjamin Herrenschmidt 88d0ea29dSHaren Myneni #include <asm/opal-api.h> 98d0ea29dSHaren Myneni 10243e2511SBenjamin Herrenschmidt #define XIVE_INVALID_VP 0xffffffff 11243e2511SBenjamin Herrenschmidt 12243e2511SBenjamin Herrenschmidt #ifdef CONFIG_PPC_XIVE 13243e2511SBenjamin Herrenschmidt 14243e2511SBenjamin Herrenschmidt /* 15243e2511SBenjamin Herrenschmidt * Thread Interrupt Management Area (TIMA) 16243e2511SBenjamin Herrenschmidt * 17243e2511SBenjamin Herrenschmidt * This is a global MMIO region divided in 4 pages of varying access 18243e2511SBenjamin Herrenschmidt * permissions, providing access to per-cpu interrupt management 19243e2511SBenjamin Herrenschmidt * functions. It always identifies the CPU doing the access based 20243e2511SBenjamin Herrenschmidt * on the PowerBus initiator ID, thus we always access via the 21243e2511SBenjamin Herrenschmidt * same offset regardless of where the code is executing 22243e2511SBenjamin Herrenschmidt */ 23243e2511SBenjamin Herrenschmidt extern void __iomem *xive_tima; 2439e9af3dSCédric Le Goater extern unsigned long xive_tima_os; 25243e2511SBenjamin Herrenschmidt 26243e2511SBenjamin Herrenschmidt /* 27243e2511SBenjamin Herrenschmidt * Offset in the TM area of our current execution level (provided by 28243e2511SBenjamin Herrenschmidt * the backend) 29243e2511SBenjamin Herrenschmidt */ 30243e2511SBenjamin Herrenschmidt extern u32 xive_tima_offset; 31243e2511SBenjamin Herrenschmidt 32243e2511SBenjamin Herrenschmidt /* 33243e2511SBenjamin Herrenschmidt * Per-irq data (irq_get_handler_data for normal IRQs), IPIs 34243e2511SBenjamin Herrenschmidt * have it stored in the xive_cpu structure. We also cache 35243e2511SBenjamin Herrenschmidt * for normal interrupts the current target CPU. 36243e2511SBenjamin Herrenschmidt * 37243e2511SBenjamin Herrenschmidt * This structure is setup by the backend for each interrupt. 38243e2511SBenjamin Herrenschmidt */ 39243e2511SBenjamin Herrenschmidt struct xive_irq_data { 40243e2511SBenjamin Herrenschmidt u64 flags; 41243e2511SBenjamin Herrenschmidt u64 eoi_page; 42243e2511SBenjamin Herrenschmidt void __iomem *eoi_mmio; 43243e2511SBenjamin Herrenschmidt u64 trig_page; 44243e2511SBenjamin Herrenschmidt void __iomem *trig_mmio; 45243e2511SBenjamin Herrenschmidt u32 esb_shift; 46243e2511SBenjamin Herrenschmidt int src_chip; 47c58a14a9SCédric Le Goater u32 hw_irq; 48243e2511SBenjamin Herrenschmidt 49243e2511SBenjamin Herrenschmidt /* Setup/used by frontend */ 50243e2511SBenjamin Herrenschmidt int target; 51da15c03bSPaul Mackerras /* 52da15c03bSPaul Mackerras * saved_p means that there is a queue entry for this interrupt 53da15c03bSPaul Mackerras * in some CPU's queue (not including guest vcpu queues), even 54da15c03bSPaul Mackerras * if P is not set in the source ESB. 55da15c03bSPaul Mackerras * stale_p means that there is no queue entry for this interrupt 56da15c03bSPaul Mackerras * in some CPU's queue, even if P is set in the source ESB. 57da15c03bSPaul Mackerras */ 58243e2511SBenjamin Herrenschmidt bool saved_p; 59da15c03bSPaul Mackerras bool stale_p; 60243e2511SBenjamin Herrenschmidt }; 61243e2511SBenjamin Herrenschmidt #define XIVE_IRQ_FLAG_STORE_EOI 0x01 62243e2511SBenjamin Herrenschmidt #define XIVE_IRQ_FLAG_LSI 0x02 634cc0e36dSCédric Le Goater /* #define XIVE_IRQ_FLAG_SHIFT_BUG 0x04 */ /* P9 DD1.0 workaround */ 64*b5277d18SCédric Le Goater /* #define XIVE_IRQ_FLAG_MASK_FW 0x08 */ /* P9 DD1.0 workaround */ 65243e2511SBenjamin Herrenschmidt #define XIVE_IRQ_FLAG_EOI_FW 0x10 66bed81ee1SCédric Le Goater #define XIVE_IRQ_FLAG_H_INT_ESB 0x20 67243e2511SBenjamin Herrenschmidt 687f1c410dSBenjamin Herrenschmidt /* Special flag set by KVM for excalation interrupts */ 694f1c3f7bSCédric Le Goater #define XIVE_IRQ_FLAG_NO_EOI 0x80 707f1c410dSBenjamin Herrenschmidt 71243e2511SBenjamin Herrenschmidt #define XIVE_INVALID_CHIP_ID -1 72243e2511SBenjamin Herrenschmidt 73243e2511SBenjamin Herrenschmidt /* A queue tracking structure in a CPU */ 74243e2511SBenjamin Herrenschmidt struct xive_q { 75243e2511SBenjamin Herrenschmidt __be32 *qpage; 76243e2511SBenjamin Herrenschmidt u32 msk; 77243e2511SBenjamin Herrenschmidt u32 idx; 78243e2511SBenjamin Herrenschmidt u32 toggle; 79243e2511SBenjamin Herrenschmidt u64 eoi_phys; 80243e2511SBenjamin Herrenschmidt u32 esc_irq; 81243e2511SBenjamin Herrenschmidt atomic_t count; 82243e2511SBenjamin Herrenschmidt atomic_t pending_count; 8313ce3297SCédric Le Goater u64 guest_qaddr; 8413ce3297SCédric Le Goater u32 guest_qshift; 85243e2511SBenjamin Herrenschmidt }; 86243e2511SBenjamin Herrenschmidt 87243e2511SBenjamin Herrenschmidt /* Global enable flags for the XIVE support */ 88243e2511SBenjamin Herrenschmidt extern bool __xive_enabled; 89243e2511SBenjamin Herrenschmidt 90243e2511SBenjamin Herrenschmidt static inline bool xive_enabled(void) { return __xive_enabled; } 91243e2511SBenjamin Herrenschmidt 92b059c636SGreg Kurz bool xive_spapr_init(void); 93b059c636SGreg Kurz bool xive_native_init(void); 94b059c636SGreg Kurz void xive_smp_probe(void); 95b059c636SGreg Kurz int xive_smp_prepare_cpu(unsigned int cpu); 96b059c636SGreg Kurz void xive_smp_setup_cpu(void); 97b059c636SGreg Kurz void xive_smp_disable_cpu(void); 98b059c636SGreg Kurz void xive_teardown_cpu(void); 99b059c636SGreg Kurz void xive_shutdown(void); 100b059c636SGreg Kurz void xive_flush_interrupt(void); 101243e2511SBenjamin Herrenschmidt 102243e2511SBenjamin Herrenschmidt /* xmon hook */ 103b059c636SGreg Kurz void xmon_xive_do_dump(int cpu); 104b059c636SGreg Kurz int xmon_xive_get_irq_config(u32 hw_irq, struct irq_data *d); 105243e2511SBenjamin Herrenschmidt 106243e2511SBenjamin Herrenschmidt /* APIs used by KVM */ 107b059c636SGreg Kurz u32 xive_native_default_eq_shift(void); 108b059c636SGreg Kurz u32 xive_native_alloc_vp_block(u32 max_vcpus); 109b059c636SGreg Kurz void xive_native_free_vp_block(u32 vp_base); 110b059c636SGreg Kurz int xive_native_populate_irq_data(u32 hw_irq, 111243e2511SBenjamin Herrenschmidt struct xive_irq_data *data); 112b059c636SGreg Kurz void xive_cleanup_irq_data(struct xive_irq_data *xd); 113b059c636SGreg Kurz void xive_native_free_irq(u32 irq); 114b059c636SGreg Kurz int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq); 115243e2511SBenjamin Herrenschmidt 116b059c636SGreg Kurz int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio, 117243e2511SBenjamin Herrenschmidt __be32 *qpage, u32 order, bool can_escalate); 118b059c636SGreg Kurz void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio); 119243e2511SBenjamin Herrenschmidt 120b059c636SGreg Kurz void xive_native_sync_source(u32 hw_irq); 121b059c636SGreg Kurz void xive_native_sync_queue(u32 hw_irq); 122b059c636SGreg Kurz bool is_xive_irq(struct irq_chip *chip); 123b059c636SGreg Kurz int xive_native_enable_vp(u32 vp_id, bool single_escalation); 124b059c636SGreg Kurz int xive_native_disable_vp(u32 vp_id); 125b059c636SGreg Kurz int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id); 126b059c636SGreg Kurz bool xive_native_has_single_escalation(void); 127243e2511SBenjamin Herrenschmidt 128b059c636SGreg Kurz int xive_native_get_queue_info(u32 vp_id, uint32_t prio, 12988ec6b93SCédric Le Goater u64 *out_qpage, 13088ec6b93SCédric Le Goater u64 *out_qsize, 13188ec6b93SCédric Le Goater u64 *out_qeoi_page, 13288ec6b93SCédric Le Goater u32 *out_escalate_irq, 13388ec6b93SCédric Le Goater u64 *out_qflags); 13488ec6b93SCédric Le Goater 135b059c636SGreg Kurz int xive_native_get_queue_state(u32 vp_id, uint32_t prio, u32 *qtoggle, 13688ec6b93SCédric Le Goater u32 *qindex); 137b059c636SGreg Kurz int xive_native_set_queue_state(u32 vp_id, uint32_t prio, u32 qtoggle, 13888ec6b93SCédric Le Goater u32 qindex); 139b059c636SGreg Kurz int xive_native_get_vp_state(u32 vp_id, u64 *out_state); 140b059c636SGreg Kurz bool xive_native_has_queue_state_support(void); 1418d0ea29dSHaren Myneni extern u32 xive_native_alloc_irq_on_chip(u32 chip_id); 1428d0ea29dSHaren Myneni 1438d0ea29dSHaren Myneni static inline u32 xive_native_alloc_irq(void) 1448d0ea29dSHaren Myneni { 1458d0ea29dSHaren Myneni return xive_native_alloc_irq_on_chip(OPAL_XIVE_ANY_CHIP); 1468d0ea29dSHaren Myneni } 14788ec6b93SCédric Le Goater 148243e2511SBenjamin Herrenschmidt #else 149243e2511SBenjamin Herrenschmidt 150243e2511SBenjamin Herrenschmidt static inline bool xive_enabled(void) { return false; } 151243e2511SBenjamin Herrenschmidt 152eac1e731SCédric Le Goater static inline bool xive_spapr_init(void) { return false; } 153243e2511SBenjamin Herrenschmidt static inline bool xive_native_init(void) { return false; } 154243e2511SBenjamin Herrenschmidt static inline void xive_smp_probe(void) { } 15538833faaSMathieu Malaterre static inline int xive_smp_prepare_cpu(unsigned int cpu) { return -EINVAL; } 156243e2511SBenjamin Herrenschmidt static inline void xive_smp_setup_cpu(void) { } 157243e2511SBenjamin Herrenschmidt static inline void xive_smp_disable_cpu(void) { } 158243e2511SBenjamin Herrenschmidt static inline void xive_shutdown(void) { } 159243e2511SBenjamin Herrenschmidt static inline void xive_flush_interrupt(void) { } 160243e2511SBenjamin Herrenschmidt 161243e2511SBenjamin Herrenschmidt static inline u32 xive_native_alloc_vp_block(u32 max_vcpus) { return XIVE_INVALID_VP; } 162243e2511SBenjamin Herrenschmidt static inline void xive_native_free_vp_block(u32 vp_base) { } 163243e2511SBenjamin Herrenschmidt 164243e2511SBenjamin Herrenschmidt #endif 165243e2511SBenjamin Herrenschmidt 166243e2511SBenjamin Herrenschmidt #endif /* _ASM_POWERPC_XIVE_H */ 167