1243e2511SBenjamin Herrenschmidt /* 2243e2511SBenjamin Herrenschmidt * Copyright 2016,2017 IBM Corporation. 3243e2511SBenjamin Herrenschmidt * 4243e2511SBenjamin Herrenschmidt * This program is free software; you can redistribute it and/or 5243e2511SBenjamin Herrenschmidt * modify it under the terms of the GNU General Public License 6243e2511SBenjamin Herrenschmidt * as published by the Free Software Foundation; either version 7243e2511SBenjamin Herrenschmidt * 2 of the License, or (at your option) any later version. 8243e2511SBenjamin Herrenschmidt */ 9243e2511SBenjamin Herrenschmidt #ifndef _ASM_POWERPC_XIVE_H 10243e2511SBenjamin Herrenschmidt #define _ASM_POWERPC_XIVE_H 11243e2511SBenjamin Herrenschmidt 12243e2511SBenjamin Herrenschmidt #define XIVE_INVALID_VP 0xffffffff 13243e2511SBenjamin Herrenschmidt 14243e2511SBenjamin Herrenschmidt #ifdef CONFIG_PPC_XIVE 15243e2511SBenjamin Herrenschmidt 16243e2511SBenjamin Herrenschmidt /* 17243e2511SBenjamin Herrenschmidt * Thread Interrupt Management Area (TIMA) 18243e2511SBenjamin Herrenschmidt * 19243e2511SBenjamin Herrenschmidt * This is a global MMIO region divided in 4 pages of varying access 20243e2511SBenjamin Herrenschmidt * permissions, providing access to per-cpu interrupt management 21243e2511SBenjamin Herrenschmidt * functions. It always identifies the CPU doing the access based 22243e2511SBenjamin Herrenschmidt * on the PowerBus initiator ID, thus we always access via the 23243e2511SBenjamin Herrenschmidt * same offset regardless of where the code is executing 24243e2511SBenjamin Herrenschmidt */ 25243e2511SBenjamin Herrenschmidt extern void __iomem *xive_tima; 26243e2511SBenjamin Herrenschmidt 27243e2511SBenjamin Herrenschmidt /* 28243e2511SBenjamin Herrenschmidt * Offset in the TM area of our current execution level (provided by 29243e2511SBenjamin Herrenschmidt * the backend) 30243e2511SBenjamin Herrenschmidt */ 31243e2511SBenjamin Herrenschmidt extern u32 xive_tima_offset; 32243e2511SBenjamin Herrenschmidt 33243e2511SBenjamin Herrenschmidt /* 34243e2511SBenjamin Herrenschmidt * Per-irq data (irq_get_handler_data for normal IRQs), IPIs 35243e2511SBenjamin Herrenschmidt * have it stored in the xive_cpu structure. We also cache 36243e2511SBenjamin Herrenschmidt * for normal interrupts the current target CPU. 37243e2511SBenjamin Herrenschmidt * 38243e2511SBenjamin Herrenschmidt * This structure is setup by the backend for each interrupt. 39243e2511SBenjamin Herrenschmidt */ 40243e2511SBenjamin Herrenschmidt struct xive_irq_data { 41243e2511SBenjamin Herrenschmidt u64 flags; 42243e2511SBenjamin Herrenschmidt u64 eoi_page; 43243e2511SBenjamin Herrenschmidt void __iomem *eoi_mmio; 44243e2511SBenjamin Herrenschmidt u64 trig_page; 45243e2511SBenjamin Herrenschmidt void __iomem *trig_mmio; 46243e2511SBenjamin Herrenschmidt u32 esb_shift; 47243e2511SBenjamin Herrenschmidt int src_chip; 48243e2511SBenjamin Herrenschmidt 49243e2511SBenjamin Herrenschmidt /* Setup/used by frontend */ 50243e2511SBenjamin Herrenschmidt int target; 51243e2511SBenjamin Herrenschmidt bool saved_p; 52243e2511SBenjamin Herrenschmidt }; 53243e2511SBenjamin Herrenschmidt #define XIVE_IRQ_FLAG_STORE_EOI 0x01 54243e2511SBenjamin Herrenschmidt #define XIVE_IRQ_FLAG_LSI 0x02 55243e2511SBenjamin Herrenschmidt #define XIVE_IRQ_FLAG_SHIFT_BUG 0x04 56243e2511SBenjamin Herrenschmidt #define XIVE_IRQ_FLAG_MASK_FW 0x08 57243e2511SBenjamin Herrenschmidt #define XIVE_IRQ_FLAG_EOI_FW 0x10 58243e2511SBenjamin Herrenschmidt 59243e2511SBenjamin Herrenschmidt #define XIVE_INVALID_CHIP_ID -1 60243e2511SBenjamin Herrenschmidt 61243e2511SBenjamin Herrenschmidt /* A queue tracking structure in a CPU */ 62243e2511SBenjamin Herrenschmidt struct xive_q { 63243e2511SBenjamin Herrenschmidt __be32 *qpage; 64243e2511SBenjamin Herrenschmidt u32 msk; 65243e2511SBenjamin Herrenschmidt u32 idx; 66243e2511SBenjamin Herrenschmidt u32 toggle; 67243e2511SBenjamin Herrenschmidt u64 eoi_phys; 68243e2511SBenjamin Herrenschmidt u32 esc_irq; 69243e2511SBenjamin Herrenschmidt atomic_t count; 70243e2511SBenjamin Herrenschmidt atomic_t pending_count; 71243e2511SBenjamin Herrenschmidt }; 72243e2511SBenjamin Herrenschmidt 73243e2511SBenjamin Herrenschmidt /* 74243e2511SBenjamin Herrenschmidt * "magic" Event State Buffer (ESB) MMIO offsets. 75243e2511SBenjamin Herrenschmidt * 76243e2511SBenjamin Herrenschmidt * Each interrupt source has a 2-bit state machine called ESB 77243e2511SBenjamin Herrenschmidt * which can be controlled by MMIO. It's made of 2 bits, P and 78243e2511SBenjamin Herrenschmidt * Q. P indicates that an interrupt is pending (has been sent 79243e2511SBenjamin Herrenschmidt * to a queue and is waiting for an EOI). Q indicates that the 80243e2511SBenjamin Herrenschmidt * interrupt has been triggered while pending. 81243e2511SBenjamin Herrenschmidt * 82243e2511SBenjamin Herrenschmidt * This acts as a coalescing mechanism in order to guarantee 83243e2511SBenjamin Herrenschmidt * that a given interrupt only occurs at most once in a queue. 84243e2511SBenjamin Herrenschmidt * 85243e2511SBenjamin Herrenschmidt * When doing an EOI, the Q bit will indicate if the interrupt 86243e2511SBenjamin Herrenschmidt * needs to be re-triggered. 87243e2511SBenjamin Herrenschmidt * 88243e2511SBenjamin Herrenschmidt * The following offsets into the ESB MMIO allow to read or 89243e2511SBenjamin Herrenschmidt * manipulate the PQ bits. They must be used with an 8-bytes 90243e2511SBenjamin Herrenschmidt * load instruction. They all return the previous state of the 91243e2511SBenjamin Herrenschmidt * interrupt (atomically). 92243e2511SBenjamin Herrenschmidt * 93243e2511SBenjamin Herrenschmidt * Additionally, some ESB pages support doing an EOI via a 94243e2511SBenjamin Herrenschmidt * store at 0 and some ESBs support doing a trigger via a 95243e2511SBenjamin Herrenschmidt * separate trigger page. 96243e2511SBenjamin Herrenschmidt */ 97243e2511SBenjamin Herrenschmidt #define XIVE_ESB_GET 0x800 98243e2511SBenjamin Herrenschmidt #define XIVE_ESB_SET_PQ_00 0xc00 99243e2511SBenjamin Herrenschmidt #define XIVE_ESB_SET_PQ_01 0xd00 100243e2511SBenjamin Herrenschmidt #define XIVE_ESB_SET_PQ_10 0xe00 101243e2511SBenjamin Herrenschmidt #define XIVE_ESB_SET_PQ_11 0xf00 102243e2511SBenjamin Herrenschmidt #define XIVE_ESB_MASK XIVE_ESB_SET_PQ_01 103243e2511SBenjamin Herrenschmidt 104243e2511SBenjamin Herrenschmidt #define XIVE_ESB_VAL_P 0x2 105243e2511SBenjamin Herrenschmidt #define XIVE_ESB_VAL_Q 0x1 106243e2511SBenjamin Herrenschmidt 107243e2511SBenjamin Herrenschmidt /* Global enable flags for the XIVE support */ 108243e2511SBenjamin Herrenschmidt extern bool __xive_enabled; 109243e2511SBenjamin Herrenschmidt 110243e2511SBenjamin Herrenschmidt static inline bool xive_enabled(void) { return __xive_enabled; } 111243e2511SBenjamin Herrenschmidt 112243e2511SBenjamin Herrenschmidt extern bool xive_native_init(void); 113243e2511SBenjamin Herrenschmidt extern void xive_smp_probe(void); 114243e2511SBenjamin Herrenschmidt extern int xive_smp_prepare_cpu(unsigned int cpu); 115243e2511SBenjamin Herrenschmidt extern void xive_smp_setup_cpu(void); 116243e2511SBenjamin Herrenschmidt extern void xive_smp_disable_cpu(void); 117243e2511SBenjamin Herrenschmidt extern void xive_kexec_teardown_cpu(int secondary); 118243e2511SBenjamin Herrenschmidt extern void xive_shutdown(void); 119243e2511SBenjamin Herrenschmidt extern void xive_flush_interrupt(void); 120243e2511SBenjamin Herrenschmidt 121243e2511SBenjamin Herrenschmidt /* xmon hook */ 122243e2511SBenjamin Herrenschmidt extern void xmon_xive_do_dump(int cpu); 123243e2511SBenjamin Herrenschmidt 124243e2511SBenjamin Herrenschmidt /* APIs used by KVM */ 125243e2511SBenjamin Herrenschmidt extern u32 xive_native_default_eq_shift(void); 126243e2511SBenjamin Herrenschmidt extern u32 xive_native_alloc_vp_block(u32 max_vcpus); 127243e2511SBenjamin Herrenschmidt extern void xive_native_free_vp_block(u32 vp_base); 128243e2511SBenjamin Herrenschmidt extern int xive_native_populate_irq_data(u32 hw_irq, 129243e2511SBenjamin Herrenschmidt struct xive_irq_data *data); 130243e2511SBenjamin Herrenschmidt extern void xive_cleanup_irq_data(struct xive_irq_data *xd); 131243e2511SBenjamin Herrenschmidt extern u32 xive_native_alloc_irq(void); 132243e2511SBenjamin Herrenschmidt extern void xive_native_free_irq(u32 irq); 133243e2511SBenjamin Herrenschmidt extern int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq); 134243e2511SBenjamin Herrenschmidt 135243e2511SBenjamin Herrenschmidt extern int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio, 136243e2511SBenjamin Herrenschmidt __be32 *qpage, u32 order, bool can_escalate); 137243e2511SBenjamin Herrenschmidt extern void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio); 138243e2511SBenjamin Herrenschmidt 139243e2511SBenjamin Herrenschmidt extern bool __xive_irq_trigger(struct xive_irq_data *xd); 140243e2511SBenjamin Herrenschmidt extern bool __xive_irq_retrigger(struct xive_irq_data *xd); 141243e2511SBenjamin Herrenschmidt extern void xive_do_source_eoi(u32 hw_irq, struct xive_irq_data *xd); 142243e2511SBenjamin Herrenschmidt 143243e2511SBenjamin Herrenschmidt extern bool is_xive_irq(struct irq_chip *chip); 144243e2511SBenjamin Herrenschmidt 145243e2511SBenjamin Herrenschmidt #else 146243e2511SBenjamin Herrenschmidt 147243e2511SBenjamin Herrenschmidt static inline bool xive_enabled(void) { return false; } 148243e2511SBenjamin Herrenschmidt 149243e2511SBenjamin Herrenschmidt static inline bool xive_native_init(void) { return false; } 150243e2511SBenjamin Herrenschmidt static inline void xive_smp_probe(void) { } 151243e2511SBenjamin Herrenschmidt extern inline int xive_smp_prepare_cpu(unsigned int cpu) { return -EINVAL; } 152243e2511SBenjamin Herrenschmidt static inline void xive_smp_setup_cpu(void) { } 153243e2511SBenjamin Herrenschmidt static inline void xive_smp_disable_cpu(void) { } 154243e2511SBenjamin Herrenschmidt static inline void xive_kexec_teardown_cpu(int secondary) { } 155243e2511SBenjamin Herrenschmidt static inline void xive_shutdown(void) { } 156243e2511SBenjamin Herrenschmidt static inline void xive_flush_interrupt(void) { } 157243e2511SBenjamin Herrenschmidt 158243e2511SBenjamin Herrenschmidt static inline u32 xive_native_alloc_vp_block(u32 max_vcpus) { return XIVE_INVALID_VP; } 159243e2511SBenjamin Herrenschmidt static inline void xive_native_free_vp_block(u32 vp_base) { } 160243e2511SBenjamin Herrenschmidt 161243e2511SBenjamin Herrenschmidt #endif 162243e2511SBenjamin Herrenschmidt 163243e2511SBenjamin Herrenschmidt #endif /* _ASM_POWERPC_XIVE_H */ 164