1 /*
2  * Copyright 2016,2017 IBM Corporation.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * as published by the Free Software Foundation; either version
7  * 2 of the License, or (at your option) any later version.
8  */
9 #ifndef _ASM_POWERPC_XIVE_REGS_H
10 #define _ASM_POWERPC_XIVE_REGS_H
11 
12 /*
13  * "magic" Event State Buffer (ESB) MMIO offsets.
14  *
15  * Each interrupt source has a 2-bit state machine called ESB
16  * which can be controlled by MMIO. It's made of 2 bits, P and
17  * Q. P indicates that an interrupt is pending (has been sent
18  * to a queue and is waiting for an EOI). Q indicates that the
19  * interrupt has been triggered while pending.
20  *
21  * This acts as a coalescing mechanism in order to guarantee
22  * that a given interrupt only occurs at most once in a queue.
23  *
24  * When doing an EOI, the Q bit will indicate if the interrupt
25  * needs to be re-triggered.
26  *
27  * The following offsets into the ESB MMIO allow to read or
28  * manipulate the PQ bits. They must be used with an 8-bytes
29  * load instruction. They all return the previous state of the
30  * interrupt (atomically).
31  *
32  * Additionally, some ESB pages support doing an EOI via a
33  * store at 0 and some ESBs support doing a trigger via a
34  * separate trigger page.
35  */
36 #define XIVE_ESB_STORE_EOI	0x400 /* Store */
37 #define XIVE_ESB_LOAD_EOI	0x000 /* Load */
38 #define XIVE_ESB_GET		0x800 /* Load */
39 #define XIVE_ESB_SET_PQ_00	0xc00 /* Load */
40 #define XIVE_ESB_SET_PQ_01	0xd00 /* Load */
41 #define XIVE_ESB_SET_PQ_10	0xe00 /* Load */
42 #define XIVE_ESB_SET_PQ_11	0xf00 /* Load */
43 
44 #define XIVE_ESB_VAL_P		0x2
45 #define XIVE_ESB_VAL_Q		0x1
46 
47 /*
48  * Thread Management (aka "TM") registers
49  */
50 
51 /* TM register offsets */
52 #define TM_QW0_USER		0x000 /* All rings */
53 #define TM_QW1_OS		0x010 /* Ring 0..2 */
54 #define TM_QW2_HV_POOL		0x020 /* Ring 0..1 */
55 #define TM_QW3_HV_PHYS		0x030 /* Ring 0..1 */
56 
57 /* Byte offsets inside a QW             QW0 QW1 QW2 QW3 */
58 #define TM_NSR			0x0  /*  +   +   -   +  */
59 #define TM_CPPR			0x1  /*  -   +   -   +  */
60 #define TM_IPB			0x2  /*  -   +   +   +  */
61 #define TM_LSMFB		0x3  /*  -   +   +   +  */
62 #define TM_ACK_CNT		0x4  /*  -   +   -   -  */
63 #define TM_INC			0x5  /*  -   +   -   +  */
64 #define TM_AGE			0x6  /*  -   +   -   +  */
65 #define TM_PIPR			0x7  /*  -   +   -   +  */
66 
67 #define TM_WORD0		0x0
68 #define TM_WORD1		0x4
69 
70 /*
71  * QW word 2 contains the valid bit at the top and other fields
72  * depending on the QW.
73  */
74 #define TM_WORD2		0x8
75 #define   TM_QW0W2_VU		PPC_BIT32(0)
76 #define   TM_QW0W2_LOGIC_SERV	PPC_BITMASK32(1,31) // XX 2,31 ?
77 #define   TM_QW1W2_VO		PPC_BIT32(0)
78 #define   TM_QW1W2_OS_CAM	PPC_BITMASK32(8,31)
79 #define   TM_QW2W2_VP		PPC_BIT32(0)
80 #define   TM_QW2W2_POOL_CAM	PPC_BITMASK32(8,31)
81 #define   TM_QW3W2_VT		PPC_BIT32(0)
82 #define   TM_QW3W2_LP		PPC_BIT32(6)
83 #define   TM_QW3W2_LE		PPC_BIT32(7)
84 #define   TM_QW3W2_T		PPC_BIT32(31)
85 
86 /*
87  * In addition to normal loads to "peek" and writes (only when invalid)
88  * using 4 and 8 bytes accesses, the above registers support these
89  * "special" byte operations:
90  *
91  *   - Byte load from QW0[NSR] - User level NSR (EBB)
92  *   - Byte store to QW0[NSR] - User level NSR (EBB)
93  *   - Byte load/store to QW1[CPPR] and QW3[CPPR] - CPPR access
94  *   - Byte load from QW3[TM_WORD2] - Read VT||00000||LP||LE on thrd 0
95  *                                    otherwise VT||0000000
96  *   - Byte store to QW3[TM_WORD2] - Set VT bit (and LP/LE if present)
97  *
98  * Then we have all these "special" CI ops at these offset that trigger
99  * all sorts of side effects:
100  */
101 #define TM_SPC_ACK_EBB		0x800	/* Load8 ack EBB to reg*/
102 #define TM_SPC_ACK_OS_REG	0x810	/* Load16 ack OS irq to reg */
103 #define TM_SPC_PUSH_USR_CTX	0x808	/* Store32 Push/Validate user context */
104 #define TM_SPC_PULL_USR_CTX	0x808	/* Load32 Pull/Invalidate user context */
105 #define TM_SPC_SET_OS_PENDING	0x812	/* Store8 Set OS irq pending bit */
106 #define TM_SPC_PULL_OS_CTX	0x818	/* Load32/Load64 Pull/Invalidate OS context to reg */
107 #define TM_SPC_PULL_POOL_CTX	0x828	/* Load32/Load64 Pull/Invalidate Pool context to reg*/
108 #define TM_SPC_ACK_HV_REG	0x830	/* Load16 ack HV irq to reg */
109 #define TM_SPC_PULL_USR_CTX_OL	0xc08	/* Store8 Pull/Inval usr ctx to odd line */
110 #define TM_SPC_ACK_OS_EL	0xc10	/* Store8 ack OS irq to even line */
111 #define TM_SPC_ACK_HV_POOL_EL	0xc20	/* Store8 ack HV evt pool to even line */
112 #define TM_SPC_ACK_HV_EL	0xc30	/* Store8 ack HV irq to even line */
113 /* XXX more... */
114 
115 /* NSR fields for the various QW ack types */
116 #define TM_QW0_NSR_EB		PPC_BIT8(0)
117 #define TM_QW1_NSR_EO		PPC_BIT8(0)
118 #define TM_QW3_NSR_HE		PPC_BITMASK8(0,1)
119 #define  TM_QW3_NSR_HE_NONE	0
120 #define  TM_QW3_NSR_HE_POOL	1
121 #define  TM_QW3_NSR_HE_PHYS	2
122 #define  TM_QW3_NSR_HE_LSI	3
123 #define TM_QW3_NSR_I		PPC_BIT8(2)
124 #define TM_QW3_NSR_GRP_LVL	PPC_BIT8(3,7)
125 
126 /* Utilities to manipulate these (originaly from OPAL) */
127 #define MASK_TO_LSH(m)		(__builtin_ffsl(m) - 1)
128 #define GETFIELD(m, v)		(((v) & (m)) >> MASK_TO_LSH(m))
129 #define SETFIELD(m, v, val)				\
130 	(((v) & ~(m)) |	((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m)))
131 
132 #endif /* _ASM_POWERPC_XIVE_REGS_H */
133