12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2243e2511SBenjamin Herrenschmidt /* 3243e2511SBenjamin Herrenschmidt * Copyright 2016,2017 IBM Corporation. 4243e2511SBenjamin Herrenschmidt */ 5243e2511SBenjamin Herrenschmidt #ifndef _ASM_POWERPC_XIVE_REGS_H 6243e2511SBenjamin Herrenschmidt #define _ASM_POWERPC_XIVE_REGS_H 7243e2511SBenjamin Herrenschmidt 8243e2511SBenjamin Herrenschmidt /* 912c1f339SBenjamin Herrenschmidt * "magic" Event State Buffer (ESB) MMIO offsets. 1012c1f339SBenjamin Herrenschmidt * 1112c1f339SBenjamin Herrenschmidt * Each interrupt source has a 2-bit state machine called ESB 1212c1f339SBenjamin Herrenschmidt * which can be controlled by MMIO. It's made of 2 bits, P and 1312c1f339SBenjamin Herrenschmidt * Q. P indicates that an interrupt is pending (has been sent 1412c1f339SBenjamin Herrenschmidt * to a queue and is waiting for an EOI). Q indicates that the 1512c1f339SBenjamin Herrenschmidt * interrupt has been triggered while pending. 1612c1f339SBenjamin Herrenschmidt * 1712c1f339SBenjamin Herrenschmidt * This acts as a coalescing mechanism in order to guarantee 1812c1f339SBenjamin Herrenschmidt * that a given interrupt only occurs at most once in a queue. 1912c1f339SBenjamin Herrenschmidt * 2012c1f339SBenjamin Herrenschmidt * When doing an EOI, the Q bit will indicate if the interrupt 2112c1f339SBenjamin Herrenschmidt * needs to be re-triggered. 2212c1f339SBenjamin Herrenschmidt * 2312c1f339SBenjamin Herrenschmidt * The following offsets into the ESB MMIO allow to read or 2412c1f339SBenjamin Herrenschmidt * manipulate the PQ bits. They must be used with an 8-bytes 2512c1f339SBenjamin Herrenschmidt * load instruction. They all return the previous state of the 2612c1f339SBenjamin Herrenschmidt * interrupt (atomically). 2712c1f339SBenjamin Herrenschmidt * 2812c1f339SBenjamin Herrenschmidt * Additionally, some ESB pages support doing an EOI via a 2912c1f339SBenjamin Herrenschmidt * store at 0 and some ESBs support doing a trigger via a 3012c1f339SBenjamin Herrenschmidt * separate trigger page. 3112c1f339SBenjamin Herrenschmidt */ 3212c1f339SBenjamin Herrenschmidt #define XIVE_ESB_STORE_EOI 0x400 /* Store */ 3312c1f339SBenjamin Herrenschmidt #define XIVE_ESB_LOAD_EOI 0x000 /* Load */ 3412c1f339SBenjamin Herrenschmidt #define XIVE_ESB_GET 0x800 /* Load */ 3512c1f339SBenjamin Herrenschmidt #define XIVE_ESB_SET_PQ_00 0xc00 /* Load */ 3612c1f339SBenjamin Herrenschmidt #define XIVE_ESB_SET_PQ_01 0xd00 /* Load */ 3712c1f339SBenjamin Herrenschmidt #define XIVE_ESB_SET_PQ_10 0xe00 /* Load */ 3812c1f339SBenjamin Herrenschmidt #define XIVE_ESB_SET_PQ_11 0xf00 /* Load */ 3912c1f339SBenjamin Herrenschmidt 40b1f9be93SCédric Le Goater /* 41b1f9be93SCédric Le Goater * Load-after-store ordering 42b1f9be93SCédric Le Goater * 43b1f9be93SCédric Le Goater * Adding this offset to the load address will enforce 44b1f9be93SCédric Le Goater * load-after-store ordering. This is required to use StoreEOI. 45b1f9be93SCédric Le Goater */ 46b1f9be93SCédric Le Goater #define XIVE_ESB_LD_ST_MO 0x40 /* Load-after-store ordering */ 47b1f9be93SCédric Le Goater 4812c1f339SBenjamin Herrenschmidt #define XIVE_ESB_VAL_P 0x2 4912c1f339SBenjamin Herrenschmidt #define XIVE_ESB_VAL_Q 0x1 5017328f21SFrederic Barrat #define XIVE_ESB_INVALID 0xFF 5112c1f339SBenjamin Herrenschmidt 5212c1f339SBenjamin Herrenschmidt /* 53243e2511SBenjamin Herrenschmidt * Thread Management (aka "TM") registers 54243e2511SBenjamin Herrenschmidt */ 55243e2511SBenjamin Herrenschmidt 56243e2511SBenjamin Herrenschmidt /* TM register offsets */ 57243e2511SBenjamin Herrenschmidt #define TM_QW0_USER 0x000 /* All rings */ 58243e2511SBenjamin Herrenschmidt #define TM_QW1_OS 0x010 /* Ring 0..2 */ 59243e2511SBenjamin Herrenschmidt #define TM_QW2_HV_POOL 0x020 /* Ring 0..1 */ 60243e2511SBenjamin Herrenschmidt #define TM_QW3_HV_PHYS 0x030 /* Ring 0..1 */ 61243e2511SBenjamin Herrenschmidt 62243e2511SBenjamin Herrenschmidt /* Byte offsets inside a QW QW0 QW1 QW2 QW3 */ 63243e2511SBenjamin Herrenschmidt #define TM_NSR 0x0 /* + + - + */ 64243e2511SBenjamin Herrenschmidt #define TM_CPPR 0x1 /* - + - + */ 65243e2511SBenjamin Herrenschmidt #define TM_IPB 0x2 /* - + + + */ 66243e2511SBenjamin Herrenschmidt #define TM_LSMFB 0x3 /* - + + + */ 67243e2511SBenjamin Herrenschmidt #define TM_ACK_CNT 0x4 /* - + - - */ 68243e2511SBenjamin Herrenschmidt #define TM_INC 0x5 /* - + - + */ 69243e2511SBenjamin Herrenschmidt #define TM_AGE 0x6 /* - + - + */ 70243e2511SBenjamin Herrenschmidt #define TM_PIPR 0x7 /* - + - + */ 71243e2511SBenjamin Herrenschmidt 72243e2511SBenjamin Herrenschmidt #define TM_WORD0 0x0 73243e2511SBenjamin Herrenschmidt #define TM_WORD1 0x4 74243e2511SBenjamin Herrenschmidt 75243e2511SBenjamin Herrenschmidt /* 76243e2511SBenjamin Herrenschmidt * QW word 2 contains the valid bit at the top and other fields 77243e2511SBenjamin Herrenschmidt * depending on the QW. 78243e2511SBenjamin Herrenschmidt */ 79243e2511SBenjamin Herrenschmidt #define TM_WORD2 0x8 80243e2511SBenjamin Herrenschmidt #define TM_QW0W2_VU PPC_BIT32(0) 81243e2511SBenjamin Herrenschmidt #define TM_QW0W2_LOGIC_SERV PPC_BITMASK32(1,31) // XX 2,31 ? 82243e2511SBenjamin Herrenschmidt #define TM_QW1W2_VO PPC_BIT32(0) 83243e2511SBenjamin Herrenschmidt #define TM_QW1W2_OS_CAM PPC_BITMASK32(8,31) 84243e2511SBenjamin Herrenschmidt #define TM_QW2W2_VP PPC_BIT32(0) 85243e2511SBenjamin Herrenschmidt #define TM_QW2W2_POOL_CAM PPC_BITMASK32(8,31) 86243e2511SBenjamin Herrenschmidt #define TM_QW3W2_VT PPC_BIT32(0) 87243e2511SBenjamin Herrenschmidt #define TM_QW3W2_LP PPC_BIT32(6) 88243e2511SBenjamin Herrenschmidt #define TM_QW3W2_LE PPC_BIT32(7) 89243e2511SBenjamin Herrenschmidt #define TM_QW3W2_T PPC_BIT32(31) 90243e2511SBenjamin Herrenschmidt 91243e2511SBenjamin Herrenschmidt /* 92243e2511SBenjamin Herrenschmidt * In addition to normal loads to "peek" and writes (only when invalid) 93243e2511SBenjamin Herrenschmidt * using 4 and 8 bytes accesses, the above registers support these 94243e2511SBenjamin Herrenschmidt * "special" byte operations: 95243e2511SBenjamin Herrenschmidt * 96243e2511SBenjamin Herrenschmidt * - Byte load from QW0[NSR] - User level NSR (EBB) 97243e2511SBenjamin Herrenschmidt * - Byte store to QW0[NSR] - User level NSR (EBB) 98243e2511SBenjamin Herrenschmidt * - Byte load/store to QW1[CPPR] and QW3[CPPR] - CPPR access 99243e2511SBenjamin Herrenschmidt * - Byte load from QW3[TM_WORD2] - Read VT||00000||LP||LE on thrd 0 100243e2511SBenjamin Herrenschmidt * otherwise VT||0000000 101243e2511SBenjamin Herrenschmidt * - Byte store to QW3[TM_WORD2] - Set VT bit (and LP/LE if present) 102243e2511SBenjamin Herrenschmidt * 103243e2511SBenjamin Herrenschmidt * Then we have all these "special" CI ops at these offset that trigger 104243e2511SBenjamin Herrenschmidt * all sorts of side effects: 105243e2511SBenjamin Herrenschmidt */ 106243e2511SBenjamin Herrenschmidt #define TM_SPC_ACK_EBB 0x800 /* Load8 ack EBB to reg*/ 107243e2511SBenjamin Herrenschmidt #define TM_SPC_ACK_OS_REG 0x810 /* Load16 ack OS irq to reg */ 108243e2511SBenjamin Herrenschmidt #define TM_SPC_PUSH_USR_CTX 0x808 /* Store32 Push/Validate user context */ 109243e2511SBenjamin Herrenschmidt #define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user context */ 110243e2511SBenjamin Herrenschmidt #define TM_SPC_SET_OS_PENDING 0x812 /* Store8 Set OS irq pending bit */ 111243e2511SBenjamin Herrenschmidt #define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS context to reg */ 112243e2511SBenjamin Herrenschmidt #define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool context to reg*/ 113243e2511SBenjamin Herrenschmidt #define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */ 114243e2511SBenjamin Herrenschmidt #define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd line */ 115243e2511SBenjamin Herrenschmidt #define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */ 116243e2511SBenjamin Herrenschmidt #define TM_SPC_ACK_HV_POOL_EL 0xc20 /* Store8 ack HV evt pool to even line */ 117243e2511SBenjamin Herrenschmidt #define TM_SPC_ACK_HV_EL 0xc30 /* Store8 ack HV irq to even line */ 118243e2511SBenjamin Herrenschmidt /* XXX more... */ 119243e2511SBenjamin Herrenschmidt 120243e2511SBenjamin Herrenschmidt /* NSR fields for the various QW ack types */ 121243e2511SBenjamin Herrenschmidt #define TM_QW0_NSR_EB PPC_BIT8(0) 122243e2511SBenjamin Herrenschmidt #define TM_QW1_NSR_EO PPC_BIT8(0) 123243e2511SBenjamin Herrenschmidt #define TM_QW3_NSR_HE PPC_BITMASK8(0,1) 124243e2511SBenjamin Herrenschmidt #define TM_QW3_NSR_HE_NONE 0 125243e2511SBenjamin Herrenschmidt #define TM_QW3_NSR_HE_POOL 1 126243e2511SBenjamin Herrenschmidt #define TM_QW3_NSR_HE_PHYS 2 127243e2511SBenjamin Herrenschmidt #define TM_QW3_NSR_HE_LSI 3 128243e2511SBenjamin Herrenschmidt #define TM_QW3_NSR_I PPC_BIT8(2) 129243e2511SBenjamin Herrenschmidt #define TM_QW3_NSR_GRP_LVL PPC_BIT8(3,7) 130243e2511SBenjamin Herrenschmidt 131243e2511SBenjamin Herrenschmidt #endif /* _ASM_POWERPC_XIVE_REGS_H */ 132