1b8b572e1SStephen Rothwell /* 2b8b572e1SStephen Rothwell * (C) Copyright 2005 Tundra Semiconductor Corp. 3b8b572e1SStephen Rothwell * Alex Bounine, <alexandreb at tundra.com). 4b8b572e1SStephen Rothwell * 5b8b572e1SStephen Rothwell * See file CREDITS for list of people who contributed to this 6b8b572e1SStephen Rothwell * project. 7b8b572e1SStephen Rothwell * 8b8b572e1SStephen Rothwell * This program is free software; you can redistribute it and/or 9b8b572e1SStephen Rothwell * modify it under the terms of the GNU General Public License as 10b8b572e1SStephen Rothwell * published by the Free Software Foundation; either version 2 of 11b8b572e1SStephen Rothwell * the License, or (at your option) any later version. 12b8b572e1SStephen Rothwell * 13b8b572e1SStephen Rothwell * This program is distributed in the hope that it will be useful, 14b8b572e1SStephen Rothwell * but WITHOUT ANY WARRANTY; without even the implied warranty of 15b8b572e1SStephen Rothwell * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16b8b572e1SStephen Rothwell * GNU General Public License for more details. 17b8b572e1SStephen Rothwell * 18b8b572e1SStephen Rothwell * You should have received a copy of the GNU General Public License 19b8b572e1SStephen Rothwell * along with this program; if not, write to the Free Software 20b8b572e1SStephen Rothwell * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21b8b572e1SStephen Rothwell * MA 02111-1307 USA 22b8b572e1SStephen Rothwell */ 23b8b572e1SStephen Rothwell 24b8b572e1SStephen Rothwell /* 25b8b572e1SStephen Rothwell * definitions for interrupt controller initialization and external interrupt 26b8b572e1SStephen Rothwell * demultiplexing on TSI108EMU/SVB boards. 27b8b572e1SStephen Rothwell */ 28b8b572e1SStephen Rothwell 29b8b572e1SStephen Rothwell #ifndef _ASM_POWERPC_TSI108_IRQ_H 30b8b572e1SStephen Rothwell #define _ASM_POWERPC_TSI108_IRQ_H 31b8b572e1SStephen Rothwell 32b8b572e1SStephen Rothwell /* 33b8b572e1SStephen Rothwell * Tsi108 interrupts 34b8b572e1SStephen Rothwell */ 35b8b572e1SStephen Rothwell #ifndef TSI108_IRQ_REG_BASE 36b8b572e1SStephen Rothwell #define TSI108_IRQ_REG_BASE 0 37b8b572e1SStephen Rothwell #endif 38b8b572e1SStephen Rothwell 39b8b572e1SStephen Rothwell #define TSI108_IRQ(x) (TSI108_IRQ_REG_BASE + (x)) 40b8b572e1SStephen Rothwell 41b8b572e1SStephen Rothwell #define TSI108_MAX_VECTORS (36 + 4) /* 36 sources + PCI INT demux */ 42b8b572e1SStephen Rothwell #define MAX_TASK_PRIO 0xF 43b8b572e1SStephen Rothwell 44b8b572e1SStephen Rothwell #define TSI108_IRQ_SPURIOUS (TSI108_MAX_VECTORS) 45b8b572e1SStephen Rothwell 46b8b572e1SStephen Rothwell #define DEFAULT_PRIO_LVL 10 /* initial priority level */ 47b8b572e1SStephen Rothwell 48b8b572e1SStephen Rothwell /* Interrupt vectors assignment to external and internal 49b8b572e1SStephen Rothwell * sources of requests. */ 50b8b572e1SStephen Rothwell 51b8b572e1SStephen Rothwell /* EXTERNAL INTERRUPT SOURCES */ 52b8b572e1SStephen Rothwell 53b8b572e1SStephen Rothwell #define IRQ_TSI108_EXT_INT0 TSI108_IRQ(0) /* External Source at INT[0] */ 54b8b572e1SStephen Rothwell #define IRQ_TSI108_EXT_INT1 TSI108_IRQ(1) /* External Source at INT[1] */ 55b8b572e1SStephen Rothwell #define IRQ_TSI108_EXT_INT2 TSI108_IRQ(2) /* External Source at INT[2] */ 56b8b572e1SStephen Rothwell #define IRQ_TSI108_EXT_INT3 TSI108_IRQ(3) /* External Source at INT[3] */ 57b8b572e1SStephen Rothwell 58b8b572e1SStephen Rothwell /* INTERNAL INTERRUPT SOURCES */ 59b8b572e1SStephen Rothwell 60b8b572e1SStephen Rothwell #define IRQ_TSI108_RESERVED0 TSI108_IRQ(4) /* Reserved IRQ */ 61b8b572e1SStephen Rothwell #define IRQ_TSI108_RESERVED1 TSI108_IRQ(5) /* Reserved IRQ */ 62b8b572e1SStephen Rothwell #define IRQ_TSI108_RESERVED2 TSI108_IRQ(6) /* Reserved IRQ */ 63b8b572e1SStephen Rothwell #define IRQ_TSI108_RESERVED3 TSI108_IRQ(7) /* Reserved IRQ */ 64b8b572e1SStephen Rothwell #define IRQ_TSI108_DMA0 TSI108_IRQ(8) /* DMA0 */ 65b8b572e1SStephen Rothwell #define IRQ_TSI108_DMA1 TSI108_IRQ(9) /* DMA1 */ 66b8b572e1SStephen Rothwell #define IRQ_TSI108_DMA2 TSI108_IRQ(10) /* DMA2 */ 67b8b572e1SStephen Rothwell #define IRQ_TSI108_DMA3 TSI108_IRQ(11) /* DMA3 */ 68b8b572e1SStephen Rothwell #define IRQ_TSI108_UART0 TSI108_IRQ(12) /* UART0 */ 69b8b572e1SStephen Rothwell #define IRQ_TSI108_UART1 TSI108_IRQ(13) /* UART1 */ 70b8b572e1SStephen Rothwell #define IRQ_TSI108_I2C TSI108_IRQ(14) /* I2C */ 71b8b572e1SStephen Rothwell #define IRQ_TSI108_GPIO TSI108_IRQ(15) /* GPIO */ 72b8b572e1SStephen Rothwell #define IRQ_TSI108_GIGE0 TSI108_IRQ(16) /* GIGE0 */ 73b8b572e1SStephen Rothwell #define IRQ_TSI108_GIGE1 TSI108_IRQ(17) /* GIGE1 */ 74b8b572e1SStephen Rothwell #define IRQ_TSI108_RESERVED4 TSI108_IRQ(18) /* Reserved IRQ */ 75b8b572e1SStephen Rothwell #define IRQ_TSI108_HLP TSI108_IRQ(19) /* HLP */ 76b8b572e1SStephen Rothwell #define IRQ_TSI108_SDRAM TSI108_IRQ(20) /* SDC */ 77b8b572e1SStephen Rothwell #define IRQ_TSI108_PROC_IF TSI108_IRQ(21) /* Processor IF */ 78b8b572e1SStephen Rothwell #define IRQ_TSI108_RESERVED5 TSI108_IRQ(22) /* Reserved IRQ */ 79b8b572e1SStephen Rothwell #define IRQ_TSI108_PCI TSI108_IRQ(23) /* PCI/X block */ 80b8b572e1SStephen Rothwell 81b8b572e1SStephen Rothwell #define IRQ_TSI108_MBOX0 TSI108_IRQ(24) /* Mailbox 0 register */ 82b8b572e1SStephen Rothwell #define IRQ_TSI108_MBOX1 TSI108_IRQ(25) /* Mailbox 1 register */ 83b8b572e1SStephen Rothwell #define IRQ_TSI108_MBOX2 TSI108_IRQ(26) /* Mailbox 2 register */ 84b8b572e1SStephen Rothwell #define IRQ_TSI108_MBOX3 TSI108_IRQ(27) /* Mailbox 3 register */ 85b8b572e1SStephen Rothwell 86b8b572e1SStephen Rothwell #define IRQ_TSI108_DBELL0 TSI108_IRQ(28) /* Doorbell 0 */ 87b8b572e1SStephen Rothwell #define IRQ_TSI108_DBELL1 TSI108_IRQ(29) /* Doorbell 1 */ 88b8b572e1SStephen Rothwell #define IRQ_TSI108_DBELL2 TSI108_IRQ(30) /* Doorbell 2 */ 89b8b572e1SStephen Rothwell #define IRQ_TSI108_DBELL3 TSI108_IRQ(31) /* Doorbell 3 */ 90b8b572e1SStephen Rothwell 91b8b572e1SStephen Rothwell #define IRQ_TSI108_TIMER0 TSI108_IRQ(32) /* Global Timer 0 */ 92b8b572e1SStephen Rothwell #define IRQ_TSI108_TIMER1 TSI108_IRQ(33) /* Global Timer 1 */ 93b8b572e1SStephen Rothwell #define IRQ_TSI108_TIMER2 TSI108_IRQ(34) /* Global Timer 2 */ 94b8b572e1SStephen Rothwell #define IRQ_TSI108_TIMER3 TSI108_IRQ(35) /* Global Timer 3 */ 95b8b572e1SStephen Rothwell 96b8b572e1SStephen Rothwell /* 97b8b572e1SStephen Rothwell * PCI bus INTA# - INTD# lines demultiplexor 98b8b572e1SStephen Rothwell */ 99b8b572e1SStephen Rothwell #define IRQ_PCI_INTAD_BASE TSI108_IRQ(36) 100b8b572e1SStephen Rothwell #define IRQ_PCI_INTA (IRQ_PCI_INTAD_BASE + 0) 101b8b572e1SStephen Rothwell #define IRQ_PCI_INTB (IRQ_PCI_INTAD_BASE + 1) 102b8b572e1SStephen Rothwell #define IRQ_PCI_INTC (IRQ_PCI_INTAD_BASE + 2) 103b8b572e1SStephen Rothwell #define IRQ_PCI_INTD (IRQ_PCI_INTAD_BASE + 3) 104b8b572e1SStephen Rothwell #define NUM_PCI_IRQS (4) 105b8b572e1SStephen Rothwell 106b8b572e1SStephen Rothwell /* number of entries in vector dispatch table */ 107b8b572e1SStephen Rothwell #define IRQ_TSI108_TAB_SIZE (TSI108_MAX_VECTORS + 1) 108b8b572e1SStephen Rothwell 109b8b572e1SStephen Rothwell /* Mapping of MPIC outputs to processors' interrupt pins */ 110b8b572e1SStephen Rothwell 111b8b572e1SStephen Rothwell #define IDIR_INT_OUT0 0x1 112b8b572e1SStephen Rothwell #define IDIR_INT_OUT1 0x2 113b8b572e1SStephen Rothwell #define IDIR_INT_OUT2 0x4 114b8b572e1SStephen Rothwell #define IDIR_INT_OUT3 0x8 115b8b572e1SStephen Rothwell 116b8b572e1SStephen Rothwell /*--------------------------------------------------------------- 117b8b572e1SStephen Rothwell * IRQ line configuration parameters */ 118b8b572e1SStephen Rothwell 119b8b572e1SStephen Rothwell /* Interrupt delivery modes */ 120b8b572e1SStephen Rothwell typedef enum { 121b8b572e1SStephen Rothwell TSI108_IRQ_DIRECTED, 122b8b572e1SStephen Rothwell TSI108_IRQ_DISTRIBUTED, 123b8b572e1SStephen Rothwell } TSI108_IRQ_MODE; 124b8b572e1SStephen Rothwell #endif /* _ASM_POWERPC_TSI108_IRQ_H */ 125