1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM 4 */ 5 6 struct pt_regs; 7 8 /* 9 * We don't allow single-stepping an mtmsrd that would clear 10 * MSR_RI, since that would make the exception unrecoverable. 11 * Since we need to single-step to proceed from a breakpoint, 12 * we don't allow putting a breakpoint on an mtmsrd instruction. 13 * Similarly we don't allow breakpoints on rfid instructions. 14 * These macros tell us if an instruction is a mtmsrd or rfid. 15 * Note that IS_MTMSRD returns true for both an mtmsr (32-bit) 16 * and an mtmsrd (64-bit). 17 */ 18 #define IS_MTMSRD(instr) (((instr) & 0xfc0007be) == 0x7c000124) 19 #define IS_RFID(instr) (((instr) & 0xfc0007fe) == 0x4c000024) 20 #define IS_RFI(instr) (((instr) & 0xfc0007fe) == 0x4c000064) 21 22 enum instruction_type { 23 COMPUTE, /* arith/logical/CR op, etc. */ 24 LOAD, /* load and store types need to be contiguous */ 25 LOAD_MULTI, 26 LOAD_FP, 27 LOAD_VMX, 28 LOAD_VSX, 29 STORE, 30 STORE_MULTI, 31 STORE_FP, 32 STORE_VMX, 33 STORE_VSX, 34 LARX, 35 STCX, 36 BRANCH, 37 MFSPR, 38 MTSPR, 39 CACHEOP, 40 BARRIER, 41 SYSCALL, 42 MFMSR, 43 MTMSR, 44 RFI, 45 INTERRUPT, 46 UNKNOWN 47 }; 48 49 #define INSTR_TYPE_MASK 0x1f 50 51 #define OP_IS_LOAD_STORE(type) (LOAD <= (type) && (type) <= STCX) 52 53 /* Compute flags, ORed in with type */ 54 #define SETREG 0x20 55 #define SETCC 0x40 56 #define SETXER 0x80 57 58 /* Branch flags, ORed in with type */ 59 #define SETLK 0x20 60 #define BRTAKEN 0x40 61 #define DECCTR 0x80 62 63 /* Load/store flags, ORed in with type */ 64 #define SIGNEXT 0x20 65 #define UPDATE 0x40 /* matches bit in opcode 31 instructions */ 66 #define BYTEREV 0x80 67 #define FPCONV 0x100 68 69 /* Barrier type field, ORed in with type */ 70 #define BARRIER_MASK 0xe0 71 #define BARRIER_SYNC 0x00 72 #define BARRIER_ISYNC 0x20 73 #define BARRIER_EIEIO 0x40 74 #define BARRIER_LWSYNC 0x60 75 #define BARRIER_PTESYNC 0x80 76 77 /* Cacheop values, ORed in with type */ 78 #define CACHEOP_MASK 0x700 79 #define DCBST 0 80 #define DCBF 0x100 81 #define DCBTST 0x200 82 #define DCBT 0x300 83 #define ICBI 0x400 84 #define DCBZ 0x500 85 86 /* VSX flags values */ 87 #define VSX_FPCONV 1 /* do floating point SP/DP conversion */ 88 #define VSX_SPLAT 2 /* store loaded value into all elements */ 89 #define VSX_LDLEFT 4 /* load VSX register from left */ 90 #define VSX_CHECK_VEC 8 /* check MSR_VEC not MSR_VSX for reg >= 32 */ 91 92 /* Size field in type word */ 93 #define SIZE(n) ((n) << 12) 94 #define GETSIZE(w) ((w) >> 12) 95 96 #define GETTYPE(t) ((t) & INSTR_TYPE_MASK) 97 98 #define MKOP(t, f, s) ((t) | (f) | SIZE(s)) 99 100 struct instruction_op { 101 int type; 102 int reg; 103 unsigned long val; 104 /* For LOAD/STORE/LARX/STCX */ 105 unsigned long ea; 106 int update_reg; 107 /* For MFSPR */ 108 int spr; 109 u32 ccval; 110 u32 xerval; 111 u8 element_size; /* for VSX/VMX loads/stores */ 112 u8 vsx_flags; 113 }; 114 115 union vsx_reg { 116 u8 b[16]; 117 u16 h[8]; 118 u32 w[4]; 119 unsigned long d[2]; 120 float fp[4]; 121 double dp[2]; 122 __vector128 v; 123 }; 124 125 /* 126 * Decode an instruction, and return information about it in *op 127 * without changing *regs. 128 * 129 * Return value is 1 if the instruction can be emulated just by 130 * updating *regs with the information in *op, -1 if we need the 131 * GPRs but *regs doesn't contain the full register set, or 0 132 * otherwise. 133 */ 134 extern int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, 135 unsigned int instr); 136 137 /* 138 * Emulate an instruction that can be executed just by updating 139 * fields in *regs. 140 */ 141 void emulate_update_regs(struct pt_regs *reg, struct instruction_op *op); 142 143 /* 144 * Emulate instructions that cause a transfer of control, 145 * arithmetic/logical instructions, loads and stores, 146 * cache operations and barriers. 147 * 148 * Returns 1 if the instruction was emulated successfully, 149 * 0 if it could not be emulated, or -1 for an instruction that 150 * should not be emulated (rfid, mtmsrd clearing MSR_RI, etc.). 151 */ 152 extern int emulate_step(struct pt_regs *regs, unsigned int instr); 153 154 /* 155 * Emulate a load or store instruction by reading/writing the 156 * memory of the current process. FP/VMX/VSX registers are assumed 157 * to hold live values if the appropriate enable bit in regs->msr is 158 * set; otherwise this will use the saved values in the thread struct 159 * for user-mode accesses. 160 */ 161 extern int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op); 162 163 extern void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg, 164 const void *mem, bool cross_endian); 165 extern void emulate_vsx_store(struct instruction_op *op, 166 const union vsx_reg *reg, void *mem, 167 bool cross_endian); 168 extern int emulate_dcbz(unsigned long ea, struct pt_regs *regs); 169