1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM 4 */ 5 #include <asm/inst.h> 6 7 struct pt_regs; 8 9 /* 10 * We don't allow single-stepping an mtmsrd that would clear 11 * MSR_RI, since that would make the exception unrecoverable. 12 * Since we need to single-step to proceed from a breakpoint, 13 * we don't allow putting a breakpoint on an mtmsrd instruction. 14 * Similarly we don't allow breakpoints on rfid instructions. 15 * These macros tell us if an instruction is a mtmsrd or rfid. 16 * Note that IS_MTMSRD returns true for both an mtmsr (32-bit) 17 * and an mtmsrd (64-bit). 18 */ 19 #define IS_MTMSRD(instr) ((ppc_inst_val(instr) & 0xfc0007be) == 0x7c000124) 20 #define IS_RFID(instr) ((ppc_inst_val(instr) & 0xfc0007fe) == 0x4c000024) 21 #define IS_RFI(instr) ((ppc_inst_val(instr) & 0xfc0007fe) == 0x4c000064) 22 23 enum instruction_type { 24 COMPUTE, /* arith/logical/CR op, etc. */ 25 LOAD, /* load and store types need to be contiguous */ 26 LOAD_MULTI, 27 LOAD_FP, 28 LOAD_VMX, 29 LOAD_VSX, 30 STORE, 31 STORE_MULTI, 32 STORE_FP, 33 STORE_VMX, 34 STORE_VSX, 35 LARX, 36 STCX, 37 BRANCH, 38 MFSPR, 39 MTSPR, 40 CACHEOP, 41 BARRIER, 42 SYSCALL, 43 MFMSR, 44 MTMSR, 45 RFI, 46 INTERRUPT, 47 UNKNOWN 48 }; 49 50 #define INSTR_TYPE_MASK 0x1f 51 52 #define OP_IS_LOAD(type) ((LOAD <= (type) && (type) <= LOAD_VSX) || (type) == LARX) 53 #define OP_IS_STORE(type) ((STORE <= (type) && (type) <= STORE_VSX) || (type) == STCX) 54 #define OP_IS_LOAD_STORE(type) (LOAD <= (type) && (type) <= STCX) 55 56 /* Compute flags, ORed in with type */ 57 #define SETREG 0x20 58 #define SETCC 0x40 59 #define SETXER 0x80 60 61 /* Branch flags, ORed in with type */ 62 #define SETLK 0x20 63 #define BRTAKEN 0x40 64 #define DECCTR 0x80 65 66 /* Load/store flags, ORed in with type */ 67 #define SIGNEXT 0x20 68 #define UPDATE 0x40 /* matches bit in opcode 31 instructions */ 69 #define BYTEREV 0x80 70 #define FPCONV 0x100 71 72 /* Barrier type field, ORed in with type */ 73 #define BARRIER_MASK 0xe0 74 #define BARRIER_SYNC 0x00 75 #define BARRIER_ISYNC 0x20 76 #define BARRIER_EIEIO 0x40 77 #define BARRIER_LWSYNC 0x60 78 #define BARRIER_PTESYNC 0x80 79 80 /* Cacheop values, ORed in with type */ 81 #define CACHEOP_MASK 0x700 82 #define DCBST 0 83 #define DCBF 0x100 84 #define DCBTST 0x200 85 #define DCBT 0x300 86 #define ICBI 0x400 87 #define DCBZ 0x500 88 89 /* VSX flags values */ 90 #define VSX_FPCONV 1 /* do floating point SP/DP conversion */ 91 #define VSX_SPLAT 2 /* store loaded value into all elements */ 92 #define VSX_LDLEFT 4 /* load VSX register from left */ 93 #define VSX_CHECK_VEC 8 /* check MSR_VEC not MSR_VSX for reg >= 32 */ 94 95 /* Prefixed flag, ORed in with type */ 96 #define PREFIXED 0x800 97 98 /* Size field in type word */ 99 #define SIZE(n) ((n) << 12) 100 #define GETSIZE(w) ((w) >> 12) 101 102 #define GETTYPE(t) ((t) & INSTR_TYPE_MASK) 103 #define GETLENGTH(t) (((t) & PREFIXED) ? 8 : 4) 104 105 #define MKOP(t, f, s) ((t) | (f) | SIZE(s)) 106 107 struct instruction_op { 108 int type; 109 int reg; 110 unsigned long val; 111 /* For LOAD/STORE/LARX/STCX */ 112 unsigned long ea; 113 int update_reg; 114 /* For MFSPR */ 115 int spr; 116 u32 ccval; 117 u32 xerval; 118 u8 element_size; /* for VSX/VMX loads/stores */ 119 u8 vsx_flags; 120 }; 121 122 union vsx_reg { 123 u8 b[16]; 124 u16 h[8]; 125 u32 w[4]; 126 unsigned long d[2]; 127 float fp[4]; 128 double dp[2]; 129 __vector128 v; 130 }; 131 132 /* 133 * Decode an instruction, and return information about it in *op 134 * without changing *regs. 135 * 136 * Return value is 1 if the instruction can be emulated just by 137 * updating *regs with the information in *op, -1 if we need the 138 * GPRs but *regs doesn't contain the full register set, or 0 139 * otherwise. 140 */ 141 extern int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, 142 struct ppc_inst instr); 143 144 /* 145 * Emulate an instruction that can be executed just by updating 146 * fields in *regs. 147 */ 148 void emulate_update_regs(struct pt_regs *reg, struct instruction_op *op); 149 150 /* 151 * Emulate instructions that cause a transfer of control, 152 * arithmetic/logical instructions, loads and stores, 153 * cache operations and barriers. 154 * 155 * Returns 1 if the instruction was emulated successfully, 156 * 0 if it could not be emulated, or -1 for an instruction that 157 * should not be emulated (rfid, mtmsrd clearing MSR_RI, etc.). 158 */ 159 extern int emulate_step(struct pt_regs *regs, struct ppc_inst instr); 160 161 /* 162 * Emulate a load or store instruction by reading/writing the 163 * memory of the current process. FP/VMX/VSX registers are assumed 164 * to hold live values if the appropriate enable bit in regs->msr is 165 * set; otherwise this will use the saved values in the thread struct 166 * for user-mode accesses. 167 */ 168 extern int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op); 169 170 extern void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg, 171 const void *mem, bool cross_endian); 172 extern void emulate_vsx_store(struct instruction_op *op, 173 const union vsx_reg *reg, void *mem, 174 bool cross_endian); 175 extern int emulate_dcbz(unsigned long ea, struct pt_regs *regs); 176