1 /* 2 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 */ 9 10 struct pt_regs; 11 12 /* 13 * We don't allow single-stepping an mtmsrd that would clear 14 * MSR_RI, since that would make the exception unrecoverable. 15 * Since we need to single-step to proceed from a breakpoint, 16 * we don't allow putting a breakpoint on an mtmsrd instruction. 17 * Similarly we don't allow breakpoints on rfid instructions. 18 * These macros tell us if an instruction is a mtmsrd or rfid. 19 * Note that IS_MTMSRD returns true for both an mtmsr (32-bit) 20 * and an mtmsrd (64-bit). 21 */ 22 #define IS_MTMSRD(instr) (((instr) & 0xfc0007be) == 0x7c000124) 23 #define IS_RFID(instr) (((instr) & 0xfc0007fe) == 0x4c000024) 24 #define IS_RFI(instr) (((instr) & 0xfc0007fe) == 0x4c000064) 25 26 enum instruction_type { 27 COMPUTE, /* arith/logical/CR op, etc. */ 28 LOAD, /* load and store types need to be contiguous */ 29 LOAD_MULTI, 30 LOAD_FP, 31 LOAD_VMX, 32 LOAD_VSX, 33 STORE, 34 STORE_MULTI, 35 STORE_FP, 36 STORE_VMX, 37 STORE_VSX, 38 LARX, 39 STCX, 40 BRANCH, 41 MFSPR, 42 MTSPR, 43 CACHEOP, 44 BARRIER, 45 SYSCALL, 46 MFMSR, 47 MTMSR, 48 RFI, 49 INTERRUPT, 50 UNKNOWN 51 }; 52 53 #define INSTR_TYPE_MASK 0x1f 54 55 #define OP_IS_LOAD_STORE(type) (LOAD <= (type) && (type) <= STCX) 56 57 /* Compute flags, ORed in with type */ 58 #define SETREG 0x20 59 #define SETCC 0x40 60 #define SETXER 0x80 61 62 /* Branch flags, ORed in with type */ 63 #define SETLK 0x20 64 #define BRTAKEN 0x40 65 #define DECCTR 0x80 66 67 /* Load/store flags, ORed in with type */ 68 #define SIGNEXT 0x20 69 #define UPDATE 0x40 /* matches bit in opcode 31 instructions */ 70 #define BYTEREV 0x80 71 #define FPCONV 0x100 72 73 /* Barrier type field, ORed in with type */ 74 #define BARRIER_MASK 0xe0 75 #define BARRIER_SYNC 0x00 76 #define BARRIER_ISYNC 0x20 77 #define BARRIER_EIEIO 0x40 78 #define BARRIER_LWSYNC 0x60 79 #define BARRIER_PTESYNC 0x80 80 81 /* Cacheop values, ORed in with type */ 82 #define CACHEOP_MASK 0x700 83 #define DCBST 0 84 #define DCBF 0x100 85 #define DCBTST 0x200 86 #define DCBT 0x300 87 #define ICBI 0x400 88 #define DCBZ 0x500 89 90 /* VSX flags values */ 91 #define VSX_FPCONV 1 /* do floating point SP/DP conversion */ 92 #define VSX_SPLAT 2 /* store loaded value into all elements */ 93 #define VSX_LDLEFT 4 /* load VSX register from left */ 94 #define VSX_CHECK_VEC 8 /* check MSR_VEC not MSR_VSX for reg >= 32 */ 95 96 /* Size field in type word */ 97 #define SIZE(n) ((n) << 12) 98 #define GETSIZE(w) ((w) >> 12) 99 100 #define MKOP(t, f, s) ((t) | (f) | SIZE(s)) 101 102 struct instruction_op { 103 int type; 104 int reg; 105 unsigned long val; 106 /* For LOAD/STORE/LARX/STCX */ 107 unsigned long ea; 108 int update_reg; 109 /* For MFSPR */ 110 int spr; 111 u32 ccval; 112 u32 xerval; 113 u8 element_size; /* for VSX/VMX loads/stores */ 114 u8 vsx_flags; 115 }; 116 117 union vsx_reg { 118 u8 b[16]; 119 u16 h[8]; 120 u32 w[4]; 121 unsigned long d[2]; 122 float fp[4]; 123 double dp[2]; 124 __vector128 v; 125 }; 126 127 /* 128 * Decode an instruction, and return information about it in *op 129 * without changing *regs. 130 * 131 * Return value is 1 if the instruction can be emulated just by 132 * updating *regs with the information in *op, -1 if we need the 133 * GPRs but *regs doesn't contain the full register set, or 0 134 * otherwise. 135 */ 136 extern int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, 137 unsigned int instr); 138 139 /* 140 * Emulate an instruction that can be executed just by updating 141 * fields in *regs. 142 */ 143 void emulate_update_regs(struct pt_regs *reg, struct instruction_op *op); 144 145 /* 146 * Emulate instructions that cause a transfer of control, 147 * arithmetic/logical instructions, loads and stores, 148 * cache operations and barriers. 149 * 150 * Returns 1 if the instruction was emulated successfully, 151 * 0 if it could not be emulated, or -1 for an instruction that 152 * should not be emulated (rfid, mtmsrd clearing MSR_RI, etc.). 153 */ 154 extern int emulate_step(struct pt_regs *regs, unsigned int instr); 155 156 /* 157 * Emulate a load or store instruction by reading/writing the 158 * memory of the current process. FP/VMX/VSX registers are assumed 159 * to hold live values if the appropriate enable bit in regs->msr is 160 * set; otherwise this will use the saved values in the thread struct 161 * for user-mode accesses. 162 */ 163 extern int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op); 164 165 extern void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg, 166 const void *mem, bool cross_endian); 167 extern void emulate_vsx_store(struct instruction_op *op, 168 const union vsx_reg *reg, void *mem, 169 bool cross_endian); 170 extern int emulate_dcbz(unsigned long ea, struct pt_regs *regs); 171