1 /* 2 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 */ 9 10 struct pt_regs; 11 12 /* 13 * We don't allow single-stepping an mtmsrd that would clear 14 * MSR_RI, since that would make the exception unrecoverable. 15 * Since we need to single-step to proceed from a breakpoint, 16 * we don't allow putting a breakpoint on an mtmsrd instruction. 17 * Similarly we don't allow breakpoints on rfid instructions. 18 * These macros tell us if an instruction is a mtmsrd or rfid. 19 * Note that IS_MTMSRD returns true for both an mtmsr (32-bit) 20 * and an mtmsrd (64-bit). 21 */ 22 #define IS_MTMSRD(instr) (((instr) & 0xfc0007be) == 0x7c000124) 23 #define IS_RFID(instr) (((instr) & 0xfc0007fe) == 0x4c000024) 24 #define IS_RFI(instr) (((instr) & 0xfc0007fe) == 0x4c000064) 25 26 /* Emulate instructions that cause a transfer of control. */ 27 extern int emulate_step(struct pt_regs *regs, unsigned int instr); 28 29 enum instruction_type { 30 COMPUTE, /* arith/logical/CR op, etc. */ 31 LOAD, 32 LOAD_MULTI, 33 LOAD_FP, 34 LOAD_VMX, 35 LOAD_VSX, 36 STORE, 37 STORE_MULTI, 38 STORE_FP, 39 STORE_VMX, 40 STORE_VSX, 41 LARX, 42 STCX, 43 BRANCH, 44 MFSPR, 45 MTSPR, 46 CACHEOP, 47 BARRIER, 48 SYSCALL, 49 MFMSR, 50 MTMSR, 51 RFI, 52 INTERRUPT, 53 UNKNOWN 54 }; 55 56 #define INSTR_TYPE_MASK 0x1f 57 58 /* Load/store flags, ORed in with type */ 59 #define SIGNEXT 0x20 60 #define UPDATE 0x40 /* matches bit in opcode 31 instructions */ 61 #define BYTEREV 0x80 62 63 /* Cacheop values, ORed in with type */ 64 #define CACHEOP_MASK 0x700 65 #define DCBST 0 66 #define DCBF 0x100 67 #define DCBTST 0x200 68 #define DCBT 0x300 69 #define ICBI 0x400 70 71 /* Size field in type word */ 72 #define SIZE(n) ((n) << 8) 73 #define GETSIZE(w) ((w) >> 8) 74 75 #define MKOP(t, f, s) ((t) | (f) | SIZE(s)) 76 77 struct instruction_op { 78 int type; 79 int reg; 80 unsigned long val; 81 /* For LOAD/STORE/LARX/STCX */ 82 unsigned long ea; 83 int update_reg; 84 /* For MFSPR */ 85 int spr; 86 }; 87 88 extern int analyse_instr(struct instruction_op *op, struct pt_regs *regs, 89 unsigned int instr); 90