1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Security related feature bit definitions.
4  *
5  * Copyright 2018, Michael Ellerman, IBM Corporation.
6  */
7 
8 #ifndef _ASM_POWERPC_SECURITY_FEATURES_H
9 #define _ASM_POWERPC_SECURITY_FEATURES_H
10 
11 
12 extern unsigned long powerpc_security_features;
13 extern bool rfi_flush;
14 
15 static inline void security_ftr_set(unsigned long feature)
16 {
17 	powerpc_security_features |= feature;
18 }
19 
20 static inline void security_ftr_clear(unsigned long feature)
21 {
22 	powerpc_security_features &= ~feature;
23 }
24 
25 static inline bool security_ftr_enabled(unsigned long feature)
26 {
27 	return !!(powerpc_security_features & feature);
28 }
29 
30 
31 // Features indicating support for Spectre/Meltdown mitigations
32 
33 // The L1-D cache can be flushed with ori r30,r30,0
34 #define SEC_FTR_L1D_FLUSH_ORI30		0x0000000000000001ull
35 
36 // The L1-D cache can be flushed with mtspr 882,r0 (aka SPRN_TRIG2)
37 #define SEC_FTR_L1D_FLUSH_TRIG2		0x0000000000000002ull
38 
39 // ori r31,r31,0 acts as a speculation barrier
40 #define SEC_FTR_SPEC_BAR_ORI31		0x0000000000000004ull
41 
42 // Speculation past bctr is disabled
43 #define SEC_FTR_BCCTRL_SERIALISED	0x0000000000000008ull
44 
45 // Entries in L1-D are private to a SMT thread
46 #define SEC_FTR_L1D_THREAD_PRIV		0x0000000000000010ull
47 
48 // Indirect branch prediction cache disabled
49 #define SEC_FTR_COUNT_CACHE_DISABLED	0x0000000000000020ull
50 
51 
52 // Features indicating need for Spectre/Meltdown mitigations
53 
54 // The L1-D cache should be flushed on MSR[HV] 1->0 transition (hypervisor to guest)
55 #define SEC_FTR_L1D_FLUSH_HV		0x0000000000000040ull
56 
57 // The L1-D cache should be flushed on MSR[PR] 0->1 transition (kernel to userspace)
58 #define SEC_FTR_L1D_FLUSH_PR		0x0000000000000080ull
59 
60 // A speculation barrier should be used for bounds checks (Spectre variant 1)
61 #define SEC_FTR_BNDS_CHK_SPEC_BAR	0x0000000000000100ull
62 
63 // Firmware configuration indicates user favours security over performance
64 #define SEC_FTR_FAVOUR_SECURITY		0x0000000000000200ull
65 
66 
67 // Features enabled by default
68 #define SEC_FTR_DEFAULT \
69 	(SEC_FTR_L1D_FLUSH_HV | \
70 	 SEC_FTR_L1D_FLUSH_PR | \
71 	 SEC_FTR_BNDS_CHK_SPEC_BAR | \
72 	 SEC_FTR_FAVOUR_SECURITY)
73 
74 #endif /* _ASM_POWERPC_SECURITY_FEATURES_H */
75