1 /* 2 * Contains register definitions for the Freescale Embedded Performance 3 * Monitor. 4 */ 5 #ifdef __KERNEL__ 6 #ifndef __ASM_POWERPC_REG_FSL_EMB_H__ 7 #define __ASM_POWERPC_REG_FSL_EMB_H__ 8 9 #ifndef __ASSEMBLY__ 10 /* Performance Monitor Registers */ 11 #define mfpmr(rn) ({unsigned int rval; \ 12 asm volatile("mfpmr %0," __stringify(rn) \ 13 : "=r" (rval)); rval;}) 14 #define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v)) 15 #endif /* __ASSEMBLY__ */ 16 17 /* Freescale Book E Performance Monitor APU Registers */ 18 #define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */ 19 #define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */ 20 #define PMRN_PMC2 0x012 /* Performance Monitor Counter 2 */ 21 #define PMRN_PMC3 0x013 /* Performance Monitor Counter 3 */ 22 #define PMRN_PMC4 0x014 /* Performance Monitor Counter 4 */ 23 #define PMRN_PMC5 0x015 /* Performance Monitor Counter 5 */ 24 #define PMRN_PMLCA0 0x090 /* PM Local Control A0 */ 25 #define PMRN_PMLCA1 0x091 /* PM Local Control A1 */ 26 #define PMRN_PMLCA2 0x092 /* PM Local Control A2 */ 27 #define PMRN_PMLCA3 0x093 /* PM Local Control A3 */ 28 #define PMRN_PMLCA4 0x094 /* PM Local Control A4 */ 29 #define PMRN_PMLCA5 0x095 /* PM Local Control A5 */ 30 31 #define PMLCA_FC 0x80000000 /* Freeze Counter */ 32 #define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */ 33 #define PMLCA_FCU 0x20000000 /* Freeze in User */ 34 #define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */ 35 #define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */ 36 #define PMLCA_CE 0x04000000 /* Condition Enable */ 37 #define PMLCA_FGCS1 0x00000002 /* Freeze in guest state */ 38 #define PMLCA_FGCS0 0x00000001 /* Freeze in hypervisor state */ 39 40 #define PMLCA_EVENT_MASK 0x01ff0000 /* Event field */ 41 #define PMLCA_EVENT_SHIFT 16 42 43 #define PMRN_PMLCB0 0x110 /* PM Local Control B0 */ 44 #define PMRN_PMLCB1 0x111 /* PM Local Control B1 */ 45 #define PMRN_PMLCB2 0x112 /* PM Local Control B2 */ 46 #define PMRN_PMLCB3 0x113 /* PM Local Control B3 */ 47 #define PMRN_PMLCB4 0x114 /* PM Local Control B4 */ 48 #define PMRN_PMLCB5 0x115 /* PM Local Control B5 */ 49 50 #define PMLCB_THRESHMUL_MASK 0x0700 /* Threshold Multiple Field */ 51 #define PMLCB_THRESHMUL_SHIFT 8 52 53 #define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */ 54 #define PMLCB_THRESHOLD_SHIFT 0 55 56 #define PMRN_PMGC0 0x190 /* PM Global Control 0 */ 57 58 #define PMGC0_FAC 0x80000000 /* Freeze all Counters */ 59 #define PMGC0_PMIE 0x40000000 /* Interrupt Enable */ 60 #define PMGC0_FCECE 0x20000000 /* Freeze countes on 61 Enabled Condition or 62 Event */ 63 64 #define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */ 65 #define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */ 66 #define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 2 */ 67 #define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 3 */ 68 #define PMRN_UPMC4 0x004 /* User Performance Monitor Counter 4 */ 69 #define PMRN_UPMC5 0x005 /* User Performance Monitor Counter 5 */ 70 #define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */ 71 #define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */ 72 #define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */ 73 #define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */ 74 #define PMRN_UPMLCA4 0x084 /* User PM Local Control A4 */ 75 #define PMRN_UPMLCA5 0x085 /* User PM Local Control A5 */ 76 #define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */ 77 #define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */ 78 #define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */ 79 #define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */ 80 #define PMRN_UPMLCB4 0x104 /* User PM Local Control B4 */ 81 #define PMRN_UPMLCB5 0x105 /* User PM Local Control B5 */ 82 #define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */ 83 84 85 #endif /* __ASM_POWERPC_REG_FSL_EMB_H__ */ 86 #endif /* __KERNEL__ */ 87