1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Contains register definitions for the Freescale Embedded Performance
4  * Monitor.
5  */
6 #ifdef __KERNEL__
7 #ifndef __ASM_POWERPC_REG_FSL_EMB_H__
8 #define __ASM_POWERPC_REG_FSL_EMB_H__
9 
10 #ifndef __ASSEMBLY__
11 /* Performance Monitor Registers */
12 #define mfpmr(rn)	({unsigned int rval; \
13 			asm volatile("mfpmr %0," __stringify(rn) \
14 				     : "=r" (rval)); rval;})
15 #define mtpmr(rn, v)	asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v))
16 #endif /* __ASSEMBLY__ */
17 
18 /* Freescale Book E Performance Monitor APU Registers */
19 #define PMRN_PMC0	0x010	/* Performance Monitor Counter 0 */
20 #define PMRN_PMC1	0x011	/* Performance Monitor Counter 1 */
21 #define PMRN_PMC2	0x012	/* Performance Monitor Counter 2 */
22 #define PMRN_PMC3	0x013	/* Performance Monitor Counter 3 */
23 #define PMRN_PMC4	0x014	/* Performance Monitor Counter 4 */
24 #define PMRN_PMC5	0x015	/* Performance Monitor Counter 5 */
25 #define PMRN_PMLCA0	0x090	/* PM Local Control A0 */
26 #define PMRN_PMLCA1	0x091	/* PM Local Control A1 */
27 #define PMRN_PMLCA2	0x092	/* PM Local Control A2 */
28 #define PMRN_PMLCA3	0x093	/* PM Local Control A3 */
29 #define PMRN_PMLCA4	0x094	/* PM Local Control A4 */
30 #define PMRN_PMLCA5	0x095	/* PM Local Control A5 */
31 
32 #define PMLCA_FC	0x80000000	/* Freeze Counter */
33 #define PMLCA_FCS	0x40000000	/* Freeze in Supervisor */
34 #define PMLCA_FCU	0x20000000	/* Freeze in User */
35 #define PMLCA_FCM1	0x10000000	/* Freeze when PMM==1 */
36 #define PMLCA_FCM0	0x08000000	/* Freeze when PMM==0 */
37 #define PMLCA_CE	0x04000000	/* Condition Enable */
38 #define PMLCA_FGCS1	0x00000002	/* Freeze in guest state */
39 #define PMLCA_FGCS0	0x00000001	/* Freeze in hypervisor state */
40 
41 #define PMLCA_EVENT_MASK 0x01ff0000	/* Event field */
42 #define PMLCA_EVENT_SHIFT	16
43 
44 #define PMRN_PMLCB0	0x110	/* PM Local Control B0 */
45 #define PMRN_PMLCB1	0x111	/* PM Local Control B1 */
46 #define PMRN_PMLCB2	0x112	/* PM Local Control B2 */
47 #define PMRN_PMLCB3	0x113	/* PM Local Control B3 */
48 #define PMRN_PMLCB4	0x114	/* PM Local Control B4 */
49 #define PMRN_PMLCB5	0x115	/* PM Local Control B5 */
50 
51 #define PMLCB_THRESHMUL_MASK	0x0700	/* Threshold Multiple Field */
52 #define PMLCB_THRESHMUL_SHIFT	8
53 
54 #define PMLCB_THRESHOLD_MASK	0x003f	/* Threshold Field */
55 #define PMLCB_THRESHOLD_SHIFT	0
56 
57 #define PMRN_PMGC0	0x190	/* PM Global Control 0 */
58 
59 #define PMGC0_FAC	0x80000000	/* Freeze all Counters */
60 #define PMGC0_PMIE	0x40000000	/* Interrupt Enable */
61 #define PMGC0_FCECE	0x20000000	/* Freeze countes on
62 					   Enabled Condition or
63 					   Event */
64 
65 #define PMRN_UPMC0	0x000	/* User Performance Monitor Counter 0 */
66 #define PMRN_UPMC1	0x001	/* User Performance Monitor Counter 1 */
67 #define PMRN_UPMC2	0x002	/* User Performance Monitor Counter 2 */
68 #define PMRN_UPMC3	0x003	/* User Performance Monitor Counter 3 */
69 #define PMRN_UPMC4	0x004	/* User Performance Monitor Counter 4 */
70 #define PMRN_UPMC5	0x005	/* User Performance Monitor Counter 5 */
71 #define PMRN_UPMLCA0	0x080	/* User PM Local Control A0 */
72 #define PMRN_UPMLCA1	0x081	/* User PM Local Control A1 */
73 #define PMRN_UPMLCA2	0x082	/* User PM Local Control A2 */
74 #define PMRN_UPMLCA3	0x083	/* User PM Local Control A3 */
75 #define PMRN_UPMLCA4	0x084	/* User PM Local Control A4 */
76 #define PMRN_UPMLCA5	0x085	/* User PM Local Control A5 */
77 #define PMRN_UPMLCB0	0x100	/* User PM Local Control B0 */
78 #define PMRN_UPMLCB1	0x101	/* User PM Local Control B1 */
79 #define PMRN_UPMLCB2	0x102	/* User PM Local Control B2 */
80 #define PMRN_UPMLCB3	0x103	/* User PM Local Control B3 */
81 #define PMRN_UPMLCB4	0x104	/* User PM Local Control B4 */
82 #define PMRN_UPMLCB5	0x105	/* User PM Local Control B5 */
83 #define PMRN_UPMGC0	0x180	/* User PM Global Control 0 */
84 
85 
86 #endif /* __ASM_POWERPC_REG_FSL_EMB_H__ */
87 #endif /* __KERNEL__ */
88