1 /* 2 * Contains register definitions common to the Book E PowerPC 3 * specification. Notice that while the IBM-40x series of CPUs 4 * are not true Book E PowerPCs, they borrowed a number of features 5 * before Book E was finalized, and are included here as well. Unfortunatly, 6 * they sometimes used different locations than true Book E CPUs did. 7 */ 8 #ifdef __KERNEL__ 9 #ifndef __ASM_POWERPC_REG_BOOKE_H__ 10 #define __ASM_POWERPC_REG_BOOKE_H__ 11 12 /* Machine State Register (MSR) Fields */ 13 #define MSR_GS (1<<28) /* Guest state */ 14 #define MSR_UCLE (1<<26) /* User-mode cache lock enable */ 15 #define MSR_SPE (1<<25) /* Enable SPE */ 16 #define MSR_DWE (1<<10) /* Debug Wait Enable */ 17 #define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ 18 #define MSR_IS MSR_IR /* Instruction Space */ 19 #define MSR_DS MSR_DR /* Data Space */ 20 #define MSR_PMM (1<<2) /* Performance monitor mark bit */ 21 #define MSR_CM (1<<31) /* Computation Mode (0=32-bit, 1=64-bit) */ 22 23 #if defined(CONFIG_PPC_BOOK3E_64) 24 #define MSR_ MSR_ME | MSR_CE 25 #define MSR_KERNEL MSR_ | MSR_CM 26 #define MSR_USER32 MSR_ | MSR_PR | MSR_EE 27 #define MSR_USER64 MSR_USER32 | MSR_CM 28 #elif defined (CONFIG_40x) 29 #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE) 30 #define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE) 31 #else 32 #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE) 33 #define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE) 34 #endif 35 36 /* Special Purpose Registers (SPRNs)*/ 37 #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */ 38 #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */ 39 #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */ 40 #define SPRN_SPRG3R 0x103 /* Special Purpose Register General 3 Read */ 41 #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */ 42 #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */ 43 #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */ 44 #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */ 45 #define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */ 46 #define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */ 47 #define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */ 48 #define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */ 49 #define SPRN_EPCR 0x133 /* Embedded Processor Control Register */ 50 #define SPRN_DBCR2 0x136 /* Debug Control Register 2 */ 51 #define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */ 52 #define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */ 53 #define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */ 54 #define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */ 55 #define SPRN_MAS8 0x155 /* MMU Assist Register 8 */ 56 #define SPRN_TLB0PS 0x158 /* TLB 0 Page Size Register */ 57 #define SPRN_MAS5_MAS6 0x15c /* MMU Assist Register 5 || 6 */ 58 #define SPRN_MAS8_MAS1 0x15d /* MMU Assist Register 8 || 1 */ 59 #define SPRN_MAS7_MAS3 0x174 /* MMU Assist Register 7 || 3 */ 60 #define SPRN_MAS0_MAS1 0x175 /* MMU Assist Register 0 || 1 */ 61 #define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */ 62 #define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */ 63 #define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */ 64 #define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */ 65 #define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */ 66 #define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */ 67 #define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */ 68 #define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */ 69 #define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */ 70 #define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */ 71 #define SPRN_IVOR10 0x19A /* Interrupt Vector Offset Register 10 */ 72 #define SPRN_IVOR11 0x19B /* Interrupt Vector Offset Register 11 */ 73 #define SPRN_IVOR12 0x19C /* Interrupt Vector Offset Register 12 */ 74 #define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */ 75 #define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */ 76 #define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */ 77 #define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ 78 #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ 79 #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ 80 #define SPRN_L1CFG0 0x203 /* L1 Cache Configure Register 0 */ 81 #define SPRN_L1CFG1 0x204 /* L1 Cache Configure Register 1 */ 82 #define SPRN_ATB 0x20E /* Alternate Time Base */ 83 #define SPRN_ATBL 0x20E /* Alternate Time Base Lower */ 84 #define SPRN_ATBU 0x20F /* Alternate Time Base Upper */ 85 #define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ 86 #define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ 87 #define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ 88 #define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ 89 #define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */ 90 #define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */ 91 #define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */ 92 #define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */ 93 #define SPRN_MCSR 0x23C /* Machine Check Status Register */ 94 #define SPRN_MCAR 0x23D /* Machine Check Address Register */ 95 #define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */ 96 #define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */ 97 #define SPRN_SPRG8 0x25C /* Special Purpose Register General 8 */ 98 #define SPRN_SPRG9 0x25D /* Special Purpose Register General 9 */ 99 #define SPRN_L1CSR2 0x25E /* L1 Cache Control and Status Register 2 */ 100 #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ 101 #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ 102 #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ 103 #define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ 104 #define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ 105 #define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ 106 #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ 107 #define SPRN_PID1 0x279 /* Process ID Register 1 */ 108 #define SPRN_PID2 0x27A /* Process ID Register 2 */ 109 #define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ 110 #define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ 111 #define SPRN_TLB2CFG 0x2B2 /* TLB 2 Config Register */ 112 #define SPRN_TLB3CFG 0x2B3 /* TLB 3 Config Register */ 113 #define SPRN_EPR 0x2BE /* External Proxy Register */ 114 #define SPRN_CCR1 0x378 /* Core Configuration Register 1 */ 115 #define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */ 116 #define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */ 117 #define SPRN_MMUCR 0x3B2 /* MMU Control Register */ 118 #define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ 119 #define SPRN_EPLC 0x3B3 /* External Process ID Load Context */ 120 #define SPRN_EPSC 0x3B4 /* External Process ID Store Context */ 121 #define SPRN_SGR 0x3B9 /* Storage Guarded Register */ 122 #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ 123 #define SPRN_SLER 0x3BB /* Little-endian real mode */ 124 #define SPRN_SU0R 0x3BC /* "User 0" real mode (40x) */ 125 #define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ 126 #define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ 127 #define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ 128 #define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */ 129 #define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */ 130 #define SPRN_MMUCSR0 0x3F4 /* MMU Control and Status Register 0 */ 131 #define SPRN_MMUCFG 0x3F7 /* MMU Configuration Register */ 132 #define SPRN_PIT 0x3DB /* Programmable Interval Timer */ 133 #define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */ 134 #define SPRN_L2CSR0 0x3F9 /* L2 Data Cache Control and Status Register 0 */ 135 #define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */ 136 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ 137 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ 138 #define SPRN_SVR 0x3FF /* System Version Register */ 139 140 /* 141 * SPRs which have conflicting definitions on true Book E versus classic, 142 * or IBM 40x. 143 */ 144 #ifdef CONFIG_BOOKE 145 #define SPRN_PID 0x030 /* Process ID */ 146 #define SPRN_PID0 SPRN_PID/* Process ID Register 0 */ 147 #define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */ 148 #define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */ 149 #define SPRN_DEAR 0x03D /* Data Error Address Register */ 150 #define SPRN_ESR 0x03E /* Exception Syndrome Register */ 151 #define SPRN_PIR 0x11E /* Processor Identification Register */ 152 #define SPRN_DBSR 0x130 /* Debug Status Register */ 153 #define SPRN_DBCR0 0x134 /* Debug Control Register 0 */ 154 #define SPRN_DBCR1 0x135 /* Debug Control Register 1 */ 155 #define SPRN_IAC1 0x138 /* Instruction Address Compare 1 */ 156 #define SPRN_IAC2 0x139 /* Instruction Address Compare 2 */ 157 #define SPRN_DAC1 0x13C /* Data Address Compare 1 */ 158 #define SPRN_DAC2 0x13D /* Data Address Compare 2 */ 159 #define SPRN_TSR 0x150 /* Timer Status Register */ 160 #define SPRN_TCR 0x154 /* Timer Control Register */ 161 #endif /* Book E */ 162 #ifdef CONFIG_40x 163 #define SPRN_PID 0x3B1 /* Process ID */ 164 #define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ 165 #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ 166 #define SPRN_DEAR 0x3D5 /* Data Error Address Register */ 167 #define SPRN_TSR 0x3D8 /* Timer Status Register */ 168 #define SPRN_TCR 0x3DA /* Timer Control Register */ 169 #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ 170 #define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ 171 #define SPRN_DBSR 0x3F0 /* Debug Status Register */ 172 #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ 173 #define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ 174 #define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ 175 #define SPRN_CSRR0 SPRN_SRR2 /* Critical Save and Restore Register 0 */ 176 #define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */ 177 #endif 178 179 /* Bit definitions for CCR1. */ 180 #define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */ 181 #define CCR1_TCS 0x00000080 /* Timer Clock Select */ 182 183 /* Bit definitions for the MCSR. */ 184 #define MCSR_MCS 0x80000000 /* Machine Check Summary */ 185 #define MCSR_IB 0x40000000 /* Instruction PLB Error */ 186 #define MCSR_DRB 0x20000000 /* Data Read PLB Error */ 187 #define MCSR_DWB 0x10000000 /* Data Write PLB Error */ 188 #define MCSR_TLBP 0x08000000 /* TLB Parity Error */ 189 #define MCSR_ICP 0x04000000 /* I-Cache Parity Error */ 190 #define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */ 191 #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ 192 #define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ 193 194 #ifdef CONFIG_E500 195 #define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ 196 #define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */ 197 #define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */ 198 #define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */ 199 #define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */ 200 #define MCSR_BUS_RAERR 0x00000040UL /* Read Address Error */ 201 #define MCSR_BUS_WAERR 0x00000020UL /* Write Address Error */ 202 #define MCSR_BUS_IBERR 0x00000010UL /* Instruction Data Error */ 203 #define MCSR_BUS_RBERR 0x00000008UL /* Read Data Bus Error */ 204 #define MCSR_BUS_WBERR 0x00000004UL /* Write Data Bus Error */ 205 #define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */ 206 #define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */ 207 208 /* e500 parts may set unused bits in MCSR; mask these off */ 209 #define MCSR_MASK (MCSR_MCP | MCSR_ICPERR | MCSR_DCP_PERR | \ 210 MCSR_DCPERR | MCSR_BUS_IAERR | MCSR_BUS_RAERR | \ 211 MCSR_BUS_WAERR | MCSR_BUS_IBERR | MCSR_BUS_RBERR | \ 212 MCSR_BUS_WBERR | MCSR_BUS_IPERR | MCSR_BUS_RPERR) 213 #endif 214 #ifdef CONFIG_E200 215 #define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ 216 #define MCSR_CP_PERR 0x20000000UL /* Cache Push Parity Error */ 217 #define MCSR_CPERR 0x10000000UL /* Cache Parity Error */ 218 #define MCSR_EXCP_ERR 0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn 219 fetch for an exception handler */ 220 #define MCSR_BUS_IRERR 0x00000010UL /* Read Bus Error on instruction fetch*/ 221 #define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */ 222 #define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered 223 store or cache line push */ 224 225 /* e200 parts may set unused bits in MCSR; mask these off */ 226 #define MCSR_MASK (MCSR_MCP | MCSR_CP_PERR | MCSR_CPERR | \ 227 MCSR_EXCP_ERR | MCSR_BUS_IRERR | MCSR_BUS_DRERR | \ 228 MCSR_BUS_WRERR) 229 #endif 230 231 /* Bit definitions for the DBSR. */ 232 /* 233 * DBSR bits which have conflicting definitions on true Book E versus IBM 40x. 234 */ 235 #ifdef CONFIG_BOOKE 236 #define DBSR_IC 0x08000000 /* Instruction Completion */ 237 #define DBSR_BT 0x04000000 /* Branch Taken */ 238 #define DBSR_IRPT 0x02000000 /* Exception Debug Event */ 239 #define DBSR_TIE 0x01000000 /* Trap Instruction Event */ 240 #define DBSR_IAC1 0x00800000 /* Instr Address Compare 1 Event */ 241 #define DBSR_IAC2 0x00400000 /* Instr Address Compare 2 Event */ 242 #define DBSR_IAC3 0x00200000 /* Instr Address Compare 3 Event */ 243 #define DBSR_IAC4 0x00100000 /* Instr Address Compare 4 Event */ 244 #define DBSR_DAC1R 0x00080000 /* Data Addr Compare 1 Read Event */ 245 #define DBSR_DAC1W 0x00040000 /* Data Addr Compare 1 Write Event */ 246 #define DBSR_DAC2R 0x00020000 /* Data Addr Compare 2 Read Event */ 247 #define DBSR_DAC2W 0x00010000 /* Data Addr Compare 2 Write Event */ 248 #define DBSR_RET 0x00008000 /* Return Debug Event */ 249 #define DBSR_CIRPT 0x00000040 /* Critical Interrupt Taken Event */ 250 #define DBSR_CRET 0x00000020 /* Critical Return Debug Event */ 251 #endif 252 #ifdef CONFIG_40x 253 #define DBSR_IC 0x80000000 /* Instruction Completion */ 254 #define DBSR_BT 0x40000000 /* Branch taken */ 255 #define DBSR_IRPT 0x20000000 /* Exception Debug Event */ 256 #define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */ 257 #define DBSR_IAC1 0x04000000 /* Instruction Address Compare 1 Event */ 258 #define DBSR_IAC2 0x02000000 /* Instruction Address Compare 2 Event */ 259 #define DBSR_IAC3 0x00080000 /* Instruction Address Compare 3 Event */ 260 #define DBSR_IAC4 0x00040000 /* Instruction Address Compare 4 Event */ 261 #define DBSR_DAC1R 0x01000000 /* Data Address Compare 1 Read Event */ 262 #define DBSR_DAC1W 0x00800000 /* Data Address Compare 1 Write Event */ 263 #define DBSR_DAC2R 0x00400000 /* Data Address Compare 2 Read Event */ 264 #define DBSR_DAC2W 0x00200000 /* Data Address Compare 2 Write Event */ 265 #endif 266 267 /* Bit definitions related to the ESR. */ 268 #define ESR_MCI 0x80000000 /* Machine Check - Instruction */ 269 #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ 270 #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ 271 #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ 272 #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ 273 #define ESR_PIL 0x08000000 /* Program Exception - Illegal */ 274 #define ESR_PPR 0x04000000 /* Program Exception - Privileged */ 275 #define ESR_PTR 0x02000000 /* Program Exception - Trap */ 276 #define ESR_FP 0x01000000 /* Floating Point Operation */ 277 #define ESR_DST 0x00800000 /* Storage Exception - Data miss */ 278 #define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ 279 #define ESR_ST 0x00800000 /* Store Operation */ 280 #define ESR_DLK 0x00200000 /* Data Cache Locking */ 281 #define ESR_ILK 0x00100000 /* Instr. Cache Locking */ 282 #define ESR_PUO 0x00040000 /* Unimplemented Operation exception */ 283 #define ESR_BO 0x00020000 /* Byte Ordering */ 284 285 /* Bit definitions related to the DBCR0. */ 286 #if defined(CONFIG_40x) 287 #define DBCR0_EDM 0x80000000 /* External Debug Mode */ 288 #define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ 289 #define DBCR0_RST 0x30000000 /* all the bits in the RST field */ 290 #define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */ 291 #define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */ 292 #define DBCR0_RST_CORE 0x10000000 /* Core Reset */ 293 #define DBCR0_RST_NONE 0x00000000 /* No Reset */ 294 #define DBCR0_IC 0x08000000 /* Instruction Completion */ 295 #define DBCR0_ICMP DBCR0_IC 296 #define DBCR0_BT 0x04000000 /* Branch Taken */ 297 #define DBCR0_BRT DBCR0_BT 298 #define DBCR0_EDE 0x02000000 /* Exception Debug Event */ 299 #define DBCR0_IRPT DBCR0_EDE 300 #define DBCR0_TDE 0x01000000 /* TRAP Debug Event */ 301 #define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */ 302 #define DBCR0_IAC1 DBCR0_IA1 303 #define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */ 304 #define DBCR0_IAC2 DBCR0_IA2 305 #define DBCR0_IA12 0x00200000 /* Instr Addr 1-2 range enable */ 306 #define DBCR0_IA12X 0x00100000 /* Instr Addr 1-2 range eXclusive */ 307 #define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */ 308 #define DBCR0_IAC3 DBCR0_IA3 309 #define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */ 310 #define DBCR0_IAC4 DBCR0_IA4 311 #define DBCR0_IA34 0x00020000 /* Instr Addr 3-4 range Enable */ 312 #define DBCR0_IA34X 0x00010000 /* Instr Addr 3-4 range eXclusive */ 313 #define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */ 314 #define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */ 315 #define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ 316 #elif defined(CONFIG_BOOKE) 317 #define DBCR0_EDM 0x80000000 /* External Debug Mode */ 318 #define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ 319 #define DBCR0_RST 0x30000000 /* all the bits in the RST field */ 320 /* DBCR0_RST_* is 44x specific and not followed in fsl booke */ 321 #define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */ 322 #define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */ 323 #define DBCR0_RST_CORE 0x10000000 /* Core Reset */ 324 #define DBCR0_RST_NONE 0x00000000 /* No Reset */ 325 #define DBCR0_ICMP 0x08000000 /* Instruction Completion */ 326 #define DBCR0_IC DBCR0_ICMP 327 #define DBCR0_BRT 0x04000000 /* Branch Taken */ 328 #define DBCR0_BT DBCR0_BRT 329 #define DBCR0_IRPT 0x02000000 /* Exception Debug Event */ 330 #define DBCR0_TDE 0x01000000 /* TRAP Debug Event */ 331 #define DBCR0_TIE DBCR0_TDE 332 #define DBCR0_IAC1 0x00800000 /* Instr Addr compare 1 enable */ 333 #define DBCR0_IAC2 0x00400000 /* Instr Addr compare 2 enable */ 334 #define DBCR0_IAC3 0x00200000 /* Instr Addr compare 3 enable */ 335 #define DBCR0_IAC4 0x00100000 /* Instr Addr compare 4 enable */ 336 #define DBCR0_DAC1R 0x00080000 /* DAC 1 Read enable */ 337 #define DBCR0_DAC1W 0x00040000 /* DAC 1 Write enable */ 338 #define DBCR0_DAC2R 0x00020000 /* DAC 2 Read enable */ 339 #define DBCR0_DAC2W 0x00010000 /* DAC 2 Write enable */ 340 #define DBCR0_RET 0x00008000 /* Return Debug Event */ 341 #define DBCR0_CIRPT 0x00000040 /* Critical Interrupt Taken Event */ 342 #define DBCR0_CRET 0x00000020 /* Critical Return Debug Event */ 343 #define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ 344 345 /* Bit definitions related to the DBCR1. */ 346 #define DBCR1_IAC12M 0x00800000 /* Instr Addr 1-2 range enable */ 347 #define DBCR1_IAC12MX 0x00C00000 /* Instr Addr 1-2 range eXclusive */ 348 #define DBCR1_IAC12AT 0x00010000 /* Instr Addr 1-2 range Toggle */ 349 #define DBCR1_IAC34M 0x00000080 /* Instr Addr 3-4 range enable */ 350 #define DBCR1_IAC34MX 0x000000C0 /* Instr Addr 3-4 range eXclusive */ 351 #define DBCR1_IAC34AT 0x00000001 /* Instr Addr 3-4 range Toggle */ 352 353 /* Bit definitions related to the DBCR2. */ 354 #define DBCR2_DAC12M 0x00800000 /* DAC 1-2 range enable */ 355 #define DBCR2_DAC12MX 0x00C00000 /* DAC 1-2 range eXclusive */ 356 #define DBCR2_DAC12A 0x00200000 /* DAC 1-2 Asynchronous */ 357 #endif 358 359 /* Bit definitions related to the TCR. */ 360 #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ 361 #define TCR_WP_MASK TCR_WP(3) 362 #define WP_2_17 0 /* 2^17 clocks */ 363 #define WP_2_21 1 /* 2^21 clocks */ 364 #define WP_2_25 2 /* 2^25 clocks */ 365 #define WP_2_29 3 /* 2^29 clocks */ 366 #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ 367 #define TCR_WRC_MASK TCR_WRC(3) 368 #define WRC_NONE 0 /* No reset will occur */ 369 #define WRC_CORE 1 /* Core reset will occur */ 370 #define WRC_CHIP 2 /* Chip reset will occur */ 371 #define WRC_SYSTEM 3 /* System reset will occur */ 372 #define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ 373 #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ 374 #define TCR_DIE TCR_PIE /* DEC Interrupt Enable */ 375 #define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ 376 #define TCR_FP_MASK TCR_FP(3) 377 #define FP_2_9 0 /* 2^9 clocks */ 378 #define FP_2_13 1 /* 2^13 clocks */ 379 #define FP_2_17 2 /* 2^17 clocks */ 380 #define FP_2_21 3 /* 2^21 clocks */ 381 #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ 382 #define TCR_ARE 0x00400000 /* Auto Reload Enable */ 383 384 /* Bit definitions for the TSR. */ 385 #define TSR_ENW 0x80000000 /* Enable Next Watchdog */ 386 #define TSR_WIS 0x40000000 /* WDT Interrupt Status */ 387 #define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */ 388 #define WRS_NONE 0 /* No WDT reset occurred */ 389 #define WRS_CORE 1 /* WDT forced core reset */ 390 #define WRS_CHIP 2 /* WDT forced chip reset */ 391 #define WRS_SYSTEM 3 /* WDT forced system reset */ 392 #define TSR_PIS 0x08000000 /* PIT Interrupt Status */ 393 #define TSR_DIS TSR_PIS /* DEC Interrupt Status */ 394 #define TSR_FIS 0x04000000 /* FIT Interrupt Status */ 395 396 /* Bit definitions for the DCCR. */ 397 #define DCCR_NOCACHE 0 /* Noncacheable */ 398 #define DCCR_CACHE 1 /* Cacheable */ 399 400 /* Bit definitions for DCWR. */ 401 #define DCWR_COPY 0 /* Copy-back */ 402 #define DCWR_WRITE 1 /* Write-through */ 403 404 /* Bit definitions for ICCR. */ 405 #define ICCR_NOCACHE 0 /* Noncacheable */ 406 #define ICCR_CACHE 1 /* Cacheable */ 407 408 /* Bit definitions for L1CSR0. */ 409 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ 410 #define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */ 411 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ 412 #define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */ 413 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ 414 415 /* Bit definitions for L1CSR1. */ 416 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ 417 #define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */ 418 #define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */ 419 #define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ 420 421 /* Bit definitions for L2CSR0. */ 422 #define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ 423 #define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */ 424 #define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */ 425 #define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */ 426 #define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */ 427 #define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */ 428 #define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */ 429 #define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */ 430 #define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */ 431 #define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */ 432 #define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */ 433 #define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */ 434 435 /* Bit definitions for SGR. */ 436 #define SGR_NORMAL 0 /* Speculative fetching allowed. */ 437 #define SGR_GUARDED 1 /* Speculative fetching disallowed. */ 438 439 /* Bit definitions for EPCR */ 440 #define SPRN_EPCR_EXTGS 0x80000000 /* External Input interrupt 441 * directed to Guest state */ 442 #define SPRN_EPCR_DTLBGS 0x40000000 /* Data TLB Error interrupt 443 * directed to guest state */ 444 #define SPRN_EPCR_ITLBGS 0x20000000 /* Instr. TLB error interrupt 445 * directed to guest state */ 446 #define SPRN_EPCR_DSIGS 0x10000000 /* Data Storage interrupt 447 * directed to guest state */ 448 #define SPRN_EPCR_ISIGS 0x08000000 /* Instr. Storage interrupt 449 * directed to guest state */ 450 #define SPRN_EPCR_DUVD 0x04000000 /* Disable Hypervisor Debug */ 451 #define SPRN_EPCR_ICM 0x02000000 /* Interrupt computation mode 452 * (copied to MSR:CM on intr) */ 453 #define SPRN_EPCR_GICM 0x01000000 /* Guest Interrupt Comp. mode */ 454 #define SPRN_EPCR_DGTMI 0x00800000 /* Disable TLB Guest Management 455 * instructions */ 456 #define SPRN_EPCR_DMIUH 0x00400000 /* Disable MAS Interrupt updates 457 * for hypervisor */ 458 459 460 /* 461 * The IBM-403 is an even more odd special case, as it is much 462 * older than the IBM-405 series. We put these down here incase someone 463 * wishes to support these machines again. 464 */ 465 #ifdef CONFIG_403GCX 466 /* Special Purpose Registers (SPRNs)*/ 467 #define SPRN_TBHU 0x3CC /* Time Base High User-mode */ 468 #define SPRN_TBLU 0x3CD /* Time Base Low User-mode */ 469 #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ 470 #define SPRN_TBHI 0x3DC /* Time Base High */ 471 #define SPRN_TBLO 0x3DD /* Time Base Low */ 472 #define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ 473 #define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ 474 #define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ 475 #define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ 476 #define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */ 477 478 479 /* Bit definitions for the DBCR. */ 480 #define DBCR_EDM DBCR0_EDM 481 #define DBCR_IDM DBCR0_IDM 482 #define DBCR_RST(x) (((x) & 0x3) << 28) 483 #define DBCR_RST_NONE 0 484 #define DBCR_RST_CORE 1 485 #define DBCR_RST_CHIP 2 486 #define DBCR_RST_SYSTEM 3 487 #define DBCR_IC DBCR0_IC /* Instruction Completion Debug Evnt */ 488 #define DBCR_BT DBCR0_BT /* Branch Taken Debug Event */ 489 #define DBCR_EDE DBCR0_EDE /* Exception Debug Event */ 490 #define DBCR_TDE DBCR0_TDE /* TRAP Debug Event */ 491 #define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ 492 #define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ 493 #define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ 494 #define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ 495 #define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ 496 #define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ 497 #define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ 498 #define DAC_BYTE 0 499 #define DAC_HALF 1 500 #define DAC_WORD 2 501 #define DAC_QUAD 3 502 #define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ 503 #define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ 504 #define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ 505 #define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ 506 #define DBCR_SED 0x00000020 /* Second Exception Debug Event */ 507 #define DBCR_STD 0x00000010 /* Second Trap Debug Event */ 508 #define DBCR_SIA 0x00000008 /* Second IAC Enable */ 509 #define DBCR_SDA 0x00000004 /* Second DAC Enable */ 510 #define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ 511 #define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ 512 #endif /* 403GCX */ 513 #endif /* __ASM_POWERPC_REG_BOOKE_H__ */ 514 #endif /* __KERNEL__ */ 515