xref: /openbmc/linux/arch/powerpc/include/asm/reg.h (revision 98ddec80)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Contains the definition of registers common to all PowerPC variants.
4  * If a register definition has been changed in a different PowerPC
5  * variant, we will case it in #ifndef XXX ... #endif, and have the
6  * number used in the Programming Environments Manual For 32-Bit
7  * Implementations of the PowerPC Architecture (a.k.a. Green Book) here.
8  */
9 
10 #ifndef _ASM_POWERPC_REG_H
11 #define _ASM_POWERPC_REG_H
12 #ifdef __KERNEL__
13 
14 #include <linux/stringify.h>
15 #include <asm/cputable.h>
16 
17 /* Pickup Book E specific registers. */
18 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
19 #include <asm/reg_booke.h>
20 #endif /* CONFIG_BOOKE || CONFIG_40x */
21 
22 #ifdef CONFIG_FSL_EMB_PERFMON
23 #include <asm/reg_fsl_emb.h>
24 #endif
25 
26 #ifdef CONFIG_PPC_8xx
27 #include <asm/reg_8xx.h>
28 #endif /* CONFIG_PPC_8xx */
29 
30 #define MSR_SF_LG	63              /* Enable 64 bit mode */
31 #define MSR_ISF_LG	61              /* Interrupt 64b mode valid on 630 */
32 #define MSR_HV_LG 	60              /* Hypervisor state */
33 #define MSR_TS_T_LG	34		/* Trans Mem state: Transactional */
34 #define MSR_TS_S_LG	33		/* Trans Mem state: Suspended */
35 #define MSR_TS_LG	33		/* Trans Mem state (2 bits) */
36 #define MSR_TM_LG	32		/* Trans Mem Available */
37 #define MSR_VEC_LG	25	        /* Enable AltiVec */
38 #define MSR_VSX_LG	23		/* Enable VSX */
39 #define MSR_POW_LG	18		/* Enable Power Management */
40 #define MSR_WE_LG	18		/* Wait State Enable */
41 #define MSR_TGPR_LG	17		/* TLB Update registers in use */
42 #define MSR_CE_LG	17		/* Critical Interrupt Enable */
43 #define MSR_ILE_LG	16		/* Interrupt Little Endian */
44 #define MSR_EE_LG	15		/* External Interrupt Enable */
45 #define MSR_PR_LG	14		/* Problem State / Privilege Level */
46 #define MSR_FP_LG	13		/* Floating Point enable */
47 #define MSR_ME_LG	12		/* Machine Check Enable */
48 #define MSR_FE0_LG	11		/* Floating Exception mode 0 */
49 #define MSR_SE_LG	10		/* Single Step */
50 #define MSR_BE_LG	9		/* Branch Trace */
51 #define MSR_DE_LG	9 		/* Debug Exception Enable */
52 #define MSR_FE1_LG	8		/* Floating Exception mode 1 */
53 #define MSR_IP_LG	6		/* Exception prefix 0x000/0xFFF */
54 #define MSR_IR_LG	5 		/* Instruction Relocate */
55 #define MSR_DR_LG	4 		/* Data Relocate */
56 #define MSR_PE_LG	3		/* Protection Enable */
57 #define MSR_PX_LG	2		/* Protection Exclusive Mode */
58 #define MSR_PMM_LG	2		/* Performance monitor */
59 #define MSR_RI_LG	1		/* Recoverable Exception */
60 #define MSR_LE_LG	0 		/* Little Endian */
61 
62 #ifdef __ASSEMBLY__
63 #define __MASK(X)	(1<<(X))
64 #else
65 #define __MASK(X)	(1UL<<(X))
66 #endif
67 
68 #ifdef CONFIG_PPC64
69 #define MSR_SF		__MASK(MSR_SF_LG)	/* Enable 64 bit mode */
70 #define MSR_ISF		__MASK(MSR_ISF_LG)	/* Interrupt 64b mode valid on 630 */
71 #define MSR_HV 		__MASK(MSR_HV_LG)	/* Hypervisor state */
72 #else
73 /* so tests for these bits fail on 32-bit */
74 #define MSR_SF		0
75 #define MSR_ISF		0
76 #define MSR_HV		0
77 #endif
78 
79 /*
80  * To be used in shared book E/book S, this avoids needing to worry about
81  * book S/book E in shared code
82  */
83 #ifndef MSR_SPE
84 #define MSR_SPE 	0
85 #endif
86 
87 #define MSR_VEC		__MASK(MSR_VEC_LG)	/* Enable AltiVec */
88 #define MSR_VSX		__MASK(MSR_VSX_LG)	/* Enable VSX */
89 #define MSR_POW		__MASK(MSR_POW_LG)	/* Enable Power Management */
90 #define MSR_WE		__MASK(MSR_WE_LG)	/* Wait State Enable */
91 #define MSR_TGPR	__MASK(MSR_TGPR_LG)	/* TLB Update registers in use */
92 #define MSR_CE		__MASK(MSR_CE_LG)	/* Critical Interrupt Enable */
93 #define MSR_ILE		__MASK(MSR_ILE_LG)	/* Interrupt Little Endian */
94 #define MSR_EE		__MASK(MSR_EE_LG)	/* External Interrupt Enable */
95 #define MSR_PR		__MASK(MSR_PR_LG)	/* Problem State / Privilege Level */
96 #define MSR_FP		__MASK(MSR_FP_LG)	/* Floating Point enable */
97 #define MSR_ME		__MASK(MSR_ME_LG)	/* Machine Check Enable */
98 #define MSR_FE0		__MASK(MSR_FE0_LG)	/* Floating Exception mode 0 */
99 #define MSR_SE		__MASK(MSR_SE_LG)	/* Single Step */
100 #define MSR_BE		__MASK(MSR_BE_LG)	/* Branch Trace */
101 #define MSR_DE		__MASK(MSR_DE_LG)	/* Debug Exception Enable */
102 #define MSR_FE1		__MASK(MSR_FE1_LG)	/* Floating Exception mode 1 */
103 #define MSR_IP		__MASK(MSR_IP_LG)	/* Exception prefix 0x000/0xFFF */
104 #define MSR_IR		__MASK(MSR_IR_LG)	/* Instruction Relocate */
105 #define MSR_DR		__MASK(MSR_DR_LG)	/* Data Relocate */
106 #define MSR_PE		__MASK(MSR_PE_LG)	/* Protection Enable */
107 #define MSR_PX		__MASK(MSR_PX_LG)	/* Protection Exclusive Mode */
108 #ifndef MSR_PMM
109 #define MSR_PMM		__MASK(MSR_PMM_LG)	/* Performance monitor */
110 #endif
111 #define MSR_RI		__MASK(MSR_RI_LG)	/* Recoverable Exception */
112 #define MSR_LE		__MASK(MSR_LE_LG)	/* Little Endian */
113 
114 #define MSR_TM		__MASK(MSR_TM_LG)	/* Transactional Mem Available */
115 #define MSR_TS_N	0			/*  Non-transactional */
116 #define MSR_TS_S	__MASK(MSR_TS_S_LG)	/*  Transaction Suspended */
117 #define MSR_TS_T	__MASK(MSR_TS_T_LG)	/*  Transaction Transactional */
118 #define MSR_TS_MASK	(MSR_TS_T | MSR_TS_S)   /* Transaction State bits */
119 #define MSR_TM_ACTIVE(x) (((x) & MSR_TS_MASK) != 0) /* Transaction active? */
120 #define MSR_TM_RESV(x) (((x) & MSR_TS_MASK) == MSR_TS_MASK) /* Reserved */
121 #define MSR_TM_TRANSACTIONAL(x)	(((x) & MSR_TS_MASK) == MSR_TS_T)
122 #define MSR_TM_SUSPENDED(x)	(((x) & MSR_TS_MASK) == MSR_TS_S)
123 
124 #if defined(CONFIG_PPC_BOOK3S_64)
125 #define MSR_64BIT	MSR_SF
126 
127 /* Server variant */
128 #define __MSR		(MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV)
129 #ifdef __BIG_ENDIAN__
130 #define MSR_		__MSR
131 #define MSR_IDLE	(MSR_ME | MSR_SF | MSR_HV)
132 #else
133 #define MSR_		(__MSR | MSR_LE)
134 #define MSR_IDLE	(MSR_ME | MSR_SF | MSR_HV | MSR_LE)
135 #endif
136 #define MSR_KERNEL	(MSR_ | MSR_64BIT)
137 #define MSR_USER32	(MSR_ | MSR_PR | MSR_EE)
138 #define MSR_USER64	(MSR_USER32 | MSR_64BIT)
139 #elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_PPC_8xx)
140 /* Default MSR for kernel mode. */
141 #define MSR_KERNEL	(MSR_ME|MSR_RI|MSR_IR|MSR_DR)
142 #define MSR_USER	(MSR_KERNEL|MSR_PR|MSR_EE)
143 #endif
144 
145 #ifndef MSR_64BIT
146 #define MSR_64BIT	0
147 #endif
148 
149 /* Condition Register related */
150 #define CR0_SHIFT	28
151 #define CR0_MASK	0xF
152 #define CR0_TBEGIN_FAILURE	(0x2 << 28) /* 0b0010 */
153 
154 
155 /* Power Management - Processor Stop Status and Control Register Fields */
156 #define PSSCR_RL_MASK		0x0000000F /* Requested Level */
157 #define PSSCR_MTL_MASK		0x000000F0 /* Maximum Transition Level */
158 #define PSSCR_TR_MASK		0x00000300 /* Transition State */
159 #define PSSCR_PSLL_MASK		0x000F0000 /* Power-Saving Level Limit */
160 #define PSSCR_EC		0x00100000 /* Exit Criterion */
161 #define PSSCR_ESL		0x00200000 /* Enable State Loss */
162 #define PSSCR_SD		0x00400000 /* Status Disable */
163 #define PSSCR_PLS	0xf000000000000000 /* Power-saving Level Status */
164 #define PSSCR_GUEST_VIS	0xf0000000000003ff /* Guest-visible PSSCR fields */
165 #define PSSCR_FAKE_SUSPEND	0x00000400 /* Fake-suspend bit (P9 DD2.2) */
166 #define PSSCR_FAKE_SUSPEND_LG	10	   /* Fake-suspend bit position */
167 
168 /* Floating Point Status and Control Register (FPSCR) Fields */
169 #define FPSCR_FX	0x80000000	/* FPU exception summary */
170 #define FPSCR_FEX	0x40000000	/* FPU enabled exception summary */
171 #define FPSCR_VX	0x20000000	/* Invalid operation summary */
172 #define FPSCR_OX	0x10000000	/* Overflow exception summary */
173 #define FPSCR_UX	0x08000000	/* Underflow exception summary */
174 #define FPSCR_ZX	0x04000000	/* Zero-divide exception summary */
175 #define FPSCR_XX	0x02000000	/* Inexact exception summary */
176 #define FPSCR_VXSNAN	0x01000000	/* Invalid op for SNaN */
177 #define FPSCR_VXISI	0x00800000	/* Invalid op for Inv - Inv */
178 #define FPSCR_VXIDI	0x00400000	/* Invalid op for Inv / Inv */
179 #define FPSCR_VXZDZ	0x00200000	/* Invalid op for Zero / Zero */
180 #define FPSCR_VXIMZ	0x00100000	/* Invalid op for Inv * Zero */
181 #define FPSCR_VXVC	0x00080000	/* Invalid op for Compare */
182 #define FPSCR_FR	0x00040000	/* Fraction rounded */
183 #define FPSCR_FI	0x00020000	/* Fraction inexact */
184 #define FPSCR_FPRF	0x0001f000	/* FPU Result Flags */
185 #define FPSCR_FPCC	0x0000f000	/* FPU Condition Codes */
186 #define FPSCR_VXSOFT	0x00000400	/* Invalid op for software request */
187 #define FPSCR_VXSQRT	0x00000200	/* Invalid op for square root */
188 #define FPSCR_VXCVI	0x00000100	/* Invalid op for integer convert */
189 #define FPSCR_VE	0x00000080	/* Invalid op exception enable */
190 #define FPSCR_OE	0x00000040	/* IEEE overflow exception enable */
191 #define FPSCR_UE	0x00000020	/* IEEE underflow exception enable */
192 #define FPSCR_ZE	0x00000010	/* IEEE zero divide exception enable */
193 #define FPSCR_XE	0x00000008	/* FP inexact exception enable */
194 #define FPSCR_NI	0x00000004	/* FPU non IEEE-Mode */
195 #define FPSCR_RN	0x00000003	/* FPU rounding control */
196 
197 /* Bit definitions for SPEFSCR. */
198 #define SPEFSCR_SOVH	0x80000000	/* Summary integer overflow high */
199 #define SPEFSCR_OVH	0x40000000	/* Integer overflow high */
200 #define SPEFSCR_FGH	0x20000000	/* Embedded FP guard bit high */
201 #define SPEFSCR_FXH	0x10000000	/* Embedded FP sticky bit high */
202 #define SPEFSCR_FINVH	0x08000000	/* Embedded FP invalid operation high */
203 #define SPEFSCR_FDBZH	0x04000000	/* Embedded FP div by zero high */
204 #define SPEFSCR_FUNFH	0x02000000	/* Embedded FP underflow high */
205 #define SPEFSCR_FOVFH	0x01000000	/* Embedded FP overflow high */
206 #define SPEFSCR_FINXS	0x00200000	/* Embedded FP inexact sticky */
207 #define SPEFSCR_FINVS	0x00100000	/* Embedded FP invalid op. sticky */
208 #define SPEFSCR_FDBZS	0x00080000	/* Embedded FP div by zero sticky */
209 #define SPEFSCR_FUNFS	0x00040000	/* Embedded FP underflow sticky */
210 #define SPEFSCR_FOVFS	0x00020000	/* Embedded FP overflow sticky */
211 #define SPEFSCR_MODE	0x00010000	/* Embedded FP mode */
212 #define SPEFSCR_SOV	0x00008000	/* Integer summary overflow */
213 #define SPEFSCR_OV	0x00004000	/* Integer overflow */
214 #define SPEFSCR_FG	0x00002000	/* Embedded FP guard bit */
215 #define SPEFSCR_FX	0x00001000	/* Embedded FP sticky bit */
216 #define SPEFSCR_FINV	0x00000800	/* Embedded FP invalid operation */
217 #define SPEFSCR_FDBZ	0x00000400	/* Embedded FP div by zero */
218 #define SPEFSCR_FUNF	0x00000200	/* Embedded FP underflow */
219 #define SPEFSCR_FOVF	0x00000100	/* Embedded FP overflow */
220 #define SPEFSCR_FINXE	0x00000040	/* Embedded FP inexact enable */
221 #define SPEFSCR_FINVE	0x00000020	/* Embedded FP invalid op. enable */
222 #define SPEFSCR_FDBZE	0x00000010	/* Embedded FP div by zero enable */
223 #define SPEFSCR_FUNFE	0x00000008	/* Embedded FP underflow enable */
224 #define SPEFSCR_FOVFE	0x00000004	/* Embedded FP overflow enable */
225 #define SPEFSCR_FRMC 	0x00000003	/* Embedded FP rounding mode control */
226 
227 /* Special Purpose Registers (SPRNs)*/
228 
229 #ifdef CONFIG_40x
230 #define SPRN_PID	0x3B1	/* Process ID */
231 #else
232 #define SPRN_PID	0x030	/* Process ID */
233 #ifdef CONFIG_BOOKE
234 #define SPRN_PID0	SPRN_PID/* Process ID Register 0 */
235 #endif
236 #endif
237 
238 #define SPRN_CTR	0x009	/* Count Register */
239 #define SPRN_DSCR	0x11
240 #define SPRN_CFAR	0x1c	/* Come From Address Register */
241 #define SPRN_AMR	0x1d	/* Authority Mask Register */
242 #define SPRN_UAMOR	0x9d	/* User Authority Mask Override Register */
243 #define SPRN_AMOR	0x15d	/* Authority Mask Override Register */
244 #define SPRN_ACOP	0x1F	/* Available Coprocessor Register */
245 #define SPRN_TFIAR	0x81	/* Transaction Failure Inst Addr   */
246 #define SPRN_TEXASR	0x82	/* Transaction EXception & Summary */
247 #define SPRN_TEXASRU	0x83	/* ''	   ''	   ''	 Upper 32  */
248 
249 #define TEXASR_FC_LG	(63 - 7)	/* Failure Code */
250 #define TEXASR_AB_LG	(63 - 31)	/* Abort */
251 #define TEXASR_SU_LG	(63 - 32)	/* Suspend */
252 #define TEXASR_HV_LG	(63 - 34)	/* Hypervisor state*/
253 #define TEXASR_PR_LG	(63 - 35)	/* Privilege level */
254 #define TEXASR_FS_LG	(63 - 36)	/* failure summary */
255 #define TEXASR_EX_LG	(63 - 37)	/* TFIAR exact bit */
256 #define TEXASR_ROT_LG	(63 - 38)	/* ROT bit */
257 
258 #define   TEXASR_ABORT	__MASK(TEXASR_AB_LG) /* terminated by tabort or treclaim */
259 #define   TEXASR_SUSP	__MASK(TEXASR_SU_LG) /* tx failed in suspended state */
260 #define   TEXASR_HV	__MASK(TEXASR_HV_LG) /* MSR[HV] when failure occurred */
261 #define   TEXASR_PR	__MASK(TEXASR_PR_LG) /* MSR[PR] when failure occurred */
262 #define   TEXASR_FS	__MASK(TEXASR_FS_LG) /* TEXASR Failure Summary */
263 #define   TEXASR_EXACT	__MASK(TEXASR_EX_LG) /* TFIAR value is exact */
264 #define   TEXASR_ROT	__MASK(TEXASR_ROT_LG)
265 #define   TEXASR_FC	(ASM_CONST(0xFF) << TEXASR_FC_LG)
266 
267 #define SPRN_TFHAR	0x80	/* Transaction Failure Handler Addr */
268 
269 #define SPRN_TIDR	144	/* Thread ID register */
270 #define SPRN_CTRLF	0x088
271 #define SPRN_CTRLT	0x098
272 #define   CTRL_CT	0xc0000000	/* current thread */
273 #define   CTRL_CT0	0x80000000	/* thread 0 */
274 #define   CTRL_CT1	0x40000000	/* thread 1 */
275 #define   CTRL_TE	0x00c00000	/* thread enable */
276 #define   CTRL_RUNLATCH	0x1
277 #define SPRN_DAWR	0xB4
278 #define SPRN_RPR	0xBA	/* Relative Priority Register */
279 #define SPRN_CIABR	0xBB
280 #define   CIABR_PRIV		0x3
281 #define   CIABR_PRIV_USER	1
282 #define   CIABR_PRIV_SUPER	2
283 #define   CIABR_PRIV_HYPER	3
284 #define SPRN_DAWRX	0xBC
285 #define   DAWRX_USER	__MASK(0)
286 #define   DAWRX_KERNEL	__MASK(1)
287 #define   DAWRX_HYP	__MASK(2)
288 #define   DAWRX_WTI	__MASK(3)
289 #define   DAWRX_WT	__MASK(4)
290 #define   DAWRX_DR	__MASK(5)
291 #define   DAWRX_DW	__MASK(6)
292 #define SPRN_DABR	0x3F5	/* Data Address Breakpoint Register */
293 #define SPRN_DABR2	0x13D	/* e300 */
294 #define SPRN_DABRX	0x3F7	/* Data Address Breakpoint Register Extension */
295 #define   DABRX_USER	__MASK(0)
296 #define   DABRX_KERNEL	__MASK(1)
297 #define   DABRX_HYP	__MASK(2)
298 #define   DABRX_BTI	__MASK(3)
299 #define   DABRX_ALL     (DABRX_BTI | DABRX_HYP | DABRX_KERNEL | DABRX_USER)
300 #define SPRN_DAR	0x013	/* Data Address Register */
301 #define SPRN_DBCR	0x136	/* e300 Data Breakpoint Control Reg */
302 #define SPRN_DSISR	0x012	/* Data Storage Interrupt Status Register */
303 #define   DSISR_BAD_DIRECT_ST	0x80000000 /* Obsolete: Direct store error */
304 #define   DSISR_NOHPTE		0x40000000 /* no translation found */
305 #define   DSISR_ATTR_CONFLICT	0x20000000 /* P9: Process vs. Partition attr */
306 #define   DSISR_NOEXEC_OR_G	0x10000000 /* Alias of SRR1 bit, see below */
307 #define   DSISR_PROTFAULT	0x08000000 /* protection fault */
308 #define   DSISR_BADACCESS	0x04000000 /* bad access to CI or G */
309 #define   DSISR_ISSTORE		0x02000000 /* access was a store */
310 #define   DSISR_DABRMATCH	0x00400000 /* hit data breakpoint */
311 #define   DSISR_NOSEGMENT	0x00200000 /* STAB miss (unsupported) */
312 #define   DSISR_KEYFAULT	0x00200000 /* Storage Key fault */
313 #define   DSISR_BAD_EXT_CTRL	0x00100000 /* Obsolete: External ctrl error */
314 #define   DSISR_UNSUPP_MMU	0x00080000 /* P9: Unsupported MMU config */
315 #define   DSISR_SET_RC		0x00040000 /* P9: Failed setting of R/C bits */
316 #define   DSISR_PRTABLE_FAULT   0x00020000 /* P9: Fault on process table */
317 #define   DSISR_ICSWX_NO_CT     0x00004000 /* P7: icswx unavailable cp type */
318 #define   DSISR_BAD_COPYPASTE   0x00000008 /* P9: Copy/Paste on wrong memtype */
319 #define   DSISR_BAD_AMO		0x00000004 /* P9: Incorrect AMO opcode */
320 #define   DSISR_BAD_CI_LDST	0x00000002 /* P8: Bad HV CI load/store */
321 
322 /*
323  * DSISR_NOEXEC_OR_G doesn't actually exist. This bit is always
324  * 0 on DSIs. However, on ISIs, the corresponding bit in SRR1
325  * indicates an attempt at executing from a no-execute PTE
326  * or segment or from a guarded page.
327  *
328  * We add a definition here for completeness as we alias
329  * DSISR and SRR1 in do_page_fault.
330  */
331 
332 /*
333  * DSISR bits that are treated as a fault. Any bit set
334  * here will skip hash_page, and cause do_page_fault to
335  * trigger a SIGBUS or SIGSEGV:
336  */
337 #define   DSISR_BAD_FAULT_32S	(DSISR_BAD_DIRECT_ST	| \
338 				 DSISR_BADACCESS	| \
339 				 DSISR_BAD_EXT_CTRL)
340 #define	  DSISR_BAD_FAULT_64S	(DSISR_BAD_FAULT_32S	| \
341 				 DSISR_ATTR_CONFLICT	| \
342 				 DSISR_UNSUPP_MMU	| \
343 				 DSISR_PRTABLE_FAULT	| \
344 				 DSISR_ICSWX_NO_CT	| \
345 				 DSISR_BAD_COPYPASTE	| \
346 				 DSISR_BAD_AMO		| \
347 				 DSISR_BAD_CI_LDST)
348 /*
349  * These bits are equivalent in SRR1 and DSISR for 0x400
350  * instruction access interrupts on Book3S
351  */
352 #define   DSISR_SRR1_MATCH_32S	(DSISR_NOHPTE		| \
353 				 DSISR_NOEXEC_OR_G	| \
354 				 DSISR_PROTFAULT)
355 #define   DSISR_SRR1_MATCH_64S	(DSISR_SRR1_MATCH_32S	| \
356 				 DSISR_KEYFAULT		| \
357 				 DSISR_UNSUPP_MMU	| \
358 				 DSISR_SET_RC		| \
359 				 DSISR_PRTABLE_FAULT)
360 
361 #define SPRN_TBRL	0x10C	/* Time Base Read Lower Register (user, R/O) */
362 #define SPRN_TBRU	0x10D	/* Time Base Read Upper Register (user, R/O) */
363 #define SPRN_CIR	0x11B	/* Chip Information Register (hyper, R/0) */
364 #define SPRN_TBWL	0x11C	/* Time Base Lower Register (super, R/W) */
365 #define SPRN_TBWU	0x11D	/* Time Base Upper Register (super, R/W) */
366 #define SPRN_TBU40	0x11E	/* Timebase upper 40 bits (hyper, R/W) */
367 #define SPRN_SPURR	0x134	/* Scaled PURR */
368 #define SPRN_HSPRG0	0x130	/* Hypervisor Scratch 0 */
369 #define SPRN_HSPRG1	0x131	/* Hypervisor Scratch 1 */
370 #define SPRN_HDSISR     0x132
371 #define SPRN_HDAR       0x133
372 #define SPRN_HDEC	0x136	/* Hypervisor Decrementer */
373 #define SPRN_HIOR	0x137	/* 970 Hypervisor interrupt offset */
374 #define SPRN_RMOR	0x138	/* Real mode offset register */
375 #define SPRN_HRMOR	0x139	/* Real mode offset register */
376 #define SPRN_HSRR0	0x13A	/* Hypervisor Save/Restore 0 */
377 #define SPRN_HSRR1	0x13B	/* Hypervisor Save/Restore 1 */
378 #define SPRN_ASDR	0x330	/* Access segment descriptor register */
379 #define SPRN_IC		0x350	/* Virtual Instruction Count */
380 #define SPRN_VTB	0x351	/* Virtual Time Base */
381 #define SPRN_LDBAR	0x352	/* LD Base Address Register */
382 #define SPRN_PMICR	0x354   /* Power Management Idle Control Reg */
383 #define SPRN_PMSR	0x355   /* Power Management Status Reg */
384 #define SPRN_PMMAR	0x356	/* Power Management Memory Activity Register */
385 #define SPRN_PSSCR	0x357	/* Processor Stop Status and Control Register (ISA 3.0) */
386 #define SPRN_PSSCR_PR	0x337	/* PSSCR ISA 3.0, privileged mode access */
387 #define SPRN_PMCR	0x374	/* Power Management Control Register */
388 #define SPRN_RWMR	0x375	/* Region-Weighting Mode Register */
389 
390 /* HFSCR and FSCR bit numbers are the same */
391 #define FSCR_SCV_LG	12	/* Enable System Call Vectored */
392 #define FSCR_MSGP_LG	10	/* Enable MSGP */
393 #define FSCR_TAR_LG	8	/* Enable Target Address Register */
394 #define FSCR_EBB_LG	7	/* Enable Event Based Branching */
395 #define FSCR_TM_LG	5	/* Enable Transactional Memory */
396 #define FSCR_BHRB_LG	4	/* Enable Branch History Rolling Buffer*/
397 #define FSCR_PM_LG	3	/* Enable prob/priv access to PMU SPRs */
398 #define FSCR_DSCR_LG	2	/* Enable Data Stream Control Register */
399 #define FSCR_VECVSX_LG	1	/* Enable VMX/VSX  */
400 #define FSCR_FP_LG	0	/* Enable Floating Point */
401 #define SPRN_FSCR	0x099	/* Facility Status & Control Register */
402 #define   FSCR_SCV	__MASK(FSCR_SCV_LG)
403 #define   FSCR_TAR	__MASK(FSCR_TAR_LG)
404 #define   FSCR_EBB	__MASK(FSCR_EBB_LG)
405 #define   FSCR_DSCR	__MASK(FSCR_DSCR_LG)
406 #define SPRN_HFSCR	0xbe	/* HV=1 Facility Status & Control Register */
407 #define   HFSCR_MSGP	__MASK(FSCR_MSGP_LG)
408 #define   HFSCR_TAR	__MASK(FSCR_TAR_LG)
409 #define   HFSCR_EBB	__MASK(FSCR_EBB_LG)
410 #define   HFSCR_TM	__MASK(FSCR_TM_LG)
411 #define   HFSCR_PM	__MASK(FSCR_PM_LG)
412 #define   HFSCR_BHRB	__MASK(FSCR_BHRB_LG)
413 #define   HFSCR_DSCR	__MASK(FSCR_DSCR_LG)
414 #define   HFSCR_VECVSX	__MASK(FSCR_VECVSX_LG)
415 #define   HFSCR_FP	__MASK(FSCR_FP_LG)
416 #define SPRN_TAR	0x32f	/* Target Address Register */
417 #define SPRN_LPCR	0x13E	/* LPAR Control Register */
418 #define   LPCR_VPM0		ASM_CONST(0x8000000000000000)
419 #define   LPCR_VPM1		ASM_CONST(0x4000000000000000)
420 #define   LPCR_ISL		ASM_CONST(0x2000000000000000)
421 #define   LPCR_VC_SH		61
422 #define   LPCR_DPFD_SH		52
423 #define   LPCR_DPFD		(ASM_CONST(7) << LPCR_DPFD_SH)
424 #define   LPCR_VRMASD_SH	47
425 #define   LPCR_VRMASD		(ASM_CONST(0x1f) << LPCR_VRMASD_SH)
426 #define   LPCR_VRMA_L		ASM_CONST(0x0008000000000000)
427 #define   LPCR_VRMA_LP0		ASM_CONST(0x0001000000000000)
428 #define   LPCR_VRMA_LP1		ASM_CONST(0x0000800000000000)
429 #define   LPCR_RMLS		0x1C000000	/* Implementation dependent RMO limit sel */
430 #define   LPCR_RMLS_SH		26
431 #define   LPCR_ILE		ASM_CONST(0x0000000002000000)   /* !HV irqs set MSR:LE */
432 #define   LPCR_AIL		ASM_CONST(0x0000000001800000)	/* Alternate interrupt location */
433 #define   LPCR_AIL_0		ASM_CONST(0x0000000000000000)	/* MMU off exception offset 0x0 */
434 #define   LPCR_AIL_3		ASM_CONST(0x0000000001800000)   /* MMU on exception offset 0xc00...4xxx */
435 #define   LPCR_ONL		ASM_CONST(0x0000000000040000)	/* online - PURR/SPURR count */
436 #define   LPCR_LD		ASM_CONST(0x0000000000020000)	/* large decremeter */
437 #define   LPCR_PECE		ASM_CONST(0x000000000001f000)	/* powersave exit cause enable */
438 #define     LPCR_PECEDP	ASM_CONST(0x0000000000010000)	/* directed priv dbells cause exit */
439 #define     LPCR_PECEDH	ASM_CONST(0x0000000000008000)	/* directed hyp dbells cause exit */
440 #define     LPCR_PECE0		ASM_CONST(0x0000000000004000)	/* ext. exceptions can cause exit */
441 #define     LPCR_PECE1		ASM_CONST(0x0000000000002000)	/* decrementer can cause exit */
442 #define     LPCR_PECE2		ASM_CONST(0x0000000000001000)	/* machine check etc can cause exit */
443 #define     LPCR_PECE_HVEE	ASM_CONST(0x0000400000000000)	/* P9 Wakeup on HV interrupts */
444 #define   LPCR_MER		ASM_CONST(0x0000000000000800)	/* Mediated External Exception */
445 #define   LPCR_MER_SH		11
446 #define	  LPCR_GTSE		ASM_CONST(0x0000000000000400)  	/* Guest Translation Shootdown Enable */
447 #define   LPCR_TC		ASM_CONST(0x0000000000000200)	/* Translation control */
448 #define   LPCR_HEIC		ASM_CONST(0x0000000000000010)   /* Hypervisor External Interrupt Control */
449 #define   LPCR_LPES		0x0000000c
450 #define   LPCR_LPES0		ASM_CONST(0x0000000000000008)      /* LPAR Env selector 0 */
451 #define   LPCR_LPES1		ASM_CONST(0x0000000000000004)      /* LPAR Env selector 1 */
452 #define   LPCR_LPES_SH		2
453 #define   LPCR_RMI		ASM_CONST(0x0000000000000002)      /* real mode is cache inhibit */
454 #define   LPCR_HVICE		ASM_CONST(0x0000000000000002)      /* P9: HV interrupt enable */
455 #define   LPCR_HDICE		ASM_CONST(0x0000000000000001)      /* Hyp Decr enable (HV,PR,EE) */
456 #define   LPCR_UPRT		ASM_CONST(0x0000000000400000)      /* Use Process Table (ISA 3) */
457 #define   LPCR_HR		ASM_CONST(0x0000000000100000)
458 #ifndef SPRN_LPID
459 #define SPRN_LPID	0x13F	/* Logical Partition Identifier */
460 #endif
461 #define   LPID_RSVD	0x3ff		/* Reserved LPID for partn switching */
462 #define	SPRN_HMER	0x150	/* Hypervisor maintenance exception reg */
463 #define   HMER_DEBUG_TRIG	(1ul << (63 - 17)) /* Debug trigger */
464 #define	SPRN_HMEER	0x151	/* Hyp maintenance exception enable reg */
465 #define SPRN_PCR	0x152	/* Processor compatibility register */
466 #define   PCR_VEC_DIS	(1ul << (63-0))	/* Vec. disable (bit NA since POWER8) */
467 #define   PCR_VSX_DIS	(1ul << (63-1))	/* VSX disable (bit NA since POWER8) */
468 #define   PCR_TM_DIS	(1ul << (63-2))	/* Trans. memory disable (POWER8) */
469 /*
470  * These bits are used in the function kvmppc_set_arch_compat() to specify and
471  * determine both the compatibility level which we want to emulate and the
472  * compatibility level which the host is capable of emulating.
473  */
474 #define   PCR_ARCH_207	0x8		/* Architecture 2.07 */
475 #define   PCR_ARCH_206	0x4		/* Architecture 2.06 */
476 #define   PCR_ARCH_205	0x2		/* Architecture 2.05 */
477 #define	SPRN_HEIR	0x153	/* Hypervisor Emulated Instruction Register */
478 #define SPRN_TLBINDEXR	0x154	/* P7 TLB control register */
479 #define SPRN_TLBVPNR	0x155	/* P7 TLB control register */
480 #define SPRN_TLBRPNR	0x156	/* P7 TLB control register */
481 #define SPRN_TLBLPIDR	0x157	/* P7 TLB control register */
482 #define SPRN_DBAT0L	0x219	/* Data BAT 0 Lower Register */
483 #define SPRN_DBAT0U	0x218	/* Data BAT 0 Upper Register */
484 #define SPRN_DBAT1L	0x21B	/* Data BAT 1 Lower Register */
485 #define SPRN_DBAT1U	0x21A	/* Data BAT 1 Upper Register */
486 #define SPRN_DBAT2L	0x21D	/* Data BAT 2 Lower Register */
487 #define SPRN_DBAT2U	0x21C	/* Data BAT 2 Upper Register */
488 #define SPRN_DBAT3L	0x21F	/* Data BAT 3 Lower Register */
489 #define SPRN_DBAT3U	0x21E	/* Data BAT 3 Upper Register */
490 #define SPRN_DBAT4L	0x239	/* Data BAT 4 Lower Register */
491 #define SPRN_DBAT4U	0x238	/* Data BAT 4 Upper Register */
492 #define SPRN_DBAT5L	0x23B	/* Data BAT 5 Lower Register */
493 #define SPRN_DBAT5U	0x23A	/* Data BAT 5 Upper Register */
494 #define SPRN_DBAT6L	0x23D	/* Data BAT 6 Lower Register */
495 #define SPRN_DBAT6U	0x23C	/* Data BAT 6 Upper Register */
496 #define SPRN_DBAT7L	0x23F	/* Data BAT 7 Lower Register */
497 #define SPRN_DBAT7U	0x23E	/* Data BAT 7 Upper Register */
498 #define SPRN_PPR	0x380	/* SMT Thread status Register */
499 #define SPRN_TSCR	0x399	/* Thread Switch Control Register */
500 
501 #define SPRN_DEC	0x016		/* Decrement Register */
502 #define SPRN_DER	0x095		/* Debug Enable Register */
503 #define DER_RSTE	0x40000000	/* Reset Interrupt */
504 #define DER_CHSTPE	0x20000000	/* Check Stop */
505 #define DER_MCIE	0x10000000	/* Machine Check Interrupt */
506 #define DER_EXTIE	0x02000000	/* External Interrupt */
507 #define DER_ALIE	0x01000000	/* Alignment Interrupt */
508 #define DER_PRIE	0x00800000	/* Program Interrupt */
509 #define DER_FPUVIE	0x00400000	/* FP Unavailable Interrupt */
510 #define DER_DECIE	0x00200000	/* Decrementer Interrupt */
511 #define DER_SYSIE	0x00040000	/* System Call Interrupt */
512 #define DER_TRE		0x00020000	/* Trace Interrupt */
513 #define DER_SEIE	0x00004000	/* FP SW Emulation Interrupt */
514 #define DER_ITLBMSE	0x00002000	/* Imp. Spec. Instruction TLB Miss */
515 #define DER_ITLBERE	0x00001000	/* Imp. Spec. Instruction TLB Error */
516 #define DER_DTLBMSE	0x00000800	/* Imp. Spec. Data TLB Miss */
517 #define DER_DTLBERE	0x00000400	/* Imp. Spec. Data TLB Error */
518 #define DER_LBRKE	0x00000008	/* Load/Store Breakpoint Interrupt */
519 #define DER_IBRKE	0x00000004	/* Instruction Breakpoint Interrupt */
520 #define DER_EBRKE	0x00000002	/* External Breakpoint Interrupt */
521 #define DER_DPIE	0x00000001	/* Dev. Port Nonmaskable Request */
522 #define SPRN_DMISS	0x3D0		/* Data TLB Miss Register */
523 #define SPRN_DHDES	0x0B1		/* Directed Hyp. Doorbell Exc. State */
524 #define SPRN_DPDES	0x0B0		/* Directed Priv. Doorbell Exc. State */
525 #define SPRN_EAR	0x11A		/* External Address Register */
526 #define SPRN_HASH1	0x3D2		/* Primary Hash Address Register */
527 #define SPRN_HASH2	0x3D3		/* Secondary Hash Address Register */
528 #define SPRN_HID0	0x3F0		/* Hardware Implementation Register 0 */
529 #define HID0_HDICE_SH	(63 - 23)	/* 970 HDEC interrupt enable */
530 #define HID0_EMCP	(1<<31)		/* Enable Machine Check pin */
531 #define HID0_EBA	(1<<29)		/* Enable Bus Address Parity */
532 #define HID0_EBD	(1<<28)		/* Enable Bus Data Parity */
533 #define HID0_SBCLK	(1<<27)
534 #define HID0_EICE	(1<<26)
535 #define HID0_TBEN	(1<<26)		/* Timebase enable - 745x */
536 #define HID0_ECLK	(1<<25)
537 #define HID0_PAR	(1<<24)
538 #define HID0_STEN	(1<<24)		/* Software table search enable - 745x */
539 #define HID0_HIGH_BAT	(1<<23)		/* Enable high BATs - 7455 */
540 #define HID0_DOZE	(1<<23)
541 #define HID0_NAP	(1<<22)
542 #define HID0_SLEEP	(1<<21)
543 #define HID0_DPM	(1<<20)
544 #define HID0_BHTCLR	(1<<18)		/* Clear branch history table - 7450 */
545 #define HID0_XAEN	(1<<17)		/* Extended addressing enable - 7450 */
546 #define HID0_NHR	(1<<16)		/* Not hard reset (software bit-7450)*/
547 #define HID0_ICE	(1<<15)		/* Instruction Cache Enable */
548 #define HID0_DCE	(1<<14)		/* Data Cache Enable */
549 #define HID0_ILOCK	(1<<13)		/* Instruction Cache Lock */
550 #define HID0_DLOCK	(1<<12)		/* Data Cache Lock */
551 #define HID0_ICFI	(1<<11)		/* Instr. Cache Flash Invalidate */
552 #define HID0_DCI	(1<<10)		/* Data Cache Invalidate */
553 #define HID0_SPD	(1<<9)		/* Speculative disable */
554 #define HID0_DAPUEN	(1<<8)		/* Debug APU enable */
555 #define HID0_SGE	(1<<7)		/* Store Gathering Enable */
556 #define HID0_SIED	(1<<7)		/* Serial Instr. Execution [Disable] */
557 #define HID0_DCFA	(1<<6)		/* Data Cache Flush Assist */
558 #define HID0_LRSTK	(1<<4)		/* Link register stack - 745x */
559 #define HID0_BTIC	(1<<5)		/* Branch Target Instr Cache Enable */
560 #define HID0_ABE	(1<<3)		/* Address Broadcast Enable */
561 #define HID0_FOLD	(1<<3)		/* Branch Folding enable - 745x */
562 #define HID0_BHTE	(1<<2)		/* Branch History Table Enable */
563 #define HID0_BTCD	(1<<1)		/* Branch target cache disable */
564 #define HID0_NOPDST	(1<<1)		/* No-op dst, dstt, etc. instr. */
565 #define HID0_NOPTI	(1<<0)		/* No-op dcbt and dcbst instr. */
566 /* POWER8 HID0 bits */
567 #define HID0_POWER8_4LPARMODE	__MASK(61)
568 #define HID0_POWER8_2LPARMODE	__MASK(57)
569 #define HID0_POWER8_1TO2LPAR	__MASK(52)
570 #define HID0_POWER8_1TO4LPAR	__MASK(51)
571 #define HID0_POWER8_DYNLPARDIS	__MASK(48)
572 
573 /* POWER9 HID0 bits */
574 #define HID0_POWER9_RADIX	__MASK(63 - 8)
575 
576 #define SPRN_HID1	0x3F1		/* Hardware Implementation Register 1 */
577 #ifdef CONFIG_6xx
578 #define HID1_EMCP	(1<<31)		/* 7450 Machine Check Pin Enable */
579 #define HID1_DFS	(1<<22)		/* 7447A Dynamic Frequency Scaling */
580 #define HID1_PC0	(1<<16)		/* 7450 PLL_CFG[0] */
581 #define HID1_PC1	(1<<15)		/* 7450 PLL_CFG[1] */
582 #define HID1_PC2	(1<<14)		/* 7450 PLL_CFG[2] */
583 #define HID1_PC3	(1<<13)		/* 7450 PLL_CFG[3] */
584 #define HID1_SYNCBE	(1<<11)		/* 7450 ABE for sync, eieio */
585 #define HID1_ABE	(1<<10)		/* 7450 Address Broadcast Enable */
586 #define HID1_PS		(1<<16)		/* 750FX PLL selection */
587 #endif
588 #define SPRN_HID2	0x3F8		/* Hardware Implementation Register 2 */
589 #define SPRN_HID2_GEKKO	0x398		/* Gekko HID2 Register */
590 #define SPRN_IABR	0x3F2	/* Instruction Address Breakpoint Register */
591 #define SPRN_IABR2	0x3FA		/* 83xx */
592 #define SPRN_IBCR	0x135		/* 83xx Insn Breakpoint Control Reg */
593 #define SPRN_IAMR	0x03D		/* Instr. Authority Mask Reg */
594 #define SPRN_HID4	0x3F4		/* 970 HID4 */
595 #define  HID4_LPES0	 (1ul << (63-0)) /* LPAR env. sel. bit 0 */
596 #define	 HID4_RMLS2_SH	 (63 - 2)	/* Real mode limit bottom 2 bits */
597 #define	 HID4_LPID5_SH	 (63 - 6)	/* partition ID bottom 4 bits */
598 #define	 HID4_RMOR_SH	 (63 - 22)	/* real mode offset (16 bits) */
599 #define  HID4_RMOR	 (0xFFFFul << HID4_RMOR_SH)
600 #define  HID4_LPES1	 (1 << (63-57))	/* LPAR env. sel. bit 1 */
601 #define  HID4_RMLS0_SH	 (63 - 58)	/* Real mode limit top bit */
602 #define	 HID4_LPID1_SH	 0		/* partition ID top 2 bits */
603 #define SPRN_HID4_GEKKO	0x3F3		/* Gekko HID4 */
604 #define SPRN_HID5	0x3F6		/* 970 HID5 */
605 #define SPRN_HID6	0x3F9	/* BE HID 6 */
606 #define   HID6_LB	(0x0F<<12) /* Concurrent Large Page Modes */
607 #define   HID6_DLP	(1<<20)	/* Disable all large page modes (4K only) */
608 #define SPRN_TSC_CELL	0x399	/* Thread switch control on Cell */
609 #define   TSC_CELL_DEC_ENABLE_0	0x400000 /* Decrementer Interrupt */
610 #define   TSC_CELL_DEC_ENABLE_1	0x200000 /* Decrementer Interrupt */
611 #define   TSC_CELL_EE_ENABLE	0x100000 /* External Interrupt */
612 #define   TSC_CELL_EE_BOOST	0x080000 /* External Interrupt Boost */
613 #define SPRN_TSC 	0x3FD	/* Thread switch control on others */
614 #define SPRN_TST 	0x3FC	/* Thread switch timeout on others */
615 #if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
616 #define SPRN_IAC1	0x3F4		/* Instruction Address Compare 1 */
617 #define SPRN_IAC2	0x3F5		/* Instruction Address Compare 2 */
618 #endif
619 #define SPRN_IBAT0L	0x211		/* Instruction BAT 0 Lower Register */
620 #define SPRN_IBAT0U	0x210		/* Instruction BAT 0 Upper Register */
621 #define SPRN_IBAT1L	0x213		/* Instruction BAT 1 Lower Register */
622 #define SPRN_IBAT1U	0x212		/* Instruction BAT 1 Upper Register */
623 #define SPRN_IBAT2L	0x215		/* Instruction BAT 2 Lower Register */
624 #define SPRN_IBAT2U	0x214		/* Instruction BAT 2 Upper Register */
625 #define SPRN_IBAT3L	0x217		/* Instruction BAT 3 Lower Register */
626 #define SPRN_IBAT3U	0x216		/* Instruction BAT 3 Upper Register */
627 #define SPRN_IBAT4L	0x231		/* Instruction BAT 4 Lower Register */
628 #define SPRN_IBAT4U	0x230		/* Instruction BAT 4 Upper Register */
629 #define SPRN_IBAT5L	0x233		/* Instruction BAT 5 Lower Register */
630 #define SPRN_IBAT5U	0x232		/* Instruction BAT 5 Upper Register */
631 #define SPRN_IBAT6L	0x235		/* Instruction BAT 6 Lower Register */
632 #define SPRN_IBAT6U	0x234		/* Instruction BAT 6 Upper Register */
633 #define SPRN_IBAT7L	0x237		/* Instruction BAT 7 Lower Register */
634 #define SPRN_IBAT7U	0x236		/* Instruction BAT 7 Upper Register */
635 #define SPRN_ICMP	0x3D5		/* Instruction TLB Compare Register */
636 #define SPRN_ICTC	0x3FB	/* Instruction Cache Throttling Control Reg */
637 #ifndef SPRN_ICTRL
638 #define SPRN_ICTRL	0x3F3	/* 1011 7450 icache and interrupt ctrl */
639 #endif
640 #define ICTRL_EICE	0x08000000	/* enable icache parity errs */
641 #define ICTRL_EDC	0x04000000	/* enable dcache parity errs */
642 #define ICTRL_EICP	0x00000100	/* enable icache par. check */
643 #define SPRN_IMISS	0x3D4		/* Instruction TLB Miss Register */
644 #define SPRN_IMMR	0x27E		/* Internal Memory Map Register */
645 #define SPRN_L2CR	0x3F9		/* Level 2 Cache Control Register */
646 #define SPRN_L2CR2	0x3f8
647 #define L2CR_L2E		0x80000000	/* L2 enable */
648 #define L2CR_L2PE		0x40000000	/* L2 parity enable */
649 #define L2CR_L2SIZ_MASK		0x30000000	/* L2 size mask */
650 #define L2CR_L2SIZ_256KB	0x10000000	/* L2 size 256KB */
651 #define L2CR_L2SIZ_512KB	0x20000000	/* L2 size 512KB */
652 #define L2CR_L2SIZ_1MB		0x30000000	/* L2 size 1MB */
653 #define L2CR_L2CLK_MASK		0x0e000000	/* L2 clock mask */
654 #define L2CR_L2CLK_DISABLED	0x00000000	/* L2 clock disabled */
655 #define L2CR_L2CLK_DIV1		0x02000000	/* L2 clock / 1 */
656 #define L2CR_L2CLK_DIV1_5	0x04000000	/* L2 clock / 1.5 */
657 #define L2CR_L2CLK_DIV2		0x08000000	/* L2 clock / 2 */
658 #define L2CR_L2CLK_DIV2_5	0x0a000000	/* L2 clock / 2.5 */
659 #define L2CR_L2CLK_DIV3		0x0c000000	/* L2 clock / 3 */
660 #define L2CR_L2RAM_MASK		0x01800000	/* L2 RAM type mask */
661 #define L2CR_L2RAM_FLOW		0x00000000	/* L2 RAM flow through */
662 #define L2CR_L2RAM_PIPE		0x01000000	/* L2 RAM pipelined */
663 #define L2CR_L2RAM_PIPE_LW	0x01800000	/* L2 RAM pipelined latewr */
664 #define L2CR_L2DO		0x00400000	/* L2 data only */
665 #define L2CR_L2I		0x00200000	/* L2 global invalidate */
666 #define L2CR_L2CTL		0x00100000	/* L2 RAM control */
667 #define L2CR_L2WT		0x00080000	/* L2 write-through */
668 #define L2CR_L2TS		0x00040000	/* L2 test support */
669 #define L2CR_L2OH_MASK		0x00030000	/* L2 output hold mask */
670 #define L2CR_L2OH_0_5		0x00000000	/* L2 output hold 0.5 ns */
671 #define L2CR_L2OH_1_0		0x00010000	/* L2 output hold 1.0 ns */
672 #define L2CR_L2SL		0x00008000	/* L2 DLL slow */
673 #define L2CR_L2DF		0x00004000	/* L2 differential clock */
674 #define L2CR_L2BYP		0x00002000	/* L2 DLL bypass */
675 #define L2CR_L2IP		0x00000001	/* L2 GI in progress */
676 #define L2CR_L2IO_745x		0x00100000	/* L2 instr. only (745x) */
677 #define L2CR_L2DO_745x		0x00010000	/* L2 data only (745x) */
678 #define L2CR_L2REP_745x		0x00001000	/* L2 repl. algorithm (745x) */
679 #define L2CR_L2HWF_745x		0x00000800	/* L2 hardware flush (745x) */
680 #define SPRN_L3CR		0x3FA	/* Level 3 Cache Control Register */
681 #define L3CR_L3E		0x80000000	/* L3 enable */
682 #define L3CR_L3PE		0x40000000	/* L3 data parity enable */
683 #define L3CR_L3APE		0x20000000	/* L3 addr parity enable */
684 #define L3CR_L3SIZ		0x10000000	/* L3 size */
685 #define L3CR_L3CLKEN		0x08000000	/* L3 clock enable */
686 #define L3CR_L3RES		0x04000000	/* L3 special reserved bit */
687 #define L3CR_L3CLKDIV		0x03800000	/* L3 clock divisor */
688 #define L3CR_L3IO		0x00400000	/* L3 instruction only */
689 #define L3CR_L3SPO		0x00040000	/* L3 sample point override */
690 #define L3CR_L3CKSP		0x00030000	/* L3 clock sample point */
691 #define L3CR_L3PSP		0x0000e000	/* L3 P-clock sample point */
692 #define L3CR_L3REP		0x00001000	/* L3 replacement algorithm */
693 #define L3CR_L3HWF		0x00000800	/* L3 hardware flush */
694 #define L3CR_L3I		0x00000400	/* L3 global invalidate */
695 #define L3CR_L3RT		0x00000300	/* L3 SRAM type */
696 #define L3CR_L3NIRCA		0x00000080	/* L3 non-integer ratio clock adj. */
697 #define L3CR_L3DO		0x00000040	/* L3 data only mode */
698 #define L3CR_PMEN		0x00000004	/* L3 private memory enable */
699 #define L3CR_PMSIZ		0x00000001	/* L3 private memory size */
700 
701 #define SPRN_MSSCR0	0x3f6	/* Memory Subsystem Control Register 0 */
702 #define SPRN_MSSSR0	0x3f7	/* Memory Subsystem Status Register 1 */
703 #define SPRN_LDSTCR	0x3f8	/* Load/Store control register */
704 #define SPRN_LDSTDB	0x3f4	/* */
705 #define SPRN_LR		0x008	/* Link Register */
706 #ifndef SPRN_PIR
707 #define SPRN_PIR	0x3FF	/* Processor Identification Register */
708 #endif
709 #define SPRN_TIR	0x1BE	/* Thread Identification Register */
710 #define SPRN_PTCR	0x1D0	/* Partition table control Register */
711 #define SPRN_PSPB	0x09F	/* Problem State Priority Boost reg */
712 #define SPRN_PTEHI	0x3D5	/* 981 7450 PTE HI word (S/W TLB load) */
713 #define SPRN_PTELO	0x3D6	/* 982 7450 PTE LO word (S/W TLB load) */
714 #define SPRN_PURR	0x135	/* Processor Utilization of Resources Reg */
715 #define SPRN_PVR	0x11F	/* Processor Version Register */
716 #define SPRN_RPA	0x3D6	/* Required Physical Address Register */
717 #define SPRN_SDA	0x3BF	/* Sampled Data Address Register */
718 #define SPRN_SDR1	0x019	/* MMU Hash Base Register */
719 #define SPRN_ASR	0x118   /* Address Space Register */
720 #define SPRN_SIA	0x3BB	/* Sampled Instruction Address Register */
721 #define SPRN_SPRG0	0x110	/* Special Purpose Register General 0 */
722 #define SPRN_SPRG1	0x111	/* Special Purpose Register General 1 */
723 #define SPRN_SPRG2	0x112	/* Special Purpose Register General 2 */
724 #define SPRN_SPRG3	0x113	/* Special Purpose Register General 3 */
725 #define SPRN_USPRG3	0x103	/* SPRG3 userspace read */
726 #define SPRN_SPRG4	0x114	/* Special Purpose Register General 4 */
727 #define SPRN_USPRG4	0x104	/* SPRG4 userspace read */
728 #define SPRN_SPRG5	0x115	/* Special Purpose Register General 5 */
729 #define SPRN_USPRG5	0x105	/* SPRG5 userspace read */
730 #define SPRN_SPRG6	0x116	/* Special Purpose Register General 6 */
731 #define SPRN_USPRG6	0x106	/* SPRG6 userspace read */
732 #define SPRN_SPRG7	0x117	/* Special Purpose Register General 7 */
733 #define SPRN_USPRG7	0x107	/* SPRG7 userspace read */
734 #define SPRN_SRR0	0x01A	/* Save/Restore Register 0 */
735 #define SPRN_SRR1	0x01B	/* Save/Restore Register 1 */
736 #define   SRR1_ISI_NOPT		0x40000000 /* ISI: Not found in hash */
737 #define   SRR1_ISI_N_OR_G	0x10000000 /* ISI: Access is no-exec or G */
738 #define   SRR1_ISI_PROT		0x08000000 /* ISI: Other protection fault */
739 #define   SRR1_WAKEMASK		0x00380000 /* reason for wakeup */
740 #define   SRR1_WAKEMASK_P8	0x003c0000 /* reason for wakeup on POWER8 and 9 */
741 #define   SRR1_WAKEMCE_RESVD	0x003c0000 /* Unused/reserved value used by MCE wakeup to indicate cause to idle wakeup handler */
742 #define   SRR1_WAKESYSERR	0x00300000 /* System error */
743 #define   SRR1_WAKEEE		0x00200000 /* External interrupt */
744 #define   SRR1_WAKEHVI		0x00240000 /* Hypervisor Virtualization Interrupt (P9) */
745 #define   SRR1_WAKEMT		0x00280000 /* mtctrl */
746 #define	  SRR1_WAKEHMI		0x00280000 /* Hypervisor maintenance */
747 #define   SRR1_WAKEDEC		0x00180000 /* Decrementer interrupt */
748 #define   SRR1_WAKEDBELL	0x00140000 /* Privileged doorbell on P8 */
749 #define   SRR1_WAKETHERM	0x00100000 /* Thermal management interrupt */
750 #define	  SRR1_WAKERESET	0x00100000 /* System reset */
751 #define   SRR1_WAKEHDBELL	0x000c0000 /* Hypervisor doorbell on P8 */
752 #define	  SRR1_WAKESTATE	0x00030000 /* Powersave exit mask [46:47] */
753 #define	  SRR1_WS_DEEPEST	0x00030000 /* Some resources not maintained,
754 					  * may not be recoverable */
755 #define	  SRR1_WS_DEEPER	0x00020000 /* Some resources not maintained */
756 #define	  SRR1_WS_DEEP		0x00010000 /* All resources maintained */
757 #define   SRR1_PROGTM		0x00200000 /* TM Bad Thing */
758 #define   SRR1_PROGFPE		0x00100000 /* Floating Point Enabled */
759 #define   SRR1_PROGILL		0x00080000 /* Illegal instruction */
760 #define   SRR1_PROGPRIV		0x00040000 /* Privileged instruction */
761 #define   SRR1_PROGTRAP		0x00020000 /* Trap */
762 #define   SRR1_PROGADDR		0x00010000 /* SRR0 contains subsequent addr */
763 
764 #define SPRN_HSRR0	0x13A	/* Save/Restore Register 0 */
765 #define SPRN_HSRR1	0x13B	/* Save/Restore Register 1 */
766 #define   HSRR1_DENORM		0x00100000 /* Denorm exception */
767 
768 #define SPRN_TBCTL	0x35f	/* PA6T Timebase control register */
769 #define   TBCTL_FREEZE		0x0000000000000000ull /* Freeze all tbs */
770 #define   TBCTL_RESTART		0x0000000100000000ull /* Restart all tbs */
771 #define   TBCTL_UPDATE_UPPER	0x0000000200000000ull /* Set upper 32 bits */
772 #define   TBCTL_UPDATE_LOWER	0x0000000300000000ull /* Set lower 32 bits */
773 
774 #ifndef SPRN_SVR
775 #define SPRN_SVR	0x11E	/* System Version Register */
776 #endif
777 #define SPRN_THRM1	0x3FC		/* Thermal Management Register 1 */
778 /* these bits were defined in inverted endian sense originally, ugh, confusing */
779 #define THRM1_TIN	(1 << 31)
780 #define THRM1_TIV	(1 << 30)
781 #define THRM1_THRES(x)	((x&0x7f)<<23)
782 #define THRM3_SITV(x)	((x&0x3fff)<<1)
783 #define THRM1_TID	(1<<2)
784 #define THRM1_TIE	(1<<1)
785 #define THRM1_V		(1<<0)
786 #define SPRN_THRM2	0x3FD		/* Thermal Management Register 2 */
787 #define SPRN_THRM3	0x3FE		/* Thermal Management Register 3 */
788 #define THRM3_E		(1<<0)
789 #define SPRN_TLBMISS	0x3D4		/* 980 7450 TLB Miss Register */
790 #define SPRN_UMMCR0	0x3A8	/* User Monitor Mode Control Register 0 */
791 #define SPRN_UMMCR1	0x3AC	/* User Monitor Mode Control Register 0 */
792 #define SPRN_UPMC1	0x3A9	/* User Performance Counter Register 1 */
793 #define SPRN_UPMC2	0x3AA	/* User Performance Counter Register 2 */
794 #define SPRN_UPMC3	0x3AD	/* User Performance Counter Register 3 */
795 #define SPRN_UPMC4	0x3AE	/* User Performance Counter Register 4 */
796 #define SPRN_USIA	0x3AB	/* User Sampled Instruction Address Register */
797 #define SPRN_VRSAVE	0x100	/* Vector Register Save Register */
798 #define SPRN_XER	0x001	/* Fixed Point Exception Register */
799 
800 #define SPRN_MMCR0_GEKKO 0x3B8 /* Gekko Monitor Mode Control Register 0 */
801 #define SPRN_MMCR1_GEKKO 0x3BC /* Gekko Monitor Mode Control Register 1 */
802 #define SPRN_PMC1_GEKKO  0x3B9 /* Gekko Performance Monitor Control 1 */
803 #define SPRN_PMC2_GEKKO  0x3BA /* Gekko Performance Monitor Control 2 */
804 #define SPRN_PMC3_GEKKO  0x3BD /* Gekko Performance Monitor Control 3 */
805 #define SPRN_PMC4_GEKKO  0x3BE /* Gekko Performance Monitor Control 4 */
806 #define SPRN_WPAR_GEKKO  0x399 /* Gekko Write Pipe Address Register */
807 
808 #define SPRN_SCOMC	0x114	/* SCOM Access Control */
809 #define SPRN_SCOMD	0x115	/* SCOM Access DATA */
810 
811 /* Performance monitor SPRs */
812 #ifdef CONFIG_PPC64
813 #define SPRN_MMCR0	795
814 #define   MMCR0_FC	0x80000000UL /* freeze counters */
815 #define   MMCR0_FCS	0x40000000UL /* freeze in supervisor state */
816 #define   MMCR0_KERNEL_DISABLE MMCR0_FCS
817 #define   MMCR0_FCP	0x20000000UL /* freeze in problem state */
818 #define   MMCR0_PROBLEM_DISABLE MMCR0_FCP
819 #define   MMCR0_FCM1	0x10000000UL /* freeze counters while MSR mark = 1 */
820 #define   MMCR0_FCM0	0x08000000UL /* freeze counters while MSR mark = 0 */
821 #define   MMCR0_PMXE	ASM_CONST(0x04000000) /* perf mon exception enable */
822 #define   MMCR0_FCECE	ASM_CONST(0x02000000) /* freeze ctrs on enabled cond or event */
823 #define   MMCR0_TBEE	0x00400000UL /* time base exception enable */
824 #define   MMCR0_BHRBA	0x00200000UL /* BHRB Access allowed in userspace */
825 #define   MMCR0_EBE	0x00100000UL /* Event based branch enable */
826 #define   MMCR0_PMCC	0x000c0000UL /* PMC control */
827 #define   MMCR0_PMCC_U6	0x00080000UL /* PMC1-6 are R/W by user (PR) */
828 #define   MMCR0_PMC1CE	0x00008000UL /* PMC1 count enable*/
829 #define   MMCR0_PMCjCE	ASM_CONST(0x00004000) /* PMCj count enable*/
830 #define   MMCR0_TRIGGER	0x00002000UL /* TRIGGER enable */
831 #define   MMCR0_PMAO_SYNC ASM_CONST(0x00000800) /* PMU intr is synchronous */
832 #define   MMCR0_C56RUN	ASM_CONST(0x00000100) /* PMC5/6 count when RUN=0 */
833 /* performance monitor alert has occurred, set to 0 after handling exception */
834 #define   MMCR0_PMAO	ASM_CONST(0x00000080)
835 #define   MMCR0_SHRFC	0x00000040UL /* SHRre freeze conditions between threads */
836 #define   MMCR0_FC56	0x00000010UL /* freeze counters 5 and 6 */
837 #define   MMCR0_FCTI	0x00000008UL /* freeze counters in tags inactive mode */
838 #define   MMCR0_FCTA	0x00000004UL /* freeze counters in tags active mode */
839 #define   MMCR0_FCWAIT	0x00000002UL /* freeze counter in WAIT state */
840 #define   MMCR0_FCHV	0x00000001UL /* freeze conditions in hypervisor mode */
841 #define SPRN_MMCR1	798
842 #define SPRN_MMCR2	785
843 #define SPRN_UMMCR2	769
844 #define SPRN_MMCRA	0x312
845 #define   MMCRA_SDSYNC	0x80000000UL /* SDAR synced with SIAR */
846 #define   MMCRA_SDAR_DCACHE_MISS 0x40000000UL
847 #define   MMCRA_SDAR_ERAT_MISS   0x20000000UL
848 #define   MMCRA_SIHV	0x10000000UL /* state of MSR HV when SIAR set */
849 #define   MMCRA_SIPR	0x08000000UL /* state of MSR PR when SIAR set */
850 #define   MMCRA_SLOT	0x07000000UL /* SLOT bits (37-39) */
851 #define   MMCRA_SLOT_SHIFT	24
852 #define   MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
853 #define   POWER6_MMCRA_SDSYNC 0x0000080000000000ULL	/* SDAR/SIAR synced */
854 #define   POWER6_MMCRA_SIHV   0x0000040000000000ULL
855 #define   POWER6_MMCRA_SIPR   0x0000020000000000ULL
856 #define   POWER6_MMCRA_THRM	0x00000020UL
857 #define   POWER6_MMCRA_OTHER	0x0000000EUL
858 
859 #define   POWER7P_MMCRA_SIAR_VALID 0x10000000	/* P7+ SIAR contents valid */
860 #define   POWER7P_MMCRA_SDAR_VALID 0x08000000	/* P7+ SDAR contents valid */
861 
862 #define SPRN_MMCRH	316	/* Hypervisor monitor mode control register */
863 #define SPRN_MMCRS	894	/* Supervisor monitor mode control register */
864 #define SPRN_MMCRC	851	/* Core monitor mode control register */
865 #define SPRN_EBBHR	804	/* Event based branch handler register */
866 #define SPRN_EBBRR	805	/* Event based branch return register */
867 #define SPRN_BESCR	806	/* Branch event status and control register */
868 #define   BESCR_GE	0x8000000000000000ULL /* Global Enable */
869 #define SPRN_WORT	895	/* Workload optimization register - thread */
870 #define SPRN_WORC	863	/* Workload optimization register - core */
871 
872 #define SPRN_PMC1	787
873 #define SPRN_PMC2	788
874 #define SPRN_PMC3	789
875 #define SPRN_PMC4	790
876 #define SPRN_PMC5	791
877 #define SPRN_PMC6	792
878 #define SPRN_PMC7	793
879 #define SPRN_PMC8	794
880 #define SPRN_SIER	784
881 #define   SIER_SIPR		0x2000000	/* Sampled MSR_PR */
882 #define   SIER_SIHV		0x1000000	/* Sampled MSR_HV */
883 #define   SIER_SIAR_VALID	0x0400000	/* SIAR contents valid */
884 #define   SIER_SDAR_VALID	0x0200000	/* SDAR contents valid */
885 #define SPRN_SIAR	796
886 #define SPRN_SDAR	797
887 #define SPRN_TACR	888
888 #define SPRN_TCSCR	889
889 #define SPRN_CSIGR	890
890 #define SPRN_SPMC1	892
891 #define SPRN_SPMC2	893
892 
893 /* When EBB is enabled, some of MMCR0/MMCR2/SIER are user accessible */
894 #define MMCR0_USER_MASK	(MMCR0_FC | MMCR0_PMXE | MMCR0_PMAO)
895 #define MMCR2_USER_MASK	0x4020100804020000UL /* (FC1P|FC2P|FC3P|FC4P|FC5P|FC6P) */
896 #define SIER_USER_MASK	0x7fffffUL
897 
898 #define SPRN_PA6T_MMCR0 795
899 #define   PA6T_MMCR0_EN0	0x0000000000000001UL
900 #define   PA6T_MMCR0_EN1	0x0000000000000002UL
901 #define   PA6T_MMCR0_EN2	0x0000000000000004UL
902 #define   PA6T_MMCR0_EN3	0x0000000000000008UL
903 #define   PA6T_MMCR0_EN4	0x0000000000000010UL
904 #define   PA6T_MMCR0_EN5	0x0000000000000020UL
905 #define   PA6T_MMCR0_SUPEN	0x0000000000000040UL
906 #define   PA6T_MMCR0_PREN	0x0000000000000080UL
907 #define   PA6T_MMCR0_HYPEN	0x0000000000000100UL
908 #define   PA6T_MMCR0_FCM0	0x0000000000000200UL
909 #define   PA6T_MMCR0_FCM1	0x0000000000000400UL
910 #define   PA6T_MMCR0_INTGEN	0x0000000000000800UL
911 #define   PA6T_MMCR0_INTEN0	0x0000000000001000UL
912 #define   PA6T_MMCR0_INTEN1	0x0000000000002000UL
913 #define   PA6T_MMCR0_INTEN2	0x0000000000004000UL
914 #define   PA6T_MMCR0_INTEN3	0x0000000000008000UL
915 #define   PA6T_MMCR0_INTEN4	0x0000000000010000UL
916 #define   PA6T_MMCR0_INTEN5	0x0000000000020000UL
917 #define   PA6T_MMCR0_DISCNT	0x0000000000040000UL
918 #define   PA6T_MMCR0_UOP	0x0000000000080000UL
919 #define   PA6T_MMCR0_TRG	0x0000000000100000UL
920 #define   PA6T_MMCR0_TRGEN	0x0000000000200000UL
921 #define   PA6T_MMCR0_TRGREG	0x0000000001600000UL
922 #define   PA6T_MMCR0_SIARLOG	0x0000000002000000UL
923 #define   PA6T_MMCR0_SDARLOG	0x0000000004000000UL
924 #define   PA6T_MMCR0_PROEN	0x0000000008000000UL
925 #define   PA6T_MMCR0_PROLOG	0x0000000010000000UL
926 #define   PA6T_MMCR0_DAMEN2	0x0000000020000000UL
927 #define   PA6T_MMCR0_DAMEN3	0x0000000040000000UL
928 #define   PA6T_MMCR0_DAMEN4	0x0000000080000000UL
929 #define   PA6T_MMCR0_DAMEN5	0x0000000100000000UL
930 #define   PA6T_MMCR0_DAMSEL2	0x0000000200000000UL
931 #define   PA6T_MMCR0_DAMSEL3	0x0000000400000000UL
932 #define   PA6T_MMCR0_DAMSEL4	0x0000000800000000UL
933 #define   PA6T_MMCR0_DAMSEL5	0x0000001000000000UL
934 #define   PA6T_MMCR0_HANDDIS	0x0000002000000000UL
935 #define   PA6T_MMCR0_PCTEN	0x0000004000000000UL
936 #define   PA6T_MMCR0_SOCEN	0x0000008000000000UL
937 #define   PA6T_MMCR0_SOCMOD	0x0000010000000000UL
938 
939 #define SPRN_PA6T_MMCR1 798
940 #define   PA6T_MMCR1_ES2	0x00000000000000ffUL
941 #define   PA6T_MMCR1_ES3	0x000000000000ff00UL
942 #define   PA6T_MMCR1_ES4	0x0000000000ff0000UL
943 #define   PA6T_MMCR1_ES5	0x00000000ff000000UL
944 
945 #define SPRN_PA6T_UPMC0 771	/* User PerfMon Counter 0 */
946 #define SPRN_PA6T_UPMC1 772	/* ... */
947 #define SPRN_PA6T_UPMC2 773
948 #define SPRN_PA6T_UPMC3 774
949 #define SPRN_PA6T_UPMC4 775
950 #define SPRN_PA6T_UPMC5 776
951 #define SPRN_PA6T_UMMCR0 779	/* User Monitor Mode Control Register 0 */
952 #define SPRN_PA6T_SIAR	780	/* Sampled Instruction Address */
953 #define SPRN_PA6T_UMMCR1 782	/* User Monitor Mode Control Register 1 */
954 #define SPRN_PA6T_SIER	785	/* Sampled Instruction Event Register */
955 #define SPRN_PA6T_PMC0	787
956 #define SPRN_PA6T_PMC1	788
957 #define SPRN_PA6T_PMC2	789
958 #define SPRN_PA6T_PMC3	790
959 #define SPRN_PA6T_PMC4	791
960 #define SPRN_PA6T_PMC5	792
961 #define SPRN_PA6T_TSR0	793	/* Timestamp Register 0 */
962 #define SPRN_PA6T_TSR1	794	/* Timestamp Register 1 */
963 #define SPRN_PA6T_TSR2	799	/* Timestamp Register 2 */
964 #define SPRN_PA6T_TSR3	784	/* Timestamp Register 3 */
965 
966 #define SPRN_PA6T_IER	981	/* Icache Error Register */
967 #define SPRN_PA6T_DER	982	/* Dcache Error Register */
968 #define SPRN_PA6T_BER	862	/* BIU Error Address Register */
969 #define SPRN_PA6T_MER	849	/* MMU Error Register */
970 
971 #define SPRN_PA6T_IMA0	880	/* Instruction Match Array 0 */
972 #define SPRN_PA6T_IMA1	881	/* ... */
973 #define SPRN_PA6T_IMA2	882
974 #define SPRN_PA6T_IMA3	883
975 #define SPRN_PA6T_IMA4	884
976 #define SPRN_PA6T_IMA5	885
977 #define SPRN_PA6T_IMA6	886
978 #define SPRN_PA6T_IMA7	887
979 #define SPRN_PA6T_IMA8	888
980 #define SPRN_PA6T_IMA9	889
981 #define SPRN_PA6T_BTCR	978	/* Breakpoint and Tagging Control Register */
982 #define SPRN_PA6T_IMAAT	979	/* Instruction Match Array Action Table */
983 #define SPRN_PA6T_PCCR	1019	/* Power Counter Control Register */
984 #define SPRN_BKMK	1020	/* Cell Bookmark Register */
985 #define SPRN_PA6T_RPCCR	1021	/* Retire PC Trace Control Register */
986 
987 
988 #else /* 32-bit */
989 #define SPRN_MMCR0	952	/* Monitor Mode Control Register 0 */
990 #define   MMCR0_FC	0x80000000UL /* freeze counters */
991 #define   MMCR0_FCS	0x40000000UL /* freeze in supervisor state */
992 #define   MMCR0_FCP	0x20000000UL /* freeze in problem state */
993 #define   MMCR0_FCM1	0x10000000UL /* freeze counters while MSR mark = 1 */
994 #define   MMCR0_FCM0	0x08000000UL /* freeze counters while MSR mark = 0 */
995 #define   MMCR0_PMXE	0x04000000UL /* performance monitor exception enable */
996 #define   MMCR0_FCECE	0x02000000UL /* freeze ctrs on enabled cond or event */
997 #define   MMCR0_TBEE	0x00400000UL /* time base exception enable */
998 #define   MMCR0_PMC1CE	0x00008000UL /* PMC1 count enable*/
999 #define   MMCR0_PMCnCE	0x00004000UL /* count enable for all but PMC 1*/
1000 #define   MMCR0_TRIGGER	0x00002000UL /* TRIGGER enable */
1001 #define   MMCR0_PMC1SEL	0x00001fc0UL /* PMC 1 Event */
1002 #define   MMCR0_PMC2SEL	0x0000003fUL /* PMC 2 Event */
1003 
1004 #define SPRN_MMCR1	956
1005 #define   MMCR1_PMC3SEL	0xf8000000UL /* PMC 3 Event */
1006 #define   MMCR1_PMC4SEL	0x07c00000UL /* PMC 4 Event */
1007 #define   MMCR1_PMC5SEL	0x003e0000UL /* PMC 5 Event */
1008 #define   MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */
1009 #define SPRN_MMCR2	944
1010 #define SPRN_PMC1	953	/* Performance Counter Register 1 */
1011 #define SPRN_PMC2	954	/* Performance Counter Register 2 */
1012 #define SPRN_PMC3	957	/* Performance Counter Register 3 */
1013 #define SPRN_PMC4	958	/* Performance Counter Register 4 */
1014 #define SPRN_PMC5	945	/* Performance Counter Register 5 */
1015 #define SPRN_PMC6	946	/* Performance Counter Register 6 */
1016 
1017 #define SPRN_SIAR	955	/* Sampled Instruction Address Register */
1018 
1019 /* Bit definitions for MMCR0 and PMC1 / PMC2. */
1020 #define MMCR0_PMC1_CYCLES	(1 << 7)
1021 #define MMCR0_PMC1_ICACHEMISS	(5 << 7)
1022 #define MMCR0_PMC1_DTLB		(6 << 7)
1023 #define MMCR0_PMC2_DCACHEMISS	0x6
1024 #define MMCR0_PMC2_CYCLES	0x1
1025 #define MMCR0_PMC2_ITLB		0x7
1026 #define MMCR0_PMC2_LOADMISSTIME	0x5
1027 #endif
1028 
1029 /*
1030  * SPRG usage:
1031  *
1032  * All 64-bit:
1033  *	- SPRG1 stores PACA pointer except 64-bit server in
1034  *        HV mode in which case it is HSPRG0
1035  *
1036  * 64-bit server:
1037  *	- SPRG0 scratch for TM recheckpoint/reclaim (reserved for HV on Power4)
1038  *	- SPRG2 scratch for exception vectors
1039  *	- SPRG3 CPU and NUMA node for VDSO getcpu (user visible)
1040  *      - HSPRG0 stores PACA in HV mode
1041  *      - HSPRG1 scratch for "HV" exceptions
1042  *
1043  * 64-bit embedded
1044  *	- SPRG0 generic exception scratch
1045  *	- SPRG2 TLB exception stack
1046  *	- SPRG3 critical exception scratch (user visible, sorry!)
1047  *	- SPRG4 unused (user visible)
1048  *	- SPRG6 TLB miss scratch (user visible, sorry !)
1049  *	- SPRG7 CPU and NUMA node for VDSO getcpu (user visible)
1050  *	- SPRG8 machine check exception scratch
1051  *	- SPRG9 debug exception scratch
1052  *
1053  * All 32-bit:
1054  *	- SPRG3 current thread_info pointer
1055  *        (virtual on BookE, physical on others)
1056  *
1057  * 32-bit classic:
1058  *	- SPRG0 scratch for exception vectors
1059  *	- SPRG1 scratch for exception vectors
1060  *	- SPRG2 indicator that we are in RTAS
1061  *	- SPRG4 (603 only) pseudo TLB LRU data
1062  *
1063  * 32-bit 40x:
1064  *	- SPRG0 scratch for exception vectors
1065  *	- SPRG1 scratch for exception vectors
1066  *	- SPRG2 scratch for exception vectors
1067  *	- SPRG4 scratch for exception vectors (not 403)
1068  *	- SPRG5 scratch for exception vectors (not 403)
1069  *	- SPRG6 scratch for exception vectors (not 403)
1070  *	- SPRG7 scratch for exception vectors (not 403)
1071  *
1072  * 32-bit 440 and FSL BookE:
1073  *	- SPRG0 scratch for exception vectors
1074  *	- SPRG1 scratch for exception vectors (*)
1075  *	- SPRG2 scratch for crit interrupts handler
1076  *	- SPRG4 scratch for exception vectors
1077  *	- SPRG5 scratch for exception vectors
1078  *	- SPRG6 scratch for machine check handler
1079  *	- SPRG7 scratch for exception vectors
1080  *	- SPRG9 scratch for debug vectors (e500 only)
1081  *
1082  *      Additionally, BookE separates "read" and "write"
1083  *      of those registers. That allows to use the userspace
1084  *      readable variant for reads, which can avoid a fault
1085  *      with KVM type virtualization.
1086  *
1087  * 32-bit 8xx:
1088  *	- SPRG0 scratch for exception vectors
1089  *	- SPRG1 scratch for exception vectors
1090  *	- SPRG2 scratch for exception vectors
1091  *
1092  */
1093 #ifdef CONFIG_PPC64
1094 #define SPRN_SPRG_PACA 		SPRN_SPRG1
1095 #else
1096 #define SPRN_SPRG_THREAD 	SPRN_SPRG3
1097 #endif
1098 
1099 #ifdef CONFIG_PPC_BOOK3S_64
1100 #define SPRN_SPRG_SCRATCH0	SPRN_SPRG2
1101 #define SPRN_SPRG_HPACA		SPRN_HSPRG0
1102 #define SPRN_SPRG_HSCRATCH0	SPRN_HSPRG1
1103 #define SPRN_SPRG_VDSO_READ	SPRN_USPRG3
1104 #define SPRN_SPRG_VDSO_WRITE	SPRN_SPRG3
1105 
1106 #define GET_PACA(rX)					\
1107 	BEGIN_FTR_SECTION_NESTED(66);			\
1108 	mfspr	rX,SPRN_SPRG_PACA;			\
1109 	FTR_SECTION_ELSE_NESTED(66);			\
1110 	mfspr	rX,SPRN_SPRG_HPACA;			\
1111 	ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1112 
1113 #define SET_PACA(rX)					\
1114 	BEGIN_FTR_SECTION_NESTED(66);			\
1115 	mtspr	SPRN_SPRG_PACA,rX;			\
1116 	FTR_SECTION_ELSE_NESTED(66);			\
1117 	mtspr	SPRN_SPRG_HPACA,rX;			\
1118 	ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1119 
1120 #define GET_SCRATCH0(rX)				\
1121 	BEGIN_FTR_SECTION_NESTED(66);			\
1122 	mfspr	rX,SPRN_SPRG_SCRATCH0;			\
1123 	FTR_SECTION_ELSE_NESTED(66);			\
1124 	mfspr	rX,SPRN_SPRG_HSCRATCH0;			\
1125 	ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1126 
1127 #define SET_SCRATCH0(rX)				\
1128 	BEGIN_FTR_SECTION_NESTED(66);			\
1129 	mtspr	SPRN_SPRG_SCRATCH0,rX;			\
1130 	FTR_SECTION_ELSE_NESTED(66);			\
1131 	mtspr	SPRN_SPRG_HSCRATCH0,rX;			\
1132 	ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1133 
1134 #else /* CONFIG_PPC_BOOK3S_64 */
1135 #define GET_SCRATCH0(rX)	mfspr	rX,SPRN_SPRG_SCRATCH0
1136 #define SET_SCRATCH0(rX)	mtspr	SPRN_SPRG_SCRATCH0,rX
1137 
1138 #endif
1139 
1140 #ifdef CONFIG_PPC_BOOK3E_64
1141 #define SPRN_SPRG_MC_SCRATCH	SPRN_SPRG8
1142 #define SPRN_SPRG_CRIT_SCRATCH	SPRN_SPRG3
1143 #define SPRN_SPRG_DBG_SCRATCH	SPRN_SPRG9
1144 #define SPRN_SPRG_TLB_EXFRAME	SPRN_SPRG2
1145 #define SPRN_SPRG_TLB_SCRATCH	SPRN_SPRG6
1146 #define SPRN_SPRG_GEN_SCRATCH	SPRN_SPRG0
1147 #define SPRN_SPRG_GDBELL_SCRATCH SPRN_SPRG_GEN_SCRATCH
1148 #define SPRN_SPRG_VDSO_READ	SPRN_USPRG7
1149 #define SPRN_SPRG_VDSO_WRITE	SPRN_SPRG7
1150 
1151 #define SET_PACA(rX)	mtspr	SPRN_SPRG_PACA,rX
1152 #define GET_PACA(rX)	mfspr	rX,SPRN_SPRG_PACA
1153 
1154 #endif
1155 
1156 #ifdef CONFIG_PPC_BOOK3S_32
1157 #define SPRN_SPRG_SCRATCH0	SPRN_SPRG0
1158 #define SPRN_SPRG_SCRATCH1	SPRN_SPRG1
1159 #define SPRN_SPRG_RTAS		SPRN_SPRG2
1160 #define SPRN_SPRG_603_LRU	SPRN_SPRG4
1161 #endif
1162 
1163 #ifdef CONFIG_40x
1164 #define SPRN_SPRG_SCRATCH0	SPRN_SPRG0
1165 #define SPRN_SPRG_SCRATCH1	SPRN_SPRG1
1166 #define SPRN_SPRG_SCRATCH2	SPRN_SPRG2
1167 #define SPRN_SPRG_SCRATCH3	SPRN_SPRG4
1168 #define SPRN_SPRG_SCRATCH4	SPRN_SPRG5
1169 #define SPRN_SPRG_SCRATCH5	SPRN_SPRG6
1170 #define SPRN_SPRG_SCRATCH6	SPRN_SPRG7
1171 #endif
1172 
1173 #ifdef CONFIG_BOOKE
1174 #define SPRN_SPRG_RSCRATCH0	SPRN_SPRG0
1175 #define SPRN_SPRG_WSCRATCH0	SPRN_SPRG0
1176 #define SPRN_SPRG_RSCRATCH1	SPRN_SPRG1
1177 #define SPRN_SPRG_WSCRATCH1	SPRN_SPRG1
1178 #define SPRN_SPRG_RSCRATCH_CRIT	SPRN_SPRG2
1179 #define SPRN_SPRG_WSCRATCH_CRIT	SPRN_SPRG2
1180 #define SPRN_SPRG_RSCRATCH2	SPRN_SPRG4R
1181 #define SPRN_SPRG_WSCRATCH2	SPRN_SPRG4W
1182 #define SPRN_SPRG_RSCRATCH3	SPRN_SPRG5R
1183 #define SPRN_SPRG_WSCRATCH3	SPRN_SPRG5W
1184 #define SPRN_SPRG_RSCRATCH_MC	SPRN_SPRG1
1185 #define SPRN_SPRG_WSCRATCH_MC	SPRN_SPRG1
1186 #define SPRN_SPRG_RSCRATCH4	SPRN_SPRG7R
1187 #define SPRN_SPRG_WSCRATCH4	SPRN_SPRG7W
1188 #ifdef CONFIG_E200
1189 #define SPRN_SPRG_RSCRATCH_DBG	SPRN_SPRG6R
1190 #define SPRN_SPRG_WSCRATCH_DBG	SPRN_SPRG6W
1191 #else
1192 #define SPRN_SPRG_RSCRATCH_DBG	SPRN_SPRG9
1193 #define SPRN_SPRG_WSCRATCH_DBG	SPRN_SPRG9
1194 #endif
1195 #endif
1196 
1197 #ifdef CONFIG_PPC_8xx
1198 #define SPRN_SPRG_SCRATCH0	SPRN_SPRG0
1199 #define SPRN_SPRG_SCRATCH1	SPRN_SPRG1
1200 #define SPRN_SPRG_SCRATCH2	SPRN_SPRG2
1201 #endif
1202 
1203 
1204 
1205 /*
1206  * An mtfsf instruction with the L bit set. On CPUs that support this a
1207  * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored.
1208  *
1209  * Until binutils gets the new form of mtfsf, hardwire the instruction.
1210  */
1211 #ifdef CONFIG_PPC64
1212 #define MTFSF_L(REG) \
1213 	.long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
1214 #else
1215 #define MTFSF_L(REG)	mtfsf	0xff, (REG)
1216 #endif
1217 
1218 /* Processor Version Register (PVR) field extraction */
1219 
1220 #define PVR_VER(pvr)	(((pvr) >>  16) & 0xFFFF)	/* Version field */
1221 #define PVR_REV(pvr)	(((pvr) >>   0) & 0xFFFF)	/* Revison field */
1222 
1223 #define pvr_version_is(pvr)	(PVR_VER(mfspr(SPRN_PVR)) == (pvr))
1224 
1225 /*
1226  * IBM has further subdivided the standard PowerPC 16-bit version and
1227  * revision subfields of the PVR for the PowerPC 403s into the following:
1228  */
1229 
1230 #define PVR_FAM(pvr)	(((pvr) >> 20) & 0xFFF)	/* Family field */
1231 #define PVR_MEM(pvr)	(((pvr) >> 16) & 0xF)	/* Member field */
1232 #define PVR_CORE(pvr)	(((pvr) >> 12) & 0xF)	/* Core field */
1233 #define PVR_CFG(pvr)	(((pvr) >>  8) & 0xF)	/* Configuration field */
1234 #define PVR_MAJ(pvr)	(((pvr) >>  4) & 0xF)	/* Major revision field */
1235 #define PVR_MIN(pvr)	(((pvr) >>  0) & 0xF)	/* Minor revision field */
1236 
1237 /* Processor Version Numbers */
1238 
1239 #define PVR_403GA	0x00200000
1240 #define PVR_403GB	0x00200100
1241 #define PVR_403GC	0x00200200
1242 #define PVR_403GCX	0x00201400
1243 #define PVR_405GP	0x40110000
1244 #define PVR_476		0x11a52000
1245 #define PVR_476FPE	0x7ff50000
1246 #define PVR_STB03XXX	0x40310000
1247 #define PVR_NP405H	0x41410000
1248 #define PVR_NP405L	0x41610000
1249 #define PVR_601		0x00010000
1250 #define PVR_602		0x00050000
1251 #define PVR_603		0x00030000
1252 #define PVR_603e	0x00060000
1253 #define PVR_603ev	0x00070000
1254 #define PVR_603r	0x00071000
1255 #define PVR_604		0x00040000
1256 #define PVR_604e	0x00090000
1257 #define PVR_604r	0x000A0000
1258 #define PVR_620		0x00140000
1259 #define PVR_740		0x00080000
1260 #define PVR_750		PVR_740
1261 #define PVR_740P	0x10080000
1262 #define PVR_750P	PVR_740P
1263 #define PVR_7400	0x000C0000
1264 #define PVR_7410	0x800C0000
1265 #define PVR_7450	0x80000000
1266 #define PVR_8540	0x80200000
1267 #define PVR_8560	0x80200000
1268 #define PVR_VER_E500V1	0x8020
1269 #define PVR_VER_E500V2	0x8021
1270 #define PVR_VER_E500MC	0x8023
1271 #define PVR_VER_E5500	0x8024
1272 #define PVR_VER_E6500	0x8040
1273 
1274 /*
1275  * For the 8xx processors, all of them report the same PVR family for
1276  * the PowerPC core. The various versions of these processors must be
1277  * differentiated by the version number in the Communication Processor
1278  * Module (CPM).
1279  */
1280 #define PVR_8xx		0x00500000
1281 
1282 #define PVR_8240	0x00810100
1283 #define PVR_8245	0x80811014
1284 #define PVR_8260	PVR_8240
1285 
1286 /* 476 Simulator seems to currently have the PVR of the 602... */
1287 #define PVR_476_ISS	0x00052000
1288 
1289 /* 64-bit processors */
1290 #define PVR_NORTHSTAR	0x0033
1291 #define PVR_PULSAR	0x0034
1292 #define PVR_POWER4	0x0035
1293 #define PVR_ICESTAR	0x0036
1294 #define PVR_SSTAR	0x0037
1295 #define PVR_POWER4p	0x0038
1296 #define PVR_970		0x0039
1297 #define PVR_POWER5	0x003A
1298 #define PVR_POWER5p	0x003B
1299 #define PVR_970FX	0x003C
1300 #define PVR_POWER6	0x003E
1301 #define PVR_POWER7	0x003F
1302 #define PVR_630		0x0040
1303 #define PVR_630p	0x0041
1304 #define PVR_970MP	0x0044
1305 #define PVR_970GX	0x0045
1306 #define PVR_POWER7p	0x004A
1307 #define PVR_POWER8E	0x004B
1308 #define PVR_POWER8NVL	0x004C
1309 #define PVR_POWER8	0x004D
1310 #define PVR_POWER9	0x004E
1311 #define PVR_BE		0x0070
1312 #define PVR_PA6T	0x0090
1313 
1314 /* "Logical" PVR values defined in PAPR, representing architecture levels */
1315 #define PVR_ARCH_204	0x0f000001
1316 #define PVR_ARCH_205	0x0f000002
1317 #define PVR_ARCH_206	0x0f000003
1318 #define PVR_ARCH_206p	0x0f100003
1319 #define PVR_ARCH_207	0x0f000004
1320 #define PVR_ARCH_300	0x0f000005
1321 
1322 /* Macros for setting and retrieving special purpose registers */
1323 #ifndef __ASSEMBLY__
1324 #define mfmsr()		({unsigned long rval; \
1325 			asm volatile("mfmsr %0" : "=r" (rval) : \
1326 						: "memory"); rval;})
1327 #ifdef CONFIG_PPC_BOOK3S_64
1328 #define __mtmsrd(v, l)	asm volatile("mtmsrd %0," __stringify(l) \
1329 				     : : "r" (v) : "memory")
1330 #define mtmsr(v)	__mtmsrd((v), 0)
1331 #define __MTMSR		"mtmsrd"
1332 #else
1333 #define mtmsr(v)	asm volatile("mtmsr %0" : \
1334 				     : "r" ((unsigned long)(v)) \
1335 				     : "memory")
1336 #define __MTMSR		"mtmsr"
1337 #endif
1338 
1339 static inline void mtmsr_isync(unsigned long val)
1340 {
1341 	asm volatile(__MTMSR " %0; " ASM_FTR_IFCLR("isync", "nop", %1) : :
1342 			"r" (val), "i" (CPU_FTR_ARCH_206) : "memory");
1343 }
1344 
1345 #define mfspr(rn)	({unsigned long rval; \
1346 			asm volatile("mfspr %0," __stringify(rn) \
1347 				: "=r" (rval)); rval;})
1348 #ifndef mtspr
1349 #define mtspr(rn, v)	asm volatile("mtspr " __stringify(rn) ",%0" : \
1350 				     : "r" ((unsigned long)(v)) \
1351 				     : "memory")
1352 #endif
1353 #define wrtspr(rn)	asm volatile("mtspr " __stringify(rn) ",0" : \
1354 				     : : "memory")
1355 
1356 extern unsigned long msr_check_and_set(unsigned long bits);
1357 extern bool strict_msr_control;
1358 extern void __msr_check_and_clear(unsigned long bits);
1359 static inline void msr_check_and_clear(unsigned long bits)
1360 {
1361 	if (strict_msr_control)
1362 		__msr_check_and_clear(bits);
1363 }
1364 
1365 #ifdef __powerpc64__
1366 #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
1367 #define mftb()		({unsigned long rval;				\
1368 			asm volatile(					\
1369 				"90:	mfspr %0, %2;\n"		\
1370 				"97:	cmpwi %0,0;\n"			\
1371 				"	beq- 90b;\n"			\
1372 				"99:\n"					\
1373 				".section __ftr_fixup,\"a\"\n"		\
1374 				".align 3\n"				\
1375 				"98:\n"					\
1376 				"	.8byte %1\n"			\
1377 				"	.8byte %1\n"			\
1378 				"	.8byte 97b-98b\n"		\
1379 				"	.8byte 99b-98b\n"		\
1380 				"	.8byte 0\n"			\
1381 				"	.8byte 0\n"			\
1382 				".previous"				\
1383 			: "=r" (rval) \
1384 			: "i" (CPU_FTR_CELL_TB_BUG), "i" (SPRN_TBRL) : "cr0"); \
1385 			rval;})
1386 #else
1387 #define mftb()		({unsigned long rval;	\
1388 			asm volatile("mfspr %0, %1" : \
1389 				     "=r" (rval) : "i" (SPRN_TBRL)); rval;})
1390 #endif /* !CONFIG_PPC_CELL */
1391 
1392 #else /* __powerpc64__ */
1393 
1394 #if defined(CONFIG_PPC_8xx)
1395 #define mftbl()		({unsigned long rval;	\
1396 			asm volatile("mftbl %0" : "=r" (rval)); rval;})
1397 #define mftbu()		({unsigned long rval;	\
1398 			asm volatile("mftbu %0" : "=r" (rval)); rval;})
1399 #else
1400 #define mftbl()		({unsigned long rval;	\
1401 			asm volatile("mfspr %0, %1" : "=r" (rval) : \
1402 				"i" (SPRN_TBRL)); rval;})
1403 #define mftbu()		({unsigned long rval;	\
1404 			asm volatile("mfspr %0, %1" : "=r" (rval) : \
1405 				"i" (SPRN_TBRU)); rval;})
1406 #endif
1407 #define mftb()		mftbl()
1408 #endif /* !__powerpc64__ */
1409 
1410 #define mttbl(v)	asm volatile("mttbl %0":: "r"(v))
1411 #define mttbu(v)	asm volatile("mttbu %0":: "r"(v))
1412 
1413 #ifdef CONFIG_PPC32
1414 #define mfsrin(v)	({unsigned int rval; \
1415 			asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \
1416 					rval;})
1417 #endif
1418 
1419 #define proc_trap()	asm volatile("trap")
1420 
1421 extern unsigned long current_stack_pointer(void);
1422 
1423 extern unsigned long scom970_read(unsigned int address);
1424 extern void scom970_write(unsigned int address, unsigned long value);
1425 
1426 struct pt_regs;
1427 
1428 extern void ppc_save_regs(struct pt_regs *regs);
1429 
1430 static inline void update_power8_hid0(unsigned long hid0)
1431 {
1432 	/*
1433 	 *  The HID0 update on Power8 should at the very least be
1434 	 *  preceded by a a SYNC instruction followed by an ISYNC
1435 	 *  instruction
1436 	 */
1437 	asm volatile("sync; mtspr %0,%1; isync":: "i"(SPRN_HID0), "r"(hid0));
1438 }
1439 #endif /* __ASSEMBLY__ */
1440 #endif /* __KERNEL__ */
1441 #endif /* _ASM_POWERPC_REG_H */
1442