1 #ifndef _ASM_POWERPC_PROCESSOR_H 2 #define _ASM_POWERPC_PROCESSOR_H 3 4 /* 5 * Copyright (C) 2001 PPC 64 Team, IBM Corp 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13 #include <asm/reg.h> 14 15 #ifdef CONFIG_VSX 16 #define TS_FPRWIDTH 2 17 #else 18 #define TS_FPRWIDTH 1 19 #endif 20 21 #ifdef CONFIG_PPC64 22 /* Default SMT priority is set to 3. Use 11- 13bits to save priority. */ 23 #define PPR_PRIORITY 3 24 #ifdef __ASSEMBLY__ 25 #define INIT_PPR (PPR_PRIORITY << 50) 26 #else 27 #define INIT_PPR ((u64)PPR_PRIORITY << 50) 28 #endif /* __ASSEMBLY__ */ 29 #endif /* CONFIG_PPC64 */ 30 31 #ifndef __ASSEMBLY__ 32 #include <linux/compiler.h> 33 #include <linux/cache.h> 34 #include <asm/ptrace.h> 35 #include <asm/types.h> 36 #include <asm/hw_breakpoint.h> 37 38 /* We do _not_ want to define new machine types at all, those must die 39 * in favor of using the device-tree 40 * -- BenH. 41 */ 42 43 /* PREP sub-platform types. Unused */ 44 #define _PREP_Motorola 0x01 /* motorola prep */ 45 #define _PREP_Firm 0x02 /* firmworks prep */ 46 #define _PREP_IBM 0x00 /* ibm prep */ 47 #define _PREP_Bull 0x03 /* bull prep */ 48 49 /* CHRP sub-platform types. These are arbitrary */ 50 #define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */ 51 #define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */ 52 #define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */ 53 #define _CHRP_briq 0x07 /* TotalImpact's briQ */ 54 55 #if defined(__KERNEL__) && defined(CONFIG_PPC32) 56 57 extern int _chrp_type; 58 59 #endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */ 60 61 /* 62 * Default implementation of macro that returns current 63 * instruction pointer ("program counter"). 64 */ 65 #define current_text_addr() ({ __label__ _l; _l: &&_l;}) 66 67 /* Macros for adjusting thread priority (hardware multi-threading) */ 68 #define HMT_very_low() asm volatile("or 31,31,31 # very low priority") 69 #define HMT_low() asm volatile("or 1,1,1 # low priority") 70 #define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority") 71 #define HMT_medium() asm volatile("or 2,2,2 # medium priority") 72 #define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority") 73 #define HMT_high() asm volatile("or 3,3,3 # high priority") 74 75 #ifdef __KERNEL__ 76 77 struct task_struct; 78 void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp); 79 void release_thread(struct task_struct *); 80 81 /* Lazy FPU handling on uni-processor */ 82 extern struct task_struct *last_task_used_math; 83 extern struct task_struct *last_task_used_altivec; 84 extern struct task_struct *last_task_used_vsx; 85 extern struct task_struct *last_task_used_spe; 86 87 #ifdef CONFIG_PPC32 88 89 #if CONFIG_TASK_SIZE > CONFIG_KERNEL_START 90 #error User TASK_SIZE overlaps with KERNEL_START address 91 #endif 92 #define TASK_SIZE (CONFIG_TASK_SIZE) 93 94 /* This decides where the kernel will search for a free chunk of vm 95 * space during mmap's. 96 */ 97 #define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3) 98 #endif 99 100 #ifdef CONFIG_PPC64 101 /* 64-bit user address space is 46-bits (64TB user VM) */ 102 #define TASK_SIZE_USER64 (0x0000400000000000UL) 103 104 /* 105 * 32-bit user address space is 4GB - 1 page 106 * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT 107 */ 108 #define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE)) 109 110 #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \ 111 TASK_SIZE_USER32 : TASK_SIZE_USER64) 112 #define TASK_SIZE TASK_SIZE_OF(current) 113 114 /* This decides where the kernel will search for a free chunk of vm 115 * space during mmap's. 116 */ 117 #define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4)) 118 #define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4)) 119 120 #define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \ 121 TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 ) 122 #endif 123 124 #ifdef __powerpc64__ 125 126 #define STACK_TOP_USER64 TASK_SIZE_USER64 127 #define STACK_TOP_USER32 TASK_SIZE_USER32 128 129 #define STACK_TOP (is_32bit_task() ? \ 130 STACK_TOP_USER32 : STACK_TOP_USER64) 131 132 #define STACK_TOP_MAX STACK_TOP_USER64 133 134 #else /* __powerpc64__ */ 135 136 #define STACK_TOP TASK_SIZE 137 #define STACK_TOP_MAX STACK_TOP 138 139 #endif /* __powerpc64__ */ 140 141 typedef struct { 142 unsigned long seg; 143 } mm_segment_t; 144 145 #define TS_FPROFFSET 0 146 #define TS_VSRLOWOFFSET 1 147 #define TS_FPR(i) fpr[i][TS_FPROFFSET] 148 #define TS_TRANS_FPR(i) transact_fpr[i][TS_FPROFFSET] 149 150 struct thread_struct { 151 unsigned long ksp; /* Kernel stack pointer */ 152 unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */ 153 154 #ifdef CONFIG_PPC64 155 unsigned long ksp_vsid; 156 #endif 157 struct pt_regs *regs; /* Pointer to saved register state */ 158 mm_segment_t fs; /* for get_fs() validation */ 159 #ifdef CONFIG_BOOKE 160 /* BookE base exception scratch space; align on cacheline */ 161 unsigned long normsave[8] ____cacheline_aligned; 162 #endif 163 #ifdef CONFIG_PPC32 164 void *pgdir; /* root of page-table tree */ 165 #endif 166 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 167 /* 168 * The following help to manage the use of Debug Control Registers 169 * om the BookE platforms. 170 */ 171 unsigned long dbcr0; 172 unsigned long dbcr1; 173 #ifdef CONFIG_BOOKE 174 unsigned long dbcr2; 175 #endif 176 /* 177 * The stored value of the DBSR register will be the value at the 178 * last debug interrupt. This register can only be read from the 179 * user (will never be written to) and has value while helping to 180 * describe the reason for the last debug trap. Torez 181 */ 182 unsigned long dbsr; 183 /* 184 * The following will contain addresses used by debug applications 185 * to help trace and trap on particular address locations. 186 * The bits in the Debug Control Registers above help define which 187 * of the following registers will contain valid data and/or addresses. 188 */ 189 unsigned long iac1; 190 unsigned long iac2; 191 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 192 unsigned long iac3; 193 unsigned long iac4; 194 #endif 195 unsigned long dac1; 196 unsigned long dac2; 197 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 198 unsigned long dvc1; 199 unsigned long dvc2; 200 #endif 201 #endif 202 /* FP and VSX 0-31 register set */ 203 double fpr[32][TS_FPRWIDTH]; 204 struct { 205 206 unsigned int pad; 207 unsigned int val; /* Floating point status */ 208 } fpscr; 209 int fpexc_mode; /* floating-point exception mode */ 210 unsigned int align_ctl; /* alignment handling control */ 211 #ifdef CONFIG_PPC64 212 unsigned long start_tb; /* Start purr when proc switched in */ 213 unsigned long accum_tb; /* Total accumilated purr for process */ 214 #ifdef CONFIG_HAVE_HW_BREAKPOINT 215 struct perf_event *ptrace_bps[HBP_NUM]; 216 /* 217 * Helps identify source of single-step exception and subsequent 218 * hw-breakpoint enablement 219 */ 220 struct perf_event *last_hit_ubp; 221 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 222 #endif 223 struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */ 224 unsigned long trap_nr; /* last trap # on this thread */ 225 #ifdef CONFIG_ALTIVEC 226 /* Complete AltiVec register set */ 227 vector128 vr[32] __attribute__((aligned(16))); 228 /* AltiVec status */ 229 vector128 vscr __attribute__((aligned(16))); 230 unsigned long vrsave; 231 int used_vr; /* set if process has used altivec */ 232 #endif /* CONFIG_ALTIVEC */ 233 #ifdef CONFIG_VSX 234 /* VSR status */ 235 int used_vsr; /* set if process has used altivec */ 236 #endif /* CONFIG_VSX */ 237 #ifdef CONFIG_SPE 238 unsigned long evr[32]; /* upper 32-bits of SPE regs */ 239 u64 acc; /* Accumulator */ 240 unsigned long spefscr; /* SPE & eFP status */ 241 int used_spe; /* set if process has used spe */ 242 #endif /* CONFIG_SPE */ 243 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 244 u64 tm_tfhar; /* Transaction fail handler addr */ 245 u64 tm_texasr; /* Transaction exception & summary */ 246 u64 tm_tfiar; /* Transaction fail instr address reg */ 247 unsigned long tm_orig_msr; /* Thread's MSR on ctx switch */ 248 struct pt_regs ckpt_regs; /* Checkpointed registers */ 249 250 /* 251 * Transactional FP and VSX 0-31 register set. 252 * NOTE: the sense of these is the opposite of the integer ckpt_regs! 253 * 254 * When a transaction is active/signalled/scheduled etc., *regs is the 255 * most recent set of/speculated GPRs with ckpt_regs being the older 256 * checkpointed regs to which we roll back if transaction aborts. 257 * 258 * However, fpr[] is the checkpointed 'base state' of FP regs, and 259 * transact_fpr[] is the new set of transactional values. 260 * VRs work the same way. 261 */ 262 double transact_fpr[32][TS_FPRWIDTH]; 263 struct { 264 unsigned int pad; 265 unsigned int val; /* Floating point status */ 266 } transact_fpscr; 267 vector128 transact_vr[32] __attribute__((aligned(16))); 268 vector128 transact_vscr __attribute__((aligned(16))); 269 unsigned long transact_vrsave; 270 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 271 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER 272 void* kvm_shadow_vcpu; /* KVM internal data */ 273 #endif /* CONFIG_KVM_BOOK3S_32_HANDLER */ 274 #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE) 275 struct kvm_vcpu *kvm_vcpu; 276 #endif 277 #ifdef CONFIG_PPC64 278 unsigned long dscr; 279 int dscr_inherit; 280 unsigned long ppr; /* used to save/restore SMT priority */ 281 #endif 282 #ifdef CONFIG_PPC_BOOK3S_64 283 unsigned long tar; 284 unsigned long ebbrr; 285 unsigned long ebbhr; 286 unsigned long bescr; 287 #endif 288 }; 289 290 #define ARCH_MIN_TASKALIGN 16 291 292 #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) 293 #define INIT_SP_LIMIT \ 294 (_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack) 295 296 #ifdef CONFIG_SPE 297 #define SPEFSCR_INIT .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, 298 #else 299 #define SPEFSCR_INIT 300 #endif 301 302 #ifdef CONFIG_PPC32 303 #define INIT_THREAD { \ 304 .ksp = INIT_SP, \ 305 .ksp_limit = INIT_SP_LIMIT, \ 306 .fs = KERNEL_DS, \ 307 .pgdir = swapper_pg_dir, \ 308 .fpexc_mode = MSR_FE0 | MSR_FE1, \ 309 SPEFSCR_INIT \ 310 } 311 #else 312 #define INIT_THREAD { \ 313 .ksp = INIT_SP, \ 314 .ksp_limit = INIT_SP_LIMIT, \ 315 .regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \ 316 .fs = KERNEL_DS, \ 317 .fpr = {{0}}, \ 318 .fpscr = { .val = 0, }, \ 319 .fpexc_mode = 0, \ 320 .ppr = INIT_PPR, \ 321 } 322 #endif 323 324 /* 325 * Return saved PC of a blocked thread. For now, this is the "user" PC 326 */ 327 #define thread_saved_pc(tsk) \ 328 ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0) 329 330 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.regs) 331 332 unsigned long get_wchan(struct task_struct *p); 333 334 #define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0) 335 #define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0) 336 337 /* Get/set floating-point exception mode */ 338 #define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr)) 339 #define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val)) 340 341 extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr); 342 extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val); 343 344 #define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr)) 345 #define SET_ENDIAN(tsk, val) set_endian((tsk), (val)) 346 347 extern int get_endian(struct task_struct *tsk, unsigned long adr); 348 extern int set_endian(struct task_struct *tsk, unsigned int val); 349 350 #define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr)) 351 #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) 352 353 extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr); 354 extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val); 355 356 static inline unsigned int __unpack_fe01(unsigned long msr_bits) 357 { 358 return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8); 359 } 360 361 static inline unsigned long __pack_fe01(unsigned int fpmode) 362 { 363 return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1); 364 } 365 366 #ifdef CONFIG_PPC64 367 #define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0) 368 #else 369 #define cpu_relax() barrier() 370 #endif 371 372 /* Check that a certain kernel stack pointer is valid in task_struct p */ 373 int validate_sp(unsigned long sp, struct task_struct *p, 374 unsigned long nbytes); 375 376 /* 377 * Prefetch macros. 378 */ 379 #define ARCH_HAS_PREFETCH 380 #define ARCH_HAS_PREFETCHW 381 #define ARCH_HAS_SPINLOCK_PREFETCH 382 383 static inline void prefetch(const void *x) 384 { 385 if (unlikely(!x)) 386 return; 387 388 __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x)); 389 } 390 391 static inline void prefetchw(const void *x) 392 { 393 if (unlikely(!x)) 394 return; 395 396 __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x)); 397 } 398 399 #define spin_lock_prefetch(x) prefetchw(x) 400 401 #ifdef CONFIG_PPC64 402 #define HAVE_ARCH_PICK_MMAP_LAYOUT 403 #endif 404 405 #ifdef CONFIG_PPC64 406 static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32) 407 { 408 unsigned long sp; 409 410 if (is_32) 411 sp = regs->gpr[1] & 0x0ffffffffUL; 412 else 413 sp = regs->gpr[1]; 414 415 return sp; 416 } 417 #else 418 static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32) 419 { 420 return regs->gpr[1]; 421 } 422 #endif 423 424 extern unsigned long cpuidle_disable; 425 enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF}; 426 427 extern int powersave_nap; /* set if nap mode can be used in idle loop */ 428 extern void power7_nap(void); 429 430 #ifdef CONFIG_PSERIES_IDLE 431 extern void update_smt_snooze_delay(int cpu, int residency); 432 #else 433 static inline void update_smt_snooze_delay(int cpu, int residency) {} 434 #endif 435 436 extern void flush_instruction_cache(void); 437 extern void hard_reset_now(void); 438 extern void poweroff_now(void); 439 extern int fix_alignment(struct pt_regs *); 440 extern void cvt_fd(float *from, double *to); 441 extern void cvt_df(double *from, float *to); 442 extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); 443 444 #ifdef CONFIG_PPC64 445 /* 446 * We handle most unaligned accesses in hardware. On the other hand 447 * unaligned DMA can be very expensive on some ppc64 IO chips (it does 448 * powers of 2 writes until it reaches sufficient alignment). 449 * 450 * Based on this we disable the IP header alignment in network drivers. 451 */ 452 #define NET_IP_ALIGN 0 453 #endif 454 455 #endif /* __KERNEL__ */ 456 #endif /* __ASSEMBLY__ */ 457 #endif /* _ASM_POWERPC_PROCESSOR_H */ 458