1 #ifndef _ASM_POWERPC_PROCESSOR_H 2 #define _ASM_POWERPC_PROCESSOR_H 3 4 /* 5 * Copyright (C) 2001 PPC 64 Team, IBM Corp 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13 #include <asm/reg.h> 14 15 #ifdef CONFIG_VSX 16 #define TS_FPRWIDTH 2 17 18 #ifdef __BIG_ENDIAN__ 19 #define TS_FPROFFSET 0 20 #define TS_VSRLOWOFFSET 1 21 #else 22 #define TS_FPROFFSET 1 23 #define TS_VSRLOWOFFSET 0 24 #endif 25 26 #else 27 #define TS_FPRWIDTH 1 28 #define TS_FPROFFSET 0 29 #endif 30 31 #ifdef CONFIG_PPC64 32 /* Default SMT priority is set to 3. Use 11- 13bits to save priority. */ 33 #define PPR_PRIORITY 3 34 #ifdef __ASSEMBLY__ 35 #define INIT_PPR (PPR_PRIORITY << 50) 36 #else 37 #define INIT_PPR ((u64)PPR_PRIORITY << 50) 38 #endif /* __ASSEMBLY__ */ 39 #endif /* CONFIG_PPC64 */ 40 41 #ifndef __ASSEMBLY__ 42 #include <linux/compiler.h> 43 #include <linux/cache.h> 44 #include <asm/ptrace.h> 45 #include <asm/types.h> 46 #include <asm/hw_breakpoint.h> 47 48 /* We do _not_ want to define new machine types at all, those must die 49 * in favor of using the device-tree 50 * -- BenH. 51 */ 52 53 /* PREP sub-platform types. Unused */ 54 #define _PREP_Motorola 0x01 /* motorola prep */ 55 #define _PREP_Firm 0x02 /* firmworks prep */ 56 #define _PREP_IBM 0x00 /* ibm prep */ 57 #define _PREP_Bull 0x03 /* bull prep */ 58 59 /* CHRP sub-platform types. These are arbitrary */ 60 #define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */ 61 #define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */ 62 #define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */ 63 #define _CHRP_briq 0x07 /* TotalImpact's briQ */ 64 65 #if defined(__KERNEL__) && defined(CONFIG_PPC32) 66 67 extern int _chrp_type; 68 69 #endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */ 70 71 /* 72 * Default implementation of macro that returns current 73 * instruction pointer ("program counter"). 74 */ 75 #define current_text_addr() ({ __label__ _l; _l: &&_l;}) 76 77 /* Macros for adjusting thread priority (hardware multi-threading) */ 78 #define HMT_very_low() asm volatile("or 31,31,31 # very low priority") 79 #define HMT_low() asm volatile("or 1,1,1 # low priority") 80 #define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority") 81 #define HMT_medium() asm volatile("or 2,2,2 # medium priority") 82 #define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority") 83 #define HMT_high() asm volatile("or 3,3,3 # high priority") 84 85 #ifdef __KERNEL__ 86 87 struct task_struct; 88 void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp); 89 void release_thread(struct task_struct *); 90 91 /* Lazy FPU handling on uni-processor */ 92 extern struct task_struct *last_task_used_math; 93 extern struct task_struct *last_task_used_altivec; 94 extern struct task_struct *last_task_used_vsx; 95 extern struct task_struct *last_task_used_spe; 96 97 #ifdef CONFIG_PPC32 98 99 #if CONFIG_TASK_SIZE > CONFIG_KERNEL_START 100 #error User TASK_SIZE overlaps with KERNEL_START address 101 #endif 102 #define TASK_SIZE (CONFIG_TASK_SIZE) 103 104 /* This decides where the kernel will search for a free chunk of vm 105 * space during mmap's. 106 */ 107 #define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3) 108 #endif 109 110 #ifdef CONFIG_PPC64 111 /* 64-bit user address space is 46-bits (64TB user VM) */ 112 #define TASK_SIZE_USER64 (0x0000400000000000UL) 113 114 /* 115 * 32-bit user address space is 4GB - 1 page 116 * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT 117 */ 118 #define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE)) 119 120 #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \ 121 TASK_SIZE_USER32 : TASK_SIZE_USER64) 122 #define TASK_SIZE TASK_SIZE_OF(current) 123 124 /* This decides where the kernel will search for a free chunk of vm 125 * space during mmap's. 126 */ 127 #define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4)) 128 #define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4)) 129 130 #define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \ 131 TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 ) 132 #endif 133 134 #ifdef __powerpc64__ 135 136 #define STACK_TOP_USER64 TASK_SIZE_USER64 137 #define STACK_TOP_USER32 TASK_SIZE_USER32 138 139 #define STACK_TOP (is_32bit_task() ? \ 140 STACK_TOP_USER32 : STACK_TOP_USER64) 141 142 #define STACK_TOP_MAX STACK_TOP_USER64 143 144 #else /* __powerpc64__ */ 145 146 #define STACK_TOP TASK_SIZE 147 #define STACK_TOP_MAX STACK_TOP 148 149 #endif /* __powerpc64__ */ 150 151 typedef struct { 152 unsigned long seg; 153 } mm_segment_t; 154 155 #define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET] 156 #define TS_TRANS_FPR(i) transact_fp.fpr[i][TS_FPROFFSET] 157 158 /* FP and VSX 0-31 register set */ 159 struct thread_fp_state { 160 u64 fpr[32][TS_FPRWIDTH] __attribute__((aligned(16))); 161 u64 fpscr; /* Floating point status */ 162 }; 163 164 /* Complete AltiVec register set including VSCR */ 165 struct thread_vr_state { 166 vector128 vr[32] __attribute__((aligned(16))); 167 vector128 vscr __attribute__((aligned(16))); 168 }; 169 170 struct debug_reg { 171 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 172 /* 173 * The following help to manage the use of Debug Control Registers 174 * om the BookE platforms. 175 */ 176 uint32_t dbcr0; 177 uint32_t dbcr1; 178 #ifdef CONFIG_BOOKE 179 uint32_t dbcr2; 180 #endif 181 /* 182 * The stored value of the DBSR register will be the value at the 183 * last debug interrupt. This register can only be read from the 184 * user (will never be written to) and has value while helping to 185 * describe the reason for the last debug trap. Torez 186 */ 187 uint32_t dbsr; 188 /* 189 * The following will contain addresses used by debug applications 190 * to help trace and trap on particular address locations. 191 * The bits in the Debug Control Registers above help define which 192 * of the following registers will contain valid data and/or addresses. 193 */ 194 unsigned long iac1; 195 unsigned long iac2; 196 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 197 unsigned long iac3; 198 unsigned long iac4; 199 #endif 200 unsigned long dac1; 201 unsigned long dac2; 202 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 203 unsigned long dvc1; 204 unsigned long dvc2; 205 #endif 206 #endif 207 }; 208 209 struct thread_struct { 210 unsigned long ksp; /* Kernel stack pointer */ 211 212 #ifdef CONFIG_PPC64 213 unsigned long ksp_vsid; 214 #endif 215 struct pt_regs *regs; /* Pointer to saved register state */ 216 mm_segment_t fs; /* for get_fs() validation */ 217 #ifdef CONFIG_BOOKE 218 /* BookE base exception scratch space; align on cacheline */ 219 unsigned long normsave[8] ____cacheline_aligned; 220 #endif 221 #ifdef CONFIG_PPC32 222 void *pgdir; /* root of page-table tree */ 223 unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */ 224 #endif 225 /* Debug Registers */ 226 struct debug_reg debug; 227 struct thread_fp_state fp_state; 228 struct thread_fp_state *fp_save_area; 229 int fpexc_mode; /* floating-point exception mode */ 230 unsigned int align_ctl; /* alignment handling control */ 231 #ifdef CONFIG_PPC64 232 unsigned long start_tb; /* Start purr when proc switched in */ 233 unsigned long accum_tb; /* Total accumilated purr for process */ 234 #ifdef CONFIG_HAVE_HW_BREAKPOINT 235 struct perf_event *ptrace_bps[HBP_NUM]; 236 /* 237 * Helps identify source of single-step exception and subsequent 238 * hw-breakpoint enablement 239 */ 240 struct perf_event *last_hit_ubp; 241 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 242 #endif 243 struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */ 244 unsigned long trap_nr; /* last trap # on this thread */ 245 #ifdef CONFIG_ALTIVEC 246 struct thread_vr_state vr_state; 247 struct thread_vr_state *vr_save_area; 248 unsigned long vrsave; 249 int used_vr; /* set if process has used altivec */ 250 #endif /* CONFIG_ALTIVEC */ 251 #ifdef CONFIG_VSX 252 /* VSR status */ 253 int used_vsr; /* set if process has used altivec */ 254 #endif /* CONFIG_VSX */ 255 #ifdef CONFIG_SPE 256 unsigned long evr[32]; /* upper 32-bits of SPE regs */ 257 u64 acc; /* Accumulator */ 258 unsigned long spefscr; /* SPE & eFP status */ 259 unsigned long spefscr_last; /* SPEFSCR value on last prctl 260 call or trap return */ 261 int used_spe; /* set if process has used spe */ 262 #endif /* CONFIG_SPE */ 263 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 264 u64 tm_tfhar; /* Transaction fail handler addr */ 265 u64 tm_texasr; /* Transaction exception & summary */ 266 u64 tm_tfiar; /* Transaction fail instr address reg */ 267 unsigned long tm_orig_msr; /* Thread's MSR on ctx switch */ 268 struct pt_regs ckpt_regs; /* Checkpointed registers */ 269 270 unsigned long tm_tar; 271 unsigned long tm_ppr; 272 unsigned long tm_dscr; 273 274 /* 275 * Transactional FP and VSX 0-31 register set. 276 * NOTE: the sense of these is the opposite of the integer ckpt_regs! 277 * 278 * When a transaction is active/signalled/scheduled etc., *regs is the 279 * most recent set of/speculated GPRs with ckpt_regs being the older 280 * checkpointed regs to which we roll back if transaction aborts. 281 * 282 * However, fpr[] is the checkpointed 'base state' of FP regs, and 283 * transact_fpr[] is the new set of transactional values. 284 * VRs work the same way. 285 */ 286 struct thread_fp_state transact_fp; 287 struct thread_vr_state transact_vr; 288 unsigned long transact_vrsave; 289 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 290 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER 291 void* kvm_shadow_vcpu; /* KVM internal data */ 292 #endif /* CONFIG_KVM_BOOK3S_32_HANDLER */ 293 #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE) 294 struct kvm_vcpu *kvm_vcpu; 295 #endif 296 #ifdef CONFIG_PPC64 297 unsigned long dscr; 298 /* 299 * This member element dscr_inherit indicates that the process 300 * has explicitly attempted and changed the DSCR register value 301 * for itself. Hence kernel wont use the default CPU DSCR value 302 * contained in the PACA structure anymore during process context 303 * switch. Once this variable is set, this behaviour will also be 304 * inherited to all the children of this process from that point 305 * onwards. 306 */ 307 int dscr_inherit; 308 unsigned long ppr; /* used to save/restore SMT priority */ 309 #endif 310 #ifdef CONFIG_PPC_BOOK3S_64 311 unsigned long tar; 312 unsigned long ebbrr; 313 unsigned long ebbhr; 314 unsigned long bescr; 315 unsigned long siar; 316 unsigned long sdar; 317 unsigned long sier; 318 unsigned long mmcr2; 319 unsigned mmcr0; 320 unsigned used_ebb; 321 #endif 322 }; 323 324 #define ARCH_MIN_TASKALIGN 16 325 326 #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) 327 #define INIT_SP_LIMIT \ 328 (_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack) 329 330 #ifdef CONFIG_SPE 331 #define SPEFSCR_INIT \ 332 .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \ 333 .spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, 334 #else 335 #define SPEFSCR_INIT 336 #endif 337 338 #ifdef CONFIG_PPC32 339 #define INIT_THREAD { \ 340 .ksp = INIT_SP, \ 341 .ksp_limit = INIT_SP_LIMIT, \ 342 .fs = KERNEL_DS, \ 343 .pgdir = swapper_pg_dir, \ 344 .fpexc_mode = MSR_FE0 | MSR_FE1, \ 345 SPEFSCR_INIT \ 346 } 347 #else 348 #define INIT_THREAD { \ 349 .ksp = INIT_SP, \ 350 .regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \ 351 .fs = KERNEL_DS, \ 352 .fpexc_mode = 0, \ 353 .ppr = INIT_PPR, \ 354 } 355 #endif 356 357 /* 358 * Return saved PC of a blocked thread. For now, this is the "user" PC 359 */ 360 #define thread_saved_pc(tsk) \ 361 ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0) 362 363 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.regs) 364 365 unsigned long get_wchan(struct task_struct *p); 366 367 #define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0) 368 #define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0) 369 370 /* Get/set floating-point exception mode */ 371 #define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr)) 372 #define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val)) 373 374 extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr); 375 extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val); 376 377 #define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr)) 378 #define SET_ENDIAN(tsk, val) set_endian((tsk), (val)) 379 380 extern int get_endian(struct task_struct *tsk, unsigned long adr); 381 extern int set_endian(struct task_struct *tsk, unsigned int val); 382 383 #define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr)) 384 #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) 385 386 extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr); 387 extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val); 388 389 extern void fp_enable(void); 390 extern void vec_enable(void); 391 extern void load_fp_state(struct thread_fp_state *fp); 392 extern void store_fp_state(struct thread_fp_state *fp); 393 extern void load_vr_state(struct thread_vr_state *vr); 394 extern void store_vr_state(struct thread_vr_state *vr); 395 396 static inline unsigned int __unpack_fe01(unsigned long msr_bits) 397 { 398 return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8); 399 } 400 401 static inline unsigned long __pack_fe01(unsigned int fpmode) 402 { 403 return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1); 404 } 405 406 #ifdef CONFIG_PPC64 407 #define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0) 408 #else 409 #define cpu_relax() barrier() 410 #endif 411 412 #define cpu_relax_lowlatency() cpu_relax() 413 414 /* Check that a certain kernel stack pointer is valid in task_struct p */ 415 int validate_sp(unsigned long sp, struct task_struct *p, 416 unsigned long nbytes); 417 418 /* 419 * Prefetch macros. 420 */ 421 #define ARCH_HAS_PREFETCH 422 #define ARCH_HAS_PREFETCHW 423 #define ARCH_HAS_SPINLOCK_PREFETCH 424 425 static inline void prefetch(const void *x) 426 { 427 if (unlikely(!x)) 428 return; 429 430 __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x)); 431 } 432 433 static inline void prefetchw(const void *x) 434 { 435 if (unlikely(!x)) 436 return; 437 438 __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x)); 439 } 440 441 #define spin_lock_prefetch(x) prefetchw(x) 442 443 #define HAVE_ARCH_PICK_MMAP_LAYOUT 444 445 #ifdef CONFIG_PPC64 446 static inline unsigned long get_clean_sp(unsigned long sp, int is_32) 447 { 448 if (is_32) 449 return sp & 0x0ffffffffUL; 450 return sp; 451 } 452 #else 453 static inline unsigned long get_clean_sp(unsigned long sp, int is_32) 454 { 455 return sp; 456 } 457 #endif 458 459 extern unsigned long cpuidle_disable; 460 enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF}; 461 462 extern int powersave_nap; /* set if nap mode can be used in idle loop */ 463 extern unsigned long power7_nap(int check_irq); 464 extern unsigned long power7_sleep(void); 465 extern unsigned long power7_winkle(void); 466 extern void flush_instruction_cache(void); 467 extern void hard_reset_now(void); 468 extern void poweroff_now(void); 469 extern int fix_alignment(struct pt_regs *); 470 extern void cvt_fd(float *from, double *to); 471 extern void cvt_df(double *from, float *to); 472 extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); 473 474 #ifdef CONFIG_PPC64 475 /* 476 * We handle most unaligned accesses in hardware. On the other hand 477 * unaligned DMA can be very expensive on some ppc64 IO chips (it does 478 * powers of 2 writes until it reaches sufficient alignment). 479 * 480 * Based on this we disable the IP header alignment in network drivers. 481 */ 482 #define NET_IP_ALIGN 0 483 #endif 484 485 #endif /* __KERNEL__ */ 486 #endif /* __ASSEMBLY__ */ 487 #endif /* _ASM_POWERPC_PROCESSOR_H */ 488