1 #ifndef _ASM_POWERPC_PROCESSOR_H 2 #define _ASM_POWERPC_PROCESSOR_H 3 4 /* 5 * Copyright (C) 2001 PPC 64 Team, IBM Corp 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13 #include <asm/reg.h> 14 15 #ifdef CONFIG_VSX 16 #define TS_FPRWIDTH 2 17 18 #ifdef __BIG_ENDIAN__ 19 #define TS_FPROFFSET 0 20 #define TS_VSRLOWOFFSET 1 21 #else 22 #define TS_FPROFFSET 1 23 #define TS_VSRLOWOFFSET 0 24 #endif 25 26 #else 27 #define TS_FPRWIDTH 1 28 #define TS_FPROFFSET 0 29 #endif 30 31 #ifdef CONFIG_PPC64 32 /* Default SMT priority is set to 3. Use 11- 13bits to save priority. */ 33 #define PPR_PRIORITY 3 34 #ifdef __ASSEMBLY__ 35 #define INIT_PPR (PPR_PRIORITY << 50) 36 #else 37 #define INIT_PPR ((u64)PPR_PRIORITY << 50) 38 #endif /* __ASSEMBLY__ */ 39 #endif /* CONFIG_PPC64 */ 40 41 #ifndef __ASSEMBLY__ 42 #include <linux/compiler.h> 43 #include <linux/cache.h> 44 #include <asm/ptrace.h> 45 #include <asm/types.h> 46 #include <asm/hw_breakpoint.h> 47 48 /* We do _not_ want to define new machine types at all, those must die 49 * in favor of using the device-tree 50 * -- BenH. 51 */ 52 53 /* PREP sub-platform types. Unused */ 54 #define _PREP_Motorola 0x01 /* motorola prep */ 55 #define _PREP_Firm 0x02 /* firmworks prep */ 56 #define _PREP_IBM 0x00 /* ibm prep */ 57 #define _PREP_Bull 0x03 /* bull prep */ 58 59 /* CHRP sub-platform types. These are arbitrary */ 60 #define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */ 61 #define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */ 62 #define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */ 63 #define _CHRP_briq 0x07 /* TotalImpact's briQ */ 64 65 #if defined(__KERNEL__) && defined(CONFIG_PPC32) 66 67 extern int _chrp_type; 68 69 #endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */ 70 71 /* 72 * Default implementation of macro that returns current 73 * instruction pointer ("program counter"). 74 */ 75 #define current_text_addr() ({ __label__ _l; _l: &&_l;}) 76 77 /* Macros for adjusting thread priority (hardware multi-threading) */ 78 #define HMT_very_low() asm volatile("or 31,31,31 # very low priority") 79 #define HMT_low() asm volatile("or 1,1,1 # low priority") 80 #define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority") 81 #define HMT_medium() asm volatile("or 2,2,2 # medium priority") 82 #define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority") 83 #define HMT_high() asm volatile("or 3,3,3 # high priority") 84 85 #ifdef __KERNEL__ 86 87 struct task_struct; 88 void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp); 89 void release_thread(struct task_struct *); 90 91 #ifdef CONFIG_PPC32 92 93 #if CONFIG_TASK_SIZE > CONFIG_KERNEL_START 94 #error User TASK_SIZE overlaps with KERNEL_START address 95 #endif 96 #define TASK_SIZE (CONFIG_TASK_SIZE) 97 98 /* This decides where the kernel will search for a free chunk of vm 99 * space during mmap's. 100 */ 101 #define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3) 102 #endif 103 104 #ifdef CONFIG_PPC64 105 /* 64-bit user address space is 46-bits (64TB user VM) */ 106 #define TASK_SIZE_USER64 (0x0000400000000000UL) 107 108 /* 109 * 32-bit user address space is 4GB - 1 page 110 * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT 111 */ 112 #define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE)) 113 114 #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \ 115 TASK_SIZE_USER32 : TASK_SIZE_USER64) 116 #define TASK_SIZE TASK_SIZE_OF(current) 117 118 /* This decides where the kernel will search for a free chunk of vm 119 * space during mmap's. 120 */ 121 #define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4)) 122 #define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4)) 123 124 #define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \ 125 TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 ) 126 #endif 127 128 #ifdef __powerpc64__ 129 130 #define STACK_TOP_USER64 TASK_SIZE_USER64 131 #define STACK_TOP_USER32 TASK_SIZE_USER32 132 133 #define STACK_TOP (is_32bit_task() ? \ 134 STACK_TOP_USER32 : STACK_TOP_USER64) 135 136 #define STACK_TOP_MAX STACK_TOP_USER64 137 138 #else /* __powerpc64__ */ 139 140 #define STACK_TOP TASK_SIZE 141 #define STACK_TOP_MAX STACK_TOP 142 143 #endif /* __powerpc64__ */ 144 145 typedef struct { 146 unsigned long seg; 147 } mm_segment_t; 148 149 #define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET] 150 #define TS_TRANS_FPR(i) transact_fp.fpr[i][TS_FPROFFSET] 151 152 /* FP and VSX 0-31 register set */ 153 struct thread_fp_state { 154 u64 fpr[32][TS_FPRWIDTH] __attribute__((aligned(16))); 155 u64 fpscr; /* Floating point status */ 156 }; 157 158 /* Complete AltiVec register set including VSCR */ 159 struct thread_vr_state { 160 vector128 vr[32] __attribute__((aligned(16))); 161 vector128 vscr __attribute__((aligned(16))); 162 }; 163 164 struct debug_reg { 165 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 166 /* 167 * The following help to manage the use of Debug Control Registers 168 * om the BookE platforms. 169 */ 170 uint32_t dbcr0; 171 uint32_t dbcr1; 172 #ifdef CONFIG_BOOKE 173 uint32_t dbcr2; 174 #endif 175 /* 176 * The stored value of the DBSR register will be the value at the 177 * last debug interrupt. This register can only be read from the 178 * user (will never be written to) and has value while helping to 179 * describe the reason for the last debug trap. Torez 180 */ 181 uint32_t dbsr; 182 /* 183 * The following will contain addresses used by debug applications 184 * to help trace and trap on particular address locations. 185 * The bits in the Debug Control Registers above help define which 186 * of the following registers will contain valid data and/or addresses. 187 */ 188 unsigned long iac1; 189 unsigned long iac2; 190 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 191 unsigned long iac3; 192 unsigned long iac4; 193 #endif 194 unsigned long dac1; 195 unsigned long dac2; 196 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 197 unsigned long dvc1; 198 unsigned long dvc2; 199 #endif 200 #endif 201 }; 202 203 struct thread_struct { 204 unsigned long ksp; /* Kernel stack pointer */ 205 206 #ifdef CONFIG_PPC64 207 unsigned long ksp_vsid; 208 #endif 209 struct pt_regs *regs; /* Pointer to saved register state */ 210 mm_segment_t fs; /* for get_fs() validation */ 211 #ifdef CONFIG_BOOKE 212 /* BookE base exception scratch space; align on cacheline */ 213 unsigned long normsave[8] ____cacheline_aligned; 214 #endif 215 #ifdef CONFIG_PPC32 216 void *pgdir; /* root of page-table tree */ 217 unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */ 218 #endif 219 /* Debug Registers */ 220 struct debug_reg debug; 221 struct thread_fp_state fp_state; 222 struct thread_fp_state *fp_save_area; 223 int fpexc_mode; /* floating-point exception mode */ 224 unsigned int align_ctl; /* alignment handling control */ 225 #ifdef CONFIG_PPC64 226 unsigned long start_tb; /* Start purr when proc switched in */ 227 unsigned long accum_tb; /* Total accumilated purr for process */ 228 #ifdef CONFIG_HAVE_HW_BREAKPOINT 229 struct perf_event *ptrace_bps[HBP_NUM]; 230 /* 231 * Helps identify source of single-step exception and subsequent 232 * hw-breakpoint enablement 233 */ 234 struct perf_event *last_hit_ubp; 235 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 236 #endif 237 struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */ 238 unsigned long trap_nr; /* last trap # on this thread */ 239 #ifdef CONFIG_ALTIVEC 240 struct thread_vr_state vr_state; 241 struct thread_vr_state *vr_save_area; 242 unsigned long vrsave; 243 int used_vr; /* set if process has used altivec */ 244 #endif /* CONFIG_ALTIVEC */ 245 #ifdef CONFIG_VSX 246 /* VSR status */ 247 int used_vsr; /* set if process has used altivec */ 248 #endif /* CONFIG_VSX */ 249 #ifdef CONFIG_SPE 250 unsigned long evr[32]; /* upper 32-bits of SPE regs */ 251 u64 acc; /* Accumulator */ 252 unsigned long spefscr; /* SPE & eFP status */ 253 unsigned long spefscr_last; /* SPEFSCR value on last prctl 254 call or trap return */ 255 int used_spe; /* set if process has used spe */ 256 #endif /* CONFIG_SPE */ 257 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 258 u64 tm_tfhar; /* Transaction fail handler addr */ 259 u64 tm_texasr; /* Transaction exception & summary */ 260 u64 tm_tfiar; /* Transaction fail instr address reg */ 261 struct pt_regs ckpt_regs; /* Checkpointed registers */ 262 263 unsigned long tm_tar; 264 unsigned long tm_ppr; 265 unsigned long tm_dscr; 266 267 /* 268 * Transactional FP and VSX 0-31 register set. 269 * NOTE: the sense of these is the opposite of the integer ckpt_regs! 270 * 271 * When a transaction is active/signalled/scheduled etc., *regs is the 272 * most recent set of/speculated GPRs with ckpt_regs being the older 273 * checkpointed regs to which we roll back if transaction aborts. 274 * 275 * However, fpr[] is the checkpointed 'base state' of FP regs, and 276 * transact_fpr[] is the new set of transactional values. 277 * VRs work the same way. 278 */ 279 struct thread_fp_state transact_fp; 280 struct thread_vr_state transact_vr; 281 unsigned long transact_vrsave; 282 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 283 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER 284 void* kvm_shadow_vcpu; /* KVM internal data */ 285 #endif /* CONFIG_KVM_BOOK3S_32_HANDLER */ 286 #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE) 287 struct kvm_vcpu *kvm_vcpu; 288 #endif 289 #ifdef CONFIG_PPC64 290 unsigned long dscr; 291 unsigned long fscr; 292 /* 293 * This member element dscr_inherit indicates that the process 294 * has explicitly attempted and changed the DSCR register value 295 * for itself. Hence kernel wont use the default CPU DSCR value 296 * contained in the PACA structure anymore during process context 297 * switch. Once this variable is set, this behaviour will also be 298 * inherited to all the children of this process from that point 299 * onwards. 300 */ 301 int dscr_inherit; 302 unsigned long ppr; /* used to save/restore SMT priority */ 303 #endif 304 #ifdef CONFIG_PPC_BOOK3S_64 305 unsigned long tar; 306 unsigned long ebbrr; 307 unsigned long ebbhr; 308 unsigned long bescr; 309 unsigned long siar; 310 unsigned long sdar; 311 unsigned long sier; 312 unsigned long mmcr2; 313 unsigned mmcr0; 314 unsigned used_ebb; 315 #endif 316 }; 317 318 #define ARCH_MIN_TASKALIGN 16 319 320 #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) 321 #define INIT_SP_LIMIT \ 322 (_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack) 323 324 #ifdef CONFIG_SPE 325 #define SPEFSCR_INIT \ 326 .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \ 327 .spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, 328 #else 329 #define SPEFSCR_INIT 330 #endif 331 332 #ifdef CONFIG_PPC32 333 #define INIT_THREAD { \ 334 .ksp = INIT_SP, \ 335 .ksp_limit = INIT_SP_LIMIT, \ 336 .fs = KERNEL_DS, \ 337 .pgdir = swapper_pg_dir, \ 338 .fpexc_mode = MSR_FE0 | MSR_FE1, \ 339 SPEFSCR_INIT \ 340 } 341 #else 342 #define INIT_THREAD { \ 343 .ksp = INIT_SP, \ 344 .regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \ 345 .fs = KERNEL_DS, \ 346 .fpexc_mode = 0, \ 347 .ppr = INIT_PPR, \ 348 } 349 #endif 350 351 /* 352 * Return saved PC of a blocked thread. For now, this is the "user" PC 353 */ 354 #define thread_saved_pc(tsk) \ 355 ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0) 356 357 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.regs) 358 359 unsigned long get_wchan(struct task_struct *p); 360 361 #define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0) 362 #define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0) 363 364 /* Get/set floating-point exception mode */ 365 #define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr)) 366 #define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val)) 367 368 extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr); 369 extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val); 370 371 #define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr)) 372 #define SET_ENDIAN(tsk, val) set_endian((tsk), (val)) 373 374 extern int get_endian(struct task_struct *tsk, unsigned long adr); 375 extern int set_endian(struct task_struct *tsk, unsigned int val); 376 377 #define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr)) 378 #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) 379 380 extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr); 381 extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val); 382 383 extern void load_fp_state(struct thread_fp_state *fp); 384 extern void store_fp_state(struct thread_fp_state *fp); 385 extern void load_vr_state(struct thread_vr_state *vr); 386 extern void store_vr_state(struct thread_vr_state *vr); 387 388 static inline unsigned int __unpack_fe01(unsigned long msr_bits) 389 { 390 return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8); 391 } 392 393 static inline unsigned long __pack_fe01(unsigned int fpmode) 394 { 395 return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1); 396 } 397 398 #ifdef CONFIG_PPC64 399 #define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0) 400 #else 401 #define cpu_relax() barrier() 402 #endif 403 404 #define cpu_relax_lowlatency() cpu_relax() 405 406 /* Check that a certain kernel stack pointer is valid in task_struct p */ 407 int validate_sp(unsigned long sp, struct task_struct *p, 408 unsigned long nbytes); 409 410 /* 411 * Prefetch macros. 412 */ 413 #define ARCH_HAS_PREFETCH 414 #define ARCH_HAS_PREFETCHW 415 #define ARCH_HAS_SPINLOCK_PREFETCH 416 417 static inline void prefetch(const void *x) 418 { 419 if (unlikely(!x)) 420 return; 421 422 __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x)); 423 } 424 425 static inline void prefetchw(const void *x) 426 { 427 if (unlikely(!x)) 428 return; 429 430 __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x)); 431 } 432 433 #define spin_lock_prefetch(x) prefetchw(x) 434 435 #define HAVE_ARCH_PICK_MMAP_LAYOUT 436 437 #ifdef CONFIG_PPC64 438 static inline unsigned long get_clean_sp(unsigned long sp, int is_32) 439 { 440 if (is_32) 441 return sp & 0x0ffffffffUL; 442 return sp; 443 } 444 #else 445 static inline unsigned long get_clean_sp(unsigned long sp, int is_32) 446 { 447 return sp; 448 } 449 #endif 450 451 extern unsigned long cpuidle_disable; 452 enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF}; 453 454 extern int powersave_nap; /* set if nap mode can be used in idle loop */ 455 extern unsigned long power7_nap(int check_irq); 456 extern unsigned long power7_sleep(void); 457 extern unsigned long power7_winkle(void); 458 extern void flush_instruction_cache(void); 459 extern void hard_reset_now(void); 460 extern void poweroff_now(void); 461 extern int fix_alignment(struct pt_regs *); 462 extern void cvt_fd(float *from, double *to); 463 extern void cvt_df(double *from, float *to); 464 extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); 465 466 #ifdef CONFIG_PPC64 467 /* 468 * We handle most unaligned accesses in hardware. On the other hand 469 * unaligned DMA can be very expensive on some ppc64 IO chips (it does 470 * powers of 2 writes until it reaches sufficient alignment). 471 * 472 * Based on this we disable the IP header alignment in network drivers. 473 */ 474 #define NET_IP_ALIGN 0 475 #endif 476 477 #endif /* __KERNEL__ */ 478 #endif /* __ASSEMBLY__ */ 479 #endif /* _ASM_POWERPC_PROCESSOR_H */ 480