1 /* 2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. 3 */ 4 #ifndef _ASM_POWERPC_PPC_ASM_H 5 #define _ASM_POWERPC_PPC_ASM_H 6 7 #include <linux/init.h> 8 #include <linux/stringify.h> 9 #include <asm/asm-compat.h> 10 #include <asm/processor.h> 11 #include <asm/ppc-opcode.h> 12 #include <asm/firmware.h> 13 14 #ifndef __ASSEMBLY__ 15 #error __FILE__ should only be used in assembler files 16 #else 17 18 #define SZL (BITS_PER_LONG/8) 19 20 /* 21 * Stuff for accurate CPU time accounting. 22 * These macros handle transitions between user and system state 23 * in exception entry and exit and accumulate time to the 24 * user_time and system_time fields in the paca. 25 */ 26 27 #ifndef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE 28 #define ACCOUNT_CPU_USER_ENTRY(ra, rb) 29 #define ACCOUNT_CPU_USER_EXIT(ra, rb) 30 #define ACCOUNT_STOLEN_TIME 31 #else 32 #define ACCOUNT_CPU_USER_ENTRY(ra, rb) \ 33 MFTB(ra); /* get timebase */ \ 34 ld rb,PACA_STARTTIME_USER(r13); \ 35 std ra,PACA_STARTTIME(r13); \ 36 subf rb,rb,ra; /* subtract start value */ \ 37 ld ra,PACA_USER_TIME(r13); \ 38 add ra,ra,rb; /* add on to user time */ \ 39 std ra,PACA_USER_TIME(r13); \ 40 41 #define ACCOUNT_CPU_USER_EXIT(ra, rb) \ 42 MFTB(ra); /* get timebase */ \ 43 ld rb,PACA_STARTTIME(r13); \ 44 std ra,PACA_STARTTIME_USER(r13); \ 45 subf rb,rb,ra; /* subtract start value */ \ 46 ld ra,PACA_SYSTEM_TIME(r13); \ 47 add ra,ra,rb; /* add on to system time */ \ 48 std ra,PACA_SYSTEM_TIME(r13) 49 50 #ifdef CONFIG_PPC_SPLPAR 51 #define ACCOUNT_STOLEN_TIME \ 52 BEGIN_FW_FTR_SECTION; \ 53 beq 33f; \ 54 /* from user - see if there are any DTL entries to process */ \ 55 ld r10,PACALPPACAPTR(r13); /* get ptr to VPA */ \ 56 ld r11,PACA_DTL_RIDX(r13); /* get log read index */ \ 57 ld r10,LPPACA_DTLIDX(r10); /* get log write index */ \ 58 cmpd cr1,r11,r10; \ 59 beq+ cr1,33f; \ 60 bl .accumulate_stolen_time; \ 61 ld r12,_MSR(r1); \ 62 andi. r10,r12,MSR_PR; /* Restore cr0 (coming from user) */ \ 63 33: \ 64 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR) 65 66 #else /* CONFIG_PPC_SPLPAR */ 67 #define ACCOUNT_STOLEN_TIME 68 69 #endif /* CONFIG_PPC_SPLPAR */ 70 71 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */ 72 73 /* 74 * Macros for storing registers into and loading registers from 75 * exception frames. 76 */ 77 #ifdef __powerpc64__ 78 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base) 79 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base) 80 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) 81 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) 82 #else 83 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) 84 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) 85 #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \ 86 SAVE_10GPRS(22, base) 87 #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \ 88 REST_10GPRS(22, base) 89 #endif 90 91 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) 92 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) 93 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) 94 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) 95 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) 96 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) 97 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) 98 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) 99 100 #define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) 101 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) 102 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) 103 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) 104 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) 105 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) 106 #define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) 107 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) 108 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) 109 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) 110 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) 111 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) 112 113 #define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,base,b 114 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) 115 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) 116 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) 117 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) 118 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) 119 #define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,base,b 120 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) 121 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) 122 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) 123 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) 124 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) 125 126 /* Save/restore FPRs, VRs and VSRs from their checkpointed backups in 127 * thread_struct: 128 */ 129 #define SAVE_FPR_TRANSACT(n, base) stfd n,THREAD_TRANSACT_FPR0+ \ 130 8*TS_FPRWIDTH*(n)(base) 131 #define SAVE_2FPRS_TRANSACT(n, base) SAVE_FPR_TRANSACT(n, base); \ 132 SAVE_FPR_TRANSACT(n+1, base) 133 #define SAVE_4FPRS_TRANSACT(n, base) SAVE_2FPRS_TRANSACT(n, base); \ 134 SAVE_2FPRS_TRANSACT(n+2, base) 135 #define SAVE_8FPRS_TRANSACT(n, base) SAVE_4FPRS_TRANSACT(n, base); \ 136 SAVE_4FPRS_TRANSACT(n+4, base) 137 #define SAVE_16FPRS_TRANSACT(n, base) SAVE_8FPRS_TRANSACT(n, base); \ 138 SAVE_8FPRS_TRANSACT(n+8, base) 139 #define SAVE_32FPRS_TRANSACT(n, base) SAVE_16FPRS_TRANSACT(n, base); \ 140 SAVE_16FPRS_TRANSACT(n+16, base) 141 142 #define REST_FPR_TRANSACT(n, base) lfd n,THREAD_TRANSACT_FPR0+ \ 143 8*TS_FPRWIDTH*(n)(base) 144 #define REST_2FPRS_TRANSACT(n, base) REST_FPR_TRANSACT(n, base); \ 145 REST_FPR_TRANSACT(n+1, base) 146 #define REST_4FPRS_TRANSACT(n, base) REST_2FPRS_TRANSACT(n, base); \ 147 REST_2FPRS_TRANSACT(n+2, base) 148 #define REST_8FPRS_TRANSACT(n, base) REST_4FPRS_TRANSACT(n, base); \ 149 REST_4FPRS_TRANSACT(n+4, base) 150 #define REST_16FPRS_TRANSACT(n, base) REST_8FPRS_TRANSACT(n, base); \ 151 REST_8FPRS_TRANSACT(n+8, base) 152 #define REST_32FPRS_TRANSACT(n, base) REST_16FPRS_TRANSACT(n, base); \ 153 REST_16FPRS_TRANSACT(n+16, base) 154 155 156 #define SAVE_VR_TRANSACT(n,b,base) li b,THREAD_TRANSACT_VR0+(16*(n)); \ 157 stvx n,b,base 158 #define SAVE_2VRS_TRANSACT(n,b,base) SAVE_VR_TRANSACT(n,b,base); \ 159 SAVE_VR_TRANSACT(n+1,b,base) 160 #define SAVE_4VRS_TRANSACT(n,b,base) SAVE_2VRS_TRANSACT(n,b,base); \ 161 SAVE_2VRS_TRANSACT(n+2,b,base) 162 #define SAVE_8VRS_TRANSACT(n,b,base) SAVE_4VRS_TRANSACT(n,b,base); \ 163 SAVE_4VRS_TRANSACT(n+4,b,base) 164 #define SAVE_16VRS_TRANSACT(n,b,base) SAVE_8VRS_TRANSACT(n,b,base); \ 165 SAVE_8VRS_TRANSACT(n+8,b,base) 166 #define SAVE_32VRS_TRANSACT(n,b,base) SAVE_16VRS_TRANSACT(n,b,base); \ 167 SAVE_16VRS_TRANSACT(n+16,b,base) 168 169 #define REST_VR_TRANSACT(n,b,base) li b,THREAD_TRANSACT_VR0+(16*(n)); \ 170 lvx n,b,base 171 #define REST_2VRS_TRANSACT(n,b,base) REST_VR_TRANSACT(n,b,base); \ 172 REST_VR_TRANSACT(n+1,b,base) 173 #define REST_4VRS_TRANSACT(n,b,base) REST_2VRS_TRANSACT(n,b,base); \ 174 REST_2VRS_TRANSACT(n+2,b,base) 175 #define REST_8VRS_TRANSACT(n,b,base) REST_4VRS_TRANSACT(n,b,base); \ 176 REST_4VRS_TRANSACT(n+4,b,base) 177 #define REST_16VRS_TRANSACT(n,b,base) REST_8VRS_TRANSACT(n,b,base); \ 178 REST_8VRS_TRANSACT(n+8,b,base) 179 #define REST_32VRS_TRANSACT(n,b,base) REST_16VRS_TRANSACT(n,b,base); \ 180 REST_16VRS_TRANSACT(n+16,b,base) 181 182 183 #define SAVE_VSR_TRANSACT(n,b,base) li b,THREAD_TRANSACT_VSR0+(16*(n)); \ 184 STXVD2X(n,R##base,R##b) 185 #define SAVE_2VSRS_TRANSACT(n,b,base) SAVE_VSR_TRANSACT(n,b,base); \ 186 SAVE_VSR_TRANSACT(n+1,b,base) 187 #define SAVE_4VSRS_TRANSACT(n,b,base) SAVE_2VSRS_TRANSACT(n,b,base); \ 188 SAVE_2VSRS_TRANSACT(n+2,b,base) 189 #define SAVE_8VSRS_TRANSACT(n,b,base) SAVE_4VSRS_TRANSACT(n,b,base); \ 190 SAVE_4VSRS_TRANSACT(n+4,b,base) 191 #define SAVE_16VSRS_TRANSACT(n,b,base) SAVE_8VSRS_TRANSACT(n,b,base); \ 192 SAVE_8VSRS_TRANSACT(n+8,b,base) 193 #define SAVE_32VSRS_TRANSACT(n,b,base) SAVE_16VSRS_TRANSACT(n,b,base); \ 194 SAVE_16VSRS_TRANSACT(n+16,b,base) 195 196 #define REST_VSR_TRANSACT(n,b,base) li b,THREAD_TRANSACT_VSR0+(16*(n)); \ 197 LXVD2X(n,R##base,R##b) 198 #define REST_2VSRS_TRANSACT(n,b,base) REST_VSR_TRANSACT(n,b,base); \ 199 REST_VSR_TRANSACT(n+1,b,base) 200 #define REST_4VSRS_TRANSACT(n,b,base) REST_2VSRS_TRANSACT(n,b,base); \ 201 REST_2VSRS_TRANSACT(n+2,b,base) 202 #define REST_8VSRS_TRANSACT(n,b,base) REST_4VSRS_TRANSACT(n,b,base); \ 203 REST_4VSRS_TRANSACT(n+4,b,base) 204 #define REST_16VSRS_TRANSACT(n,b,base) REST_8VSRS_TRANSACT(n,b,base); \ 205 REST_8VSRS_TRANSACT(n+8,b,base) 206 #define REST_32VSRS_TRANSACT(n,b,base) REST_16VSRS_TRANSACT(n,b,base); \ 207 REST_16VSRS_TRANSACT(n+16,b,base) 208 209 /* Save the lower 32 VSRs in the thread VSR region */ 210 #define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,R##base,R##b) 211 #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) 212 #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base) 213 #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base) 214 #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base) 215 #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) 216 #define REST_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,R##base,R##b) 217 #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base) 218 #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base) 219 #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base) 220 #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base) 221 #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base) 222 /* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */ 223 #define SAVE_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,R##base,R##b) 224 #define SAVE_2VSRSU(n,b,base) SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base) 225 #define SAVE_4VSRSU(n,b,base) SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base) 226 #define SAVE_8VSRSU(n,b,base) SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base) 227 #define SAVE_16VSRSU(n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base) 228 #define SAVE_32VSRSU(n,b,base) SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base) 229 #define REST_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,R##base,R##b) 230 #define REST_2VSRSU(n,b,base) REST_VSRU(n,b,base); REST_VSRU(n+1,b,base) 231 #define REST_4VSRSU(n,b,base) REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base) 232 #define REST_8VSRSU(n,b,base) REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base) 233 #define REST_16VSRSU(n,b,base) REST_8VSRSU(n,b,base); REST_8VSRSU(n+8,b,base) 234 #define REST_32VSRSU(n,b,base) REST_16VSRSU(n,b,base); REST_16VSRSU(n+16,b,base) 235 236 /* 237 * b = base register for addressing, o = base offset from register of 1st EVR 238 * n = first EVR, s = scratch 239 */ 240 #define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b) 241 #define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o) 242 #define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o) 243 #define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o) 244 #define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o) 245 #define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o) 246 #define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n 247 #define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o) 248 #define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o) 249 #define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o) 250 #define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o) 251 #define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o) 252 253 /* Macros to adjust thread priority for hardware multithreading */ 254 #define HMT_VERY_LOW or 31,31,31 # very low priority 255 #define HMT_LOW or 1,1,1 256 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority 257 #define HMT_MEDIUM or 2,2,2 258 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority 259 #define HMT_HIGH or 3,3,3 260 #define HMT_EXTRA_HIGH or 7,7,7 # power7 only 261 262 #ifdef CONFIG_PPC64 263 #define ULONG_SIZE 8 264 #else 265 #define ULONG_SIZE 4 266 #endif 267 #define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE)) 268 #define VCPU_GPR(n) __VCPU_GPR(__REG_##n) 269 270 #ifdef __KERNEL__ 271 #ifdef CONFIG_PPC64 272 273 #define STACKFRAMESIZE 256 274 #define __STK_REG(i) (112 + ((i)-14)*8) 275 #define STK_REG(i) __STK_REG(__REG_##i) 276 277 #define __STK_PARAM(i) (48 + ((i)-3)*8) 278 #define STK_PARAM(i) __STK_PARAM(__REG_##i) 279 280 #define XGLUE(a,b) a##b 281 #define GLUE(a,b) XGLUE(a,b) 282 283 #define _GLOBAL(name) \ 284 .section ".text"; \ 285 .align 2 ; \ 286 .globl name; \ 287 .globl GLUE(.,name); \ 288 .section ".opd","aw"; \ 289 name: \ 290 .quad GLUE(.,name); \ 291 .quad .TOC.@tocbase; \ 292 .quad 0; \ 293 .previous; \ 294 .type GLUE(.,name),@function; \ 295 GLUE(.,name): 296 297 #define _INIT_GLOBAL(name) \ 298 __REF; \ 299 .align 2 ; \ 300 .globl name; \ 301 .globl GLUE(.,name); \ 302 .section ".opd","aw"; \ 303 name: \ 304 .quad GLUE(.,name); \ 305 .quad .TOC.@tocbase; \ 306 .quad 0; \ 307 .previous; \ 308 .type GLUE(.,name),@function; \ 309 GLUE(.,name): 310 311 #define _KPROBE(name) \ 312 .section ".kprobes.text","a"; \ 313 .align 2 ; \ 314 .globl name; \ 315 .globl GLUE(.,name); \ 316 .section ".opd","aw"; \ 317 name: \ 318 .quad GLUE(.,name); \ 319 .quad .TOC.@tocbase; \ 320 .quad 0; \ 321 .previous; \ 322 .type GLUE(.,name),@function; \ 323 GLUE(.,name): 324 325 #define _STATIC(name) \ 326 .section ".text"; \ 327 .align 2 ; \ 328 .section ".opd","aw"; \ 329 name: \ 330 .quad GLUE(.,name); \ 331 .quad .TOC.@tocbase; \ 332 .quad 0; \ 333 .previous; \ 334 .type GLUE(.,name),@function; \ 335 GLUE(.,name): 336 337 #define _INIT_STATIC(name) \ 338 __REF; \ 339 .align 2 ; \ 340 .section ".opd","aw"; \ 341 name: \ 342 .quad GLUE(.,name); \ 343 .quad .TOC.@tocbase; \ 344 .quad 0; \ 345 .previous; \ 346 .type GLUE(.,name),@function; \ 347 GLUE(.,name): 348 349 #else /* 32-bit */ 350 351 #define _ENTRY(n) \ 352 .globl n; \ 353 n: 354 355 #define _GLOBAL(n) \ 356 .text; \ 357 .stabs __stringify(n:F-1),N_FUN,0,0,n;\ 358 .globl n; \ 359 n: 360 361 #define _KPROBE(n) \ 362 .section ".kprobes.text","a"; \ 363 .globl n; \ 364 n: 365 366 #endif 367 368 /* 369 * LOAD_REG_IMMEDIATE(rn, expr) 370 * Loads the value of the constant expression 'expr' into register 'rn' 371 * using immediate instructions only. Use this when it's important not 372 * to reference other data (i.e. on ppc64 when the TOC pointer is not 373 * valid) and when 'expr' is a constant or absolute address. 374 * 375 * LOAD_REG_ADDR(rn, name) 376 * Loads the address of label 'name' into register 'rn'. Use this when 377 * you don't particularly need immediate instructions only, but you need 378 * the whole address in one register (e.g. it's a structure address and 379 * you want to access various offsets within it). On ppc32 this is 380 * identical to LOAD_REG_IMMEDIATE. 381 * 382 * LOAD_REG_ADDRBASE(rn, name) 383 * ADDROFF(name) 384 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into 385 * register 'rn'. ADDROFF(name) returns the remainder of the address as 386 * a constant expression. ADDROFF(name) is a signed expression < 16 bits 387 * in size, so is suitable for use directly as an offset in load and store 388 * instructions. Use this when loading/storing a single word or less as: 389 * LOAD_REG_ADDRBASE(rX, name) 390 * ld rY,ADDROFF(name)(rX) 391 */ 392 #ifdef __powerpc64__ 393 #define LOAD_REG_IMMEDIATE(reg,expr) \ 394 lis reg,(expr)@highest; \ 395 ori reg,reg,(expr)@higher; \ 396 rldicr reg,reg,32,31; \ 397 oris reg,reg,(expr)@h; \ 398 ori reg,reg,(expr)@l; 399 400 #define LOAD_REG_ADDR(reg,name) \ 401 ld reg,name@got(r2) 402 403 #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name) 404 #define ADDROFF(name) 0 405 406 /* offsets for stack frame layout */ 407 #define LRSAVE 16 408 409 #else /* 32-bit */ 410 411 #define LOAD_REG_IMMEDIATE(reg,expr) \ 412 lis reg,(expr)@ha; \ 413 addi reg,reg,(expr)@l; 414 415 #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name) 416 417 #define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha 418 #define ADDROFF(name) name@l 419 420 /* offsets for stack frame layout */ 421 #define LRSAVE 4 422 423 #endif 424 425 /* various errata or part fixups */ 426 #ifdef CONFIG_PPC601_SYNC_FIX 427 #define SYNC \ 428 BEGIN_FTR_SECTION \ 429 sync; \ 430 isync; \ 431 END_FTR_SECTION_IFSET(CPU_FTR_601) 432 #define SYNC_601 \ 433 BEGIN_FTR_SECTION \ 434 sync; \ 435 END_FTR_SECTION_IFSET(CPU_FTR_601) 436 #define ISYNC_601 \ 437 BEGIN_FTR_SECTION \ 438 isync; \ 439 END_FTR_SECTION_IFSET(CPU_FTR_601) 440 #else 441 #define SYNC 442 #define SYNC_601 443 #define ISYNC_601 444 #endif 445 446 #ifdef CONFIG_PPC_CELL 447 #define MFTB(dest) \ 448 90: mftb dest; \ 449 BEGIN_FTR_SECTION_NESTED(96); \ 450 cmpwi dest,0; \ 451 beq- 90b; \ 452 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) 453 #else 454 #define MFTB(dest) mftb dest 455 #endif 456 457 #ifndef CONFIG_SMP 458 #define TLBSYNC 459 #else /* CONFIG_SMP */ 460 /* tlbsync is not implemented on 601 */ 461 #define TLBSYNC \ 462 BEGIN_FTR_SECTION \ 463 tlbsync; \ 464 sync; \ 465 END_FTR_SECTION_IFCLR(CPU_FTR_601) 466 #endif 467 468 #ifdef CONFIG_PPC64 469 #define MTOCRF(FXM, RS) \ 470 BEGIN_FTR_SECTION_NESTED(848); \ 471 mtcrf (FXM), RS; \ 472 FTR_SECTION_ELSE_NESTED(848); \ 473 mtocrf (FXM), RS; \ 474 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848) 475 476 /* 477 * PPR restore macros used in entry_64.S 478 * Used for P7 or later processors 479 */ 480 #define HMT_MEDIUM_LOW_HAS_PPR \ 481 BEGIN_FTR_SECTION_NESTED(944) \ 482 HMT_MEDIUM_LOW; \ 483 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,944) 484 485 #define SET_DEFAULT_THREAD_PPR(ra, rb) \ 486 BEGIN_FTR_SECTION_NESTED(945) \ 487 lis ra,INIT_PPR@highest; /* default ppr=3 */ \ 488 ld rb,PACACURRENT(r13); \ 489 sldi ra,ra,32; /* 11- 13 bits are used for ppr */ \ 490 std ra,TASKTHREADPPR(rb); \ 491 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,945) 492 493 #define RESTORE_PPR(ra, rb) \ 494 BEGIN_FTR_SECTION_NESTED(946) \ 495 ld ra,PACACURRENT(r13); \ 496 ld rb,TASKTHREADPPR(ra); \ 497 mtspr SPRN_PPR,rb; /* Restore PPR */ \ 498 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,946) 499 500 #endif 501 502 /* 503 * This instruction is not implemented on the PPC 603 or 601; however, on 504 * the 403GCX and 405GP tlbia IS defined and tlbie is not. 505 * All of these instructions exist in the 8xx, they have magical powers, 506 * and they must be used. 507 */ 508 509 #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx) 510 #define tlbia \ 511 li r4,1024; \ 512 mtctr r4; \ 513 lis r4,KERNELBASE@h; \ 514 0: tlbie r4; \ 515 addi r4,r4,0x1000; \ 516 bdnz 0b 517 #endif 518 519 520 #ifdef CONFIG_IBM440EP_ERR42 521 #define PPC440EP_ERR42 isync 522 #else 523 #define PPC440EP_ERR42 524 #endif 525 526 /* 527 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them 528 * keep the address intact to be compatible with code shared with 529 * 32-bit classic. 530 * 531 * On the other hand, I find it useful to have them behave as expected 532 * by their name (ie always do the addition) on 64-bit BookE 533 */ 534 #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64) 535 #define toreal(rd) 536 #define fromreal(rd) 537 538 /* 539 * We use addis to ensure compatibility with the "classic" ppc versions of 540 * these macros, which use rs = 0 to get the tophys offset in rd, rather than 541 * converting the address in r0, and so this version has to do that too 542 * (i.e. set register rd to 0 when rs == 0). 543 */ 544 #define tophys(rd,rs) \ 545 addis rd,rs,0 546 547 #define tovirt(rd,rs) \ 548 addis rd,rs,0 549 550 #elif defined(CONFIG_PPC64) 551 #define toreal(rd) /* we can access c000... in real mode */ 552 #define fromreal(rd) 553 554 #define tophys(rd,rs) \ 555 clrldi rd,rs,2 556 557 #define tovirt(rd,rs) \ 558 rotldi rd,rs,16; \ 559 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\ 560 rotldi rd,rd,48 561 #else 562 /* 563 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the 564 * physical base address of RAM at compile time. 565 */ 566 #define toreal(rd) tophys(rd,rd) 567 #define fromreal(rd) tovirt(rd,rd) 568 569 #define tophys(rd,rs) \ 570 0: addis rd,rs,-PAGE_OFFSET@h; \ 571 .section ".vtop_fixup","aw"; \ 572 .align 1; \ 573 .long 0b; \ 574 .previous 575 576 #define tovirt(rd,rs) \ 577 0: addis rd,rs,PAGE_OFFSET@h; \ 578 .section ".ptov_fixup","aw"; \ 579 .align 1; \ 580 .long 0b; \ 581 .previous 582 #endif 583 584 #ifdef CONFIG_PPC_BOOK3S_64 585 #define RFI rfid 586 #define MTMSRD(r) mtmsrd r 587 #define MTMSR_EERI(reg) mtmsrd reg,1 588 #else 589 #define FIX_SRR1(ra, rb) 590 #ifndef CONFIG_40x 591 #define RFI rfi 592 #else 593 #define RFI rfi; b . /* Prevent prefetch past rfi */ 594 #endif 595 #define MTMSRD(r) mtmsr r 596 #define MTMSR_EERI(reg) mtmsr reg 597 #define CLR_TOP32(r) 598 #endif 599 600 #endif /* __KERNEL__ */ 601 602 /* The boring bits... */ 603 604 /* Condition Register Bit Fields */ 605 606 #define cr0 0 607 #define cr1 1 608 #define cr2 2 609 #define cr3 3 610 #define cr4 4 611 #define cr5 5 612 #define cr6 6 613 #define cr7 7 614 615 616 /* 617 * General Purpose Registers (GPRs) 618 * 619 * The lower case r0-r31 should be used in preference to the upper 620 * case R0-R31 as they provide more error checking in the assembler. 621 * Use R0-31 only when really nessesary. 622 */ 623 624 #define r0 %r0 625 #define r1 %r1 626 #define r2 %r2 627 #define r3 %r3 628 #define r4 %r4 629 #define r5 %r5 630 #define r6 %r6 631 #define r7 %r7 632 #define r8 %r8 633 #define r9 %r9 634 #define r10 %r10 635 #define r11 %r11 636 #define r12 %r12 637 #define r13 %r13 638 #define r14 %r14 639 #define r15 %r15 640 #define r16 %r16 641 #define r17 %r17 642 #define r18 %r18 643 #define r19 %r19 644 #define r20 %r20 645 #define r21 %r21 646 #define r22 %r22 647 #define r23 %r23 648 #define r24 %r24 649 #define r25 %r25 650 #define r26 %r26 651 #define r27 %r27 652 #define r28 %r28 653 #define r29 %r29 654 #define r30 %r30 655 #define r31 %r31 656 657 658 /* Floating Point Registers (FPRs) */ 659 660 #define fr0 0 661 #define fr1 1 662 #define fr2 2 663 #define fr3 3 664 #define fr4 4 665 #define fr5 5 666 #define fr6 6 667 #define fr7 7 668 #define fr8 8 669 #define fr9 9 670 #define fr10 10 671 #define fr11 11 672 #define fr12 12 673 #define fr13 13 674 #define fr14 14 675 #define fr15 15 676 #define fr16 16 677 #define fr17 17 678 #define fr18 18 679 #define fr19 19 680 #define fr20 20 681 #define fr21 21 682 #define fr22 22 683 #define fr23 23 684 #define fr24 24 685 #define fr25 25 686 #define fr26 26 687 #define fr27 27 688 #define fr28 28 689 #define fr29 29 690 #define fr30 30 691 #define fr31 31 692 693 /* AltiVec Registers (VPRs) */ 694 695 #define vr0 0 696 #define vr1 1 697 #define vr2 2 698 #define vr3 3 699 #define vr4 4 700 #define vr5 5 701 #define vr6 6 702 #define vr7 7 703 #define vr8 8 704 #define vr9 9 705 #define vr10 10 706 #define vr11 11 707 #define vr12 12 708 #define vr13 13 709 #define vr14 14 710 #define vr15 15 711 #define vr16 16 712 #define vr17 17 713 #define vr18 18 714 #define vr19 19 715 #define vr20 20 716 #define vr21 21 717 #define vr22 22 718 #define vr23 23 719 #define vr24 24 720 #define vr25 25 721 #define vr26 26 722 #define vr27 27 723 #define vr28 28 724 #define vr29 29 725 #define vr30 30 726 #define vr31 31 727 728 /* VSX Registers (VSRs) */ 729 730 #define vsr0 0 731 #define vsr1 1 732 #define vsr2 2 733 #define vsr3 3 734 #define vsr4 4 735 #define vsr5 5 736 #define vsr6 6 737 #define vsr7 7 738 #define vsr8 8 739 #define vsr9 9 740 #define vsr10 10 741 #define vsr11 11 742 #define vsr12 12 743 #define vsr13 13 744 #define vsr14 14 745 #define vsr15 15 746 #define vsr16 16 747 #define vsr17 17 748 #define vsr18 18 749 #define vsr19 19 750 #define vsr20 20 751 #define vsr21 21 752 #define vsr22 22 753 #define vsr23 23 754 #define vsr24 24 755 #define vsr25 25 756 #define vsr26 26 757 #define vsr27 27 758 #define vsr28 28 759 #define vsr29 29 760 #define vsr30 30 761 #define vsr31 31 762 #define vsr32 32 763 #define vsr33 33 764 #define vsr34 34 765 #define vsr35 35 766 #define vsr36 36 767 #define vsr37 37 768 #define vsr38 38 769 #define vsr39 39 770 #define vsr40 40 771 #define vsr41 41 772 #define vsr42 42 773 #define vsr43 43 774 #define vsr44 44 775 #define vsr45 45 776 #define vsr46 46 777 #define vsr47 47 778 #define vsr48 48 779 #define vsr49 49 780 #define vsr50 50 781 #define vsr51 51 782 #define vsr52 52 783 #define vsr53 53 784 #define vsr54 54 785 #define vsr55 55 786 #define vsr56 56 787 #define vsr57 57 788 #define vsr58 58 789 #define vsr59 59 790 #define vsr60 60 791 #define vsr61 61 792 #define vsr62 62 793 #define vsr63 63 794 795 /* SPE Registers (EVPRs) */ 796 797 #define evr0 0 798 #define evr1 1 799 #define evr2 2 800 #define evr3 3 801 #define evr4 4 802 #define evr5 5 803 #define evr6 6 804 #define evr7 7 805 #define evr8 8 806 #define evr9 9 807 #define evr10 10 808 #define evr11 11 809 #define evr12 12 810 #define evr13 13 811 #define evr14 14 812 #define evr15 15 813 #define evr16 16 814 #define evr17 17 815 #define evr18 18 816 #define evr19 19 817 #define evr20 20 818 #define evr21 21 819 #define evr22 22 820 #define evr23 23 821 #define evr24 24 822 #define evr25 25 823 #define evr26 26 824 #define evr27 27 825 #define evr28 28 826 #define evr29 29 827 #define evr30 30 828 #define evr31 31 829 830 /* some stab codes */ 831 #define N_FUN 36 832 #define N_RSYM 64 833 #define N_SLINE 68 834 #define N_SO 100 835 836 #endif /* __ASSEMBLY__ */ 837 838 #endif /* _ASM_POWERPC_PPC_ASM_H */ 839