1 /* 2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. 3 */ 4 #ifndef _ASM_POWERPC_PPC_ASM_H 5 #define _ASM_POWERPC_PPC_ASM_H 6 7 #include <linux/init.h> 8 #include <linux/stringify.h> 9 #include <asm/asm-compat.h> 10 #include <asm/processor.h> 11 #include <asm/ppc-opcode.h> 12 13 #ifndef __ASSEMBLY__ 14 #error __FILE__ should only be used in assembler files 15 #else 16 17 #define SZL (BITS_PER_LONG/8) 18 19 /* 20 * Stuff for accurate CPU time accounting. 21 * These macros handle transitions between user and system state 22 * in exception entry and exit and accumulate time to the 23 * user_time and system_time fields in the paca. 24 */ 25 26 #ifndef CONFIG_VIRT_CPU_ACCOUNTING 27 #define ACCOUNT_CPU_USER_ENTRY(ra, rb) 28 #define ACCOUNT_CPU_USER_EXIT(ra, rb) 29 #else 30 #define ACCOUNT_CPU_USER_ENTRY(ra, rb) \ 31 beq 2f; /* if from kernel mode */ \ 32 BEGIN_FTR_SECTION; \ 33 mfspr ra,SPRN_PURR; /* get processor util. reg */ \ 34 END_FTR_SECTION_IFSET(CPU_FTR_PURR); \ 35 BEGIN_FTR_SECTION; \ 36 MFTB(ra); /* or get TB if no PURR */ \ 37 END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \ 38 ld rb,PACA_STARTPURR(r13); \ 39 std ra,PACA_STARTPURR(r13); \ 40 subf rb,rb,ra; /* subtract start value */ \ 41 ld ra,PACA_USER_TIME(r13); \ 42 add ra,ra,rb; /* add on to user time */ \ 43 std ra,PACA_USER_TIME(r13); \ 44 2: 45 46 #define ACCOUNT_CPU_USER_EXIT(ra, rb) \ 47 BEGIN_FTR_SECTION; \ 48 mfspr ra,SPRN_PURR; /* get processor util. reg */ \ 49 END_FTR_SECTION_IFSET(CPU_FTR_PURR); \ 50 BEGIN_FTR_SECTION; \ 51 MFTB(ra); /* or get TB if no PURR */ \ 52 END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \ 53 ld rb,PACA_STARTPURR(r13); \ 54 std ra,PACA_STARTPURR(r13); \ 55 subf rb,rb,ra; /* subtract start value */ \ 56 ld ra,PACA_SYSTEM_TIME(r13); \ 57 add ra,ra,rb; /* add on to user time */ \ 58 std ra,PACA_SYSTEM_TIME(r13); 59 #endif 60 61 /* 62 * Macros for storing registers into and loading registers from 63 * exception frames. 64 */ 65 #ifdef __powerpc64__ 66 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base) 67 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base) 68 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) 69 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) 70 #else 71 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) 72 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) 73 #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \ 74 SAVE_10GPRS(22, base) 75 #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \ 76 REST_10GPRS(22, base) 77 #endif 78 79 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) 80 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) 81 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) 82 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) 83 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) 84 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) 85 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) 86 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) 87 88 #define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) 89 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) 90 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) 91 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) 92 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) 93 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) 94 #define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) 95 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) 96 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) 97 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) 98 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) 99 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) 100 101 #define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,base,b 102 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) 103 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) 104 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) 105 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) 106 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) 107 #define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,base,b 108 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) 109 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) 110 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) 111 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) 112 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) 113 114 /* Save the lower 32 VSRs in the thread VSR region */ 115 #define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,base,b) 116 #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) 117 #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base) 118 #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base) 119 #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base) 120 #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) 121 #define REST_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,base,b) 122 #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base) 123 #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base) 124 #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base) 125 #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base) 126 #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base) 127 /* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */ 128 #define SAVE_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,base,b) 129 #define SAVE_2VSRSU(n,b,base) SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base) 130 #define SAVE_4VSRSU(n,b,base) SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base) 131 #define SAVE_8VSRSU(n,b,base) SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base) 132 #define SAVE_16VSRSU(n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base) 133 #define SAVE_32VSRSU(n,b,base) SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base) 134 #define REST_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,base,b) 135 #define REST_2VSRSU(n,b,base) REST_VSRU(n,b,base); REST_VSRU(n+1,b,base) 136 #define REST_4VSRSU(n,b,base) REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base) 137 #define REST_8VSRSU(n,b,base) REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base) 138 #define REST_16VSRSU(n,b,base) REST_8VSRSU(n,b,base); REST_8VSRSU(n+8,b,base) 139 #define REST_32VSRSU(n,b,base) REST_16VSRSU(n,b,base); REST_16VSRSU(n+16,b,base) 140 141 #define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base) 142 #define SAVE_2EVRS(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base) 143 #define SAVE_4EVRS(n,s,base) SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base) 144 #define SAVE_8EVRS(n,s,base) SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base) 145 #define SAVE_16EVRS(n,s,base) SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base) 146 #define SAVE_32EVRS(n,s,base) SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base) 147 #define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n 148 #define REST_2EVRS(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base) 149 #define REST_4EVRS(n,s,base) REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base) 150 #define REST_8EVRS(n,s,base) REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base) 151 #define REST_16EVRS(n,s,base) REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base) 152 #define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base) 153 154 /* Macros to adjust thread priority for hardware multithreading */ 155 #define HMT_VERY_LOW or 31,31,31 # very low priority 156 #define HMT_LOW or 1,1,1 157 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority 158 #define HMT_MEDIUM or 2,2,2 159 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority 160 #define HMT_HIGH or 3,3,3 161 162 #ifdef __KERNEL__ 163 #ifdef CONFIG_PPC64 164 165 #define XGLUE(a,b) a##b 166 #define GLUE(a,b) XGLUE(a,b) 167 168 #define _GLOBAL(name) \ 169 .section ".text"; \ 170 .align 2 ; \ 171 .globl name; \ 172 .globl GLUE(.,name); \ 173 .section ".opd","aw"; \ 174 name: \ 175 .quad GLUE(.,name); \ 176 .quad .TOC.@tocbase; \ 177 .quad 0; \ 178 .previous; \ 179 .type GLUE(.,name),@function; \ 180 GLUE(.,name): 181 182 #define _INIT_GLOBAL(name) \ 183 __REF; \ 184 .align 2 ; \ 185 .globl name; \ 186 .globl GLUE(.,name); \ 187 .section ".opd","aw"; \ 188 name: \ 189 .quad GLUE(.,name); \ 190 .quad .TOC.@tocbase; \ 191 .quad 0; \ 192 .previous; \ 193 .type GLUE(.,name),@function; \ 194 GLUE(.,name): 195 196 #define _KPROBE(name) \ 197 .section ".kprobes.text","a"; \ 198 .align 2 ; \ 199 .globl name; \ 200 .globl GLUE(.,name); \ 201 .section ".opd","aw"; \ 202 name: \ 203 .quad GLUE(.,name); \ 204 .quad .TOC.@tocbase; \ 205 .quad 0; \ 206 .previous; \ 207 .type GLUE(.,name),@function; \ 208 GLUE(.,name): 209 210 #define _STATIC(name) \ 211 .section ".text"; \ 212 .align 2 ; \ 213 .section ".opd","aw"; \ 214 name: \ 215 .quad GLUE(.,name); \ 216 .quad .TOC.@tocbase; \ 217 .quad 0; \ 218 .previous; \ 219 .type GLUE(.,name),@function; \ 220 GLUE(.,name): 221 222 #define _INIT_STATIC(name) \ 223 __REF; \ 224 .align 2 ; \ 225 .section ".opd","aw"; \ 226 name: \ 227 .quad GLUE(.,name); \ 228 .quad .TOC.@tocbase; \ 229 .quad 0; \ 230 .previous; \ 231 .type GLUE(.,name),@function; \ 232 GLUE(.,name): 233 234 #else /* 32-bit */ 235 236 #define _ENTRY(n) \ 237 .globl n; \ 238 n: 239 240 #define _GLOBAL(n) \ 241 .text; \ 242 .stabs __stringify(n:F-1),N_FUN,0,0,n;\ 243 .globl n; \ 244 n: 245 246 #define _KPROBE(n) \ 247 .section ".kprobes.text","a"; \ 248 .globl n; \ 249 n: 250 251 #endif 252 253 /* 254 * LOAD_REG_IMMEDIATE(rn, expr) 255 * Loads the value of the constant expression 'expr' into register 'rn' 256 * using immediate instructions only. Use this when it's important not 257 * to reference other data (i.e. on ppc64 when the TOC pointer is not 258 * valid) and when 'expr' is a constant or absolute address. 259 * 260 * LOAD_REG_ADDR(rn, name) 261 * Loads the address of label 'name' into register 'rn'. Use this when 262 * you don't particularly need immediate instructions only, but you need 263 * the whole address in one register (e.g. it's a structure address and 264 * you want to access various offsets within it). On ppc32 this is 265 * identical to LOAD_REG_IMMEDIATE. 266 * 267 * LOAD_REG_ADDRBASE(rn, name) 268 * ADDROFF(name) 269 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into 270 * register 'rn'. ADDROFF(name) returns the remainder of the address as 271 * a constant expression. ADDROFF(name) is a signed expression < 16 bits 272 * in size, so is suitable for use directly as an offset in load and store 273 * instructions. Use this when loading/storing a single word or less as: 274 * LOAD_REG_ADDRBASE(rX, name) 275 * ld rY,ADDROFF(name)(rX) 276 */ 277 #ifdef __powerpc64__ 278 #define LOAD_REG_IMMEDIATE(reg,expr) \ 279 lis (reg),(expr)@highest; \ 280 ori (reg),(reg),(expr)@higher; \ 281 rldicr (reg),(reg),32,31; \ 282 oris (reg),(reg),(expr)@h; \ 283 ori (reg),(reg),(expr)@l; 284 285 #define LOAD_REG_ADDR(reg,name) \ 286 ld (reg),name@got(r2) 287 288 #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name) 289 #define ADDROFF(name) 0 290 291 /* offsets for stack frame layout */ 292 #define LRSAVE 16 293 294 #else /* 32-bit */ 295 296 #define LOAD_REG_IMMEDIATE(reg,expr) \ 297 lis (reg),(expr)@ha; \ 298 addi (reg),(reg),(expr)@l; 299 300 #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name) 301 302 #define LOAD_REG_ADDRBASE(reg, name) lis (reg),name@ha 303 #define ADDROFF(name) name@l 304 305 /* offsets for stack frame layout */ 306 #define LRSAVE 4 307 308 #endif 309 310 /* various errata or part fixups */ 311 #ifdef CONFIG_PPC601_SYNC_FIX 312 #define SYNC \ 313 BEGIN_FTR_SECTION \ 314 sync; \ 315 isync; \ 316 END_FTR_SECTION_IFSET(CPU_FTR_601) 317 #define SYNC_601 \ 318 BEGIN_FTR_SECTION \ 319 sync; \ 320 END_FTR_SECTION_IFSET(CPU_FTR_601) 321 #define ISYNC_601 \ 322 BEGIN_FTR_SECTION \ 323 isync; \ 324 END_FTR_SECTION_IFSET(CPU_FTR_601) 325 #else 326 #define SYNC 327 #define SYNC_601 328 #define ISYNC_601 329 #endif 330 331 #ifdef CONFIG_PPC_CELL 332 #define MFTB(dest) \ 333 90: mftb dest; \ 334 BEGIN_FTR_SECTION_NESTED(96); \ 335 cmpwi dest,0; \ 336 beq- 90b; \ 337 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) 338 #else 339 #define MFTB(dest) mftb dest 340 #endif 341 342 #ifndef CONFIG_SMP 343 #define TLBSYNC 344 #else /* CONFIG_SMP */ 345 /* tlbsync is not implemented on 601 */ 346 #define TLBSYNC \ 347 BEGIN_FTR_SECTION \ 348 tlbsync; \ 349 sync; \ 350 END_FTR_SECTION_IFCLR(CPU_FTR_601) 351 #endif 352 353 354 /* 355 * This instruction is not implemented on the PPC 603 or 601; however, on 356 * the 403GCX and 405GP tlbia IS defined and tlbie is not. 357 * All of these instructions exist in the 8xx, they have magical powers, 358 * and they must be used. 359 */ 360 361 #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx) 362 #define tlbia \ 363 li r4,1024; \ 364 mtctr r4; \ 365 lis r4,KERNELBASE@h; \ 366 0: tlbie r4; \ 367 addi r4,r4,0x1000; \ 368 bdnz 0b 369 #endif 370 371 372 #ifdef CONFIG_IBM440EP_ERR42 373 #define PPC440EP_ERR42 isync 374 #else 375 #define PPC440EP_ERR42 376 #endif 377 378 /* 379 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them 380 * keep the address intact to be compatible with code shared with 381 * 32-bit classic. 382 * 383 * On the other hand, I find it useful to have them behave as expected 384 * by their name (ie always do the addition) on 64-bit BookE 385 */ 386 #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64) 387 #define toreal(rd) 388 #define fromreal(rd) 389 390 /* 391 * We use addis to ensure compatibility with the "classic" ppc versions of 392 * these macros, which use rs = 0 to get the tophys offset in rd, rather than 393 * converting the address in r0, and so this version has to do that too 394 * (i.e. set register rd to 0 when rs == 0). 395 */ 396 #define tophys(rd,rs) \ 397 addis rd,rs,0 398 399 #define tovirt(rd,rs) \ 400 addis rd,rs,0 401 402 #elif defined(CONFIG_PPC64) 403 #define toreal(rd) /* we can access c000... in real mode */ 404 #define fromreal(rd) 405 406 #define tophys(rd,rs) \ 407 clrldi rd,rs,2 408 409 #define tovirt(rd,rs) \ 410 rotldi rd,rs,16; \ 411 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\ 412 rotldi rd,rd,48 413 #else 414 /* 415 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the 416 * physical base address of RAM at compile time. 417 */ 418 #define toreal(rd) tophys(rd,rd) 419 #define fromreal(rd) tovirt(rd,rd) 420 421 #define tophys(rd,rs) \ 422 0: addis rd,rs,-PAGE_OFFSET@h; \ 423 .section ".vtop_fixup","aw"; \ 424 .align 1; \ 425 .long 0b; \ 426 .previous 427 428 #define tovirt(rd,rs) \ 429 0: addis rd,rs,PAGE_OFFSET@h; \ 430 .section ".ptov_fixup","aw"; \ 431 .align 1; \ 432 .long 0b; \ 433 .previous 434 #endif 435 436 #ifdef CONFIG_PPC_BOOK3S_64 437 #define RFI rfid 438 #define MTMSRD(r) mtmsrd r 439 #else 440 #define FIX_SRR1(ra, rb) 441 #ifndef CONFIG_40x 442 #define RFI rfi 443 #else 444 #define RFI rfi; b . /* Prevent prefetch past rfi */ 445 #endif 446 #define MTMSRD(r) mtmsr r 447 #define CLR_TOP32(r) 448 #endif 449 450 #endif /* __KERNEL__ */ 451 452 /* The boring bits... */ 453 454 /* Condition Register Bit Fields */ 455 456 #define cr0 0 457 #define cr1 1 458 #define cr2 2 459 #define cr3 3 460 #define cr4 4 461 #define cr5 5 462 #define cr6 6 463 #define cr7 7 464 465 466 /* General Purpose Registers (GPRs) */ 467 468 #define r0 0 469 #define r1 1 470 #define r2 2 471 #define r3 3 472 #define r4 4 473 #define r5 5 474 #define r6 6 475 #define r7 7 476 #define r8 8 477 #define r9 9 478 #define r10 10 479 #define r11 11 480 #define r12 12 481 #define r13 13 482 #define r14 14 483 #define r15 15 484 #define r16 16 485 #define r17 17 486 #define r18 18 487 #define r19 19 488 #define r20 20 489 #define r21 21 490 #define r22 22 491 #define r23 23 492 #define r24 24 493 #define r25 25 494 #define r26 26 495 #define r27 27 496 #define r28 28 497 #define r29 29 498 #define r30 30 499 #define r31 31 500 501 502 /* Floating Point Registers (FPRs) */ 503 504 #define fr0 0 505 #define fr1 1 506 #define fr2 2 507 #define fr3 3 508 #define fr4 4 509 #define fr5 5 510 #define fr6 6 511 #define fr7 7 512 #define fr8 8 513 #define fr9 9 514 #define fr10 10 515 #define fr11 11 516 #define fr12 12 517 #define fr13 13 518 #define fr14 14 519 #define fr15 15 520 #define fr16 16 521 #define fr17 17 522 #define fr18 18 523 #define fr19 19 524 #define fr20 20 525 #define fr21 21 526 #define fr22 22 527 #define fr23 23 528 #define fr24 24 529 #define fr25 25 530 #define fr26 26 531 #define fr27 27 532 #define fr28 28 533 #define fr29 29 534 #define fr30 30 535 #define fr31 31 536 537 /* AltiVec Registers (VPRs) */ 538 539 #define vr0 0 540 #define vr1 1 541 #define vr2 2 542 #define vr3 3 543 #define vr4 4 544 #define vr5 5 545 #define vr6 6 546 #define vr7 7 547 #define vr8 8 548 #define vr9 9 549 #define vr10 10 550 #define vr11 11 551 #define vr12 12 552 #define vr13 13 553 #define vr14 14 554 #define vr15 15 555 #define vr16 16 556 #define vr17 17 557 #define vr18 18 558 #define vr19 19 559 #define vr20 20 560 #define vr21 21 561 #define vr22 22 562 #define vr23 23 563 #define vr24 24 564 #define vr25 25 565 #define vr26 26 566 #define vr27 27 567 #define vr28 28 568 #define vr29 29 569 #define vr30 30 570 #define vr31 31 571 572 /* VSX Registers (VSRs) */ 573 574 #define vsr0 0 575 #define vsr1 1 576 #define vsr2 2 577 #define vsr3 3 578 #define vsr4 4 579 #define vsr5 5 580 #define vsr6 6 581 #define vsr7 7 582 #define vsr8 8 583 #define vsr9 9 584 #define vsr10 10 585 #define vsr11 11 586 #define vsr12 12 587 #define vsr13 13 588 #define vsr14 14 589 #define vsr15 15 590 #define vsr16 16 591 #define vsr17 17 592 #define vsr18 18 593 #define vsr19 19 594 #define vsr20 20 595 #define vsr21 21 596 #define vsr22 22 597 #define vsr23 23 598 #define vsr24 24 599 #define vsr25 25 600 #define vsr26 26 601 #define vsr27 27 602 #define vsr28 28 603 #define vsr29 29 604 #define vsr30 30 605 #define vsr31 31 606 #define vsr32 32 607 #define vsr33 33 608 #define vsr34 34 609 #define vsr35 35 610 #define vsr36 36 611 #define vsr37 37 612 #define vsr38 38 613 #define vsr39 39 614 #define vsr40 40 615 #define vsr41 41 616 #define vsr42 42 617 #define vsr43 43 618 #define vsr44 44 619 #define vsr45 45 620 #define vsr46 46 621 #define vsr47 47 622 #define vsr48 48 623 #define vsr49 49 624 #define vsr50 50 625 #define vsr51 51 626 #define vsr52 52 627 #define vsr53 53 628 #define vsr54 54 629 #define vsr55 55 630 #define vsr56 56 631 #define vsr57 57 632 #define vsr58 58 633 #define vsr59 59 634 #define vsr60 60 635 #define vsr61 61 636 #define vsr62 62 637 #define vsr63 63 638 639 /* SPE Registers (EVPRs) */ 640 641 #define evr0 0 642 #define evr1 1 643 #define evr2 2 644 #define evr3 3 645 #define evr4 4 646 #define evr5 5 647 #define evr6 6 648 #define evr7 7 649 #define evr8 8 650 #define evr9 9 651 #define evr10 10 652 #define evr11 11 653 #define evr12 12 654 #define evr13 13 655 #define evr14 14 656 #define evr15 15 657 #define evr16 16 658 #define evr17 17 659 #define evr18 18 660 #define evr19 19 661 #define evr20 20 662 #define evr21 21 663 #define evr22 22 664 #define evr23 23 665 #define evr24 24 666 #define evr25 25 667 #define evr26 26 668 #define evr27 27 669 #define evr28 28 670 #define evr29 29 671 #define evr30 30 672 #define evr31 31 673 674 /* some stab codes */ 675 #define N_FUN 36 676 #define N_RSYM 64 677 #define N_SLINE 68 678 #define N_SO 100 679 680 #endif /* __ASSEMBLY__ */ 681 682 #endif /* _ASM_POWERPC_PPC_ASM_H */ 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