1 /* 2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. 3 */ 4 #ifndef _ASM_POWERPC_PPC_ASM_H 5 #define _ASM_POWERPC_PPC_ASM_H 6 7 #include <linux/stringify.h> 8 #include <asm/asm-compat.h> 9 #include <asm/processor.h> 10 #include <asm/ppc-opcode.h> 11 #include <asm/firmware.h> 12 13 #ifndef __ASSEMBLY__ 14 #error __FILE__ should only be used in assembler files 15 #else 16 17 #define SZL (BITS_PER_LONG/8) 18 19 /* 20 * Stuff for accurate CPU time accounting. 21 * These macros handle transitions between user and system state 22 * in exception entry and exit and accumulate time to the 23 * user_time and system_time fields in the paca. 24 */ 25 26 #ifndef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE 27 #define ACCOUNT_CPU_USER_ENTRY(ra, rb) 28 #define ACCOUNT_CPU_USER_EXIT(ra, rb) 29 #define ACCOUNT_STOLEN_TIME 30 #else 31 #define ACCOUNT_CPU_USER_ENTRY(ra, rb) \ 32 MFTB(ra); /* get timebase */ \ 33 ld rb,PACA_STARTTIME_USER(r13); \ 34 std ra,PACA_STARTTIME(r13); \ 35 subf rb,rb,ra; /* subtract start value */ \ 36 ld ra,PACA_USER_TIME(r13); \ 37 add ra,ra,rb; /* add on to user time */ \ 38 std ra,PACA_USER_TIME(r13); \ 39 40 #define ACCOUNT_CPU_USER_EXIT(ra, rb) \ 41 MFTB(ra); /* get timebase */ \ 42 ld rb,PACA_STARTTIME(r13); \ 43 std ra,PACA_STARTTIME_USER(r13); \ 44 subf rb,rb,ra; /* subtract start value */ \ 45 ld ra,PACA_SYSTEM_TIME(r13); \ 46 add ra,ra,rb; /* add on to system time */ \ 47 std ra,PACA_SYSTEM_TIME(r13) 48 49 #ifdef CONFIG_PPC_SPLPAR 50 #define ACCOUNT_STOLEN_TIME \ 51 BEGIN_FW_FTR_SECTION; \ 52 beq 33f; \ 53 /* from user - see if there are any DTL entries to process */ \ 54 ld r10,PACALPPACAPTR(r13); /* get ptr to VPA */ \ 55 ld r11,PACA_DTL_RIDX(r13); /* get log read index */ \ 56 addi r10,r10,LPPACA_DTLIDX; \ 57 LDX_BE r10,0,r10; /* get log write index */ \ 58 cmpd cr1,r11,r10; \ 59 beq+ cr1,33f; \ 60 bl .accumulate_stolen_time; \ 61 ld r12,_MSR(r1); \ 62 andi. r10,r12,MSR_PR; /* Restore cr0 (coming from user) */ \ 63 33: \ 64 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR) 65 66 #else /* CONFIG_PPC_SPLPAR */ 67 #define ACCOUNT_STOLEN_TIME 68 69 #endif /* CONFIG_PPC_SPLPAR */ 70 71 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */ 72 73 /* 74 * Macros for storing registers into and loading registers from 75 * exception frames. 76 */ 77 #ifdef __powerpc64__ 78 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base) 79 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base) 80 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) 81 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) 82 #else 83 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) 84 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) 85 #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \ 86 SAVE_10GPRS(22, base) 87 #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \ 88 REST_10GPRS(22, base) 89 #endif 90 91 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) 92 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) 93 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) 94 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) 95 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) 96 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) 97 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) 98 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) 99 100 #define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base) 101 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) 102 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) 103 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) 104 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) 105 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) 106 #define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base) 107 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) 108 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) 109 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) 110 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) 111 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) 112 113 #define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b 114 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) 115 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) 116 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) 117 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) 118 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) 119 #define REST_VR(n,b,base) li b,16*(n); lvx n,base,b 120 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) 121 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) 122 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) 123 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) 124 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) 125 126 #ifdef __BIG_ENDIAN__ 127 #define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base) 128 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base) 129 #else 130 #define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \ 131 STXVD2X(n,b,base); \ 132 XXSWAPD(n,n) 133 134 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \ 135 XXSWAPD(n,n) 136 #endif 137 /* Save the lower 32 VSRs in the thread VSR region */ 138 #define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b) 139 #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) 140 #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base) 141 #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base) 142 #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base) 143 #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) 144 #define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b) 145 #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base) 146 #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base) 147 #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base) 148 #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base) 149 #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base) 150 151 /* 152 * b = base register for addressing, o = base offset from register of 1st EVR 153 * n = first EVR, s = scratch 154 */ 155 #define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b) 156 #define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o) 157 #define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o) 158 #define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o) 159 #define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o) 160 #define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o) 161 #define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n 162 #define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o) 163 #define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o) 164 #define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o) 165 #define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o) 166 #define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o) 167 168 /* Macros to adjust thread priority for hardware multithreading */ 169 #define HMT_VERY_LOW or 31,31,31 # very low priority 170 #define HMT_LOW or 1,1,1 171 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority 172 #define HMT_MEDIUM or 2,2,2 173 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority 174 #define HMT_HIGH or 3,3,3 175 #define HMT_EXTRA_HIGH or 7,7,7 # power7 only 176 177 #ifdef CONFIG_PPC64 178 #define ULONG_SIZE 8 179 #else 180 #define ULONG_SIZE 4 181 #endif 182 #define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE)) 183 #define VCPU_GPR(n) __VCPU_GPR(__REG_##n) 184 185 #ifdef __KERNEL__ 186 #ifdef CONFIG_PPC64 187 188 #define STACKFRAMESIZE 256 189 #define __STK_REG(i) (112 + ((i)-14)*8) 190 #define STK_REG(i) __STK_REG(__REG_##i) 191 192 #define __STK_PARAM(i) (48 + ((i)-3)*8) 193 #define STK_PARAM(i) __STK_PARAM(__REG_##i) 194 195 #define XGLUE(a,b) a##b 196 #define GLUE(a,b) XGLUE(a,b) 197 198 #define _GLOBAL(name) \ 199 .section ".text"; \ 200 .align 2 ; \ 201 .globl name; \ 202 .globl GLUE(.,name); \ 203 .section ".opd","aw"; \ 204 name: \ 205 .quad GLUE(.,name); \ 206 .quad .TOC.@tocbase; \ 207 .quad 0; \ 208 .previous; \ 209 .type GLUE(.,name),@function; \ 210 GLUE(.,name): 211 212 #define _INIT_GLOBAL(name) \ 213 __REF; \ 214 .align 2 ; \ 215 .globl name; \ 216 .globl GLUE(.,name); \ 217 .section ".opd","aw"; \ 218 name: \ 219 .quad GLUE(.,name); \ 220 .quad .TOC.@tocbase; \ 221 .quad 0; \ 222 .previous; \ 223 .type GLUE(.,name),@function; \ 224 GLUE(.,name): 225 226 #define _KPROBE(name) \ 227 .section ".kprobes.text","a"; \ 228 .align 2 ; \ 229 .globl name; \ 230 .globl GLUE(.,name); \ 231 .section ".opd","aw"; \ 232 name: \ 233 .quad GLUE(.,name); \ 234 .quad .TOC.@tocbase; \ 235 .quad 0; \ 236 .previous; \ 237 .type GLUE(.,name),@function; \ 238 GLUE(.,name): 239 240 #define _STATIC(name) \ 241 .section ".text"; \ 242 .align 2 ; \ 243 .section ".opd","aw"; \ 244 name: \ 245 .quad GLUE(.,name); \ 246 .quad .TOC.@tocbase; \ 247 .quad 0; \ 248 .previous; \ 249 .type GLUE(.,name),@function; \ 250 GLUE(.,name): 251 252 #define _INIT_STATIC(name) \ 253 __REF; \ 254 .align 2 ; \ 255 .section ".opd","aw"; \ 256 name: \ 257 .quad GLUE(.,name); \ 258 .quad .TOC.@tocbase; \ 259 .quad 0; \ 260 .previous; \ 261 .type GLUE(.,name),@function; \ 262 GLUE(.,name): 263 264 #else /* 32-bit */ 265 266 #define _ENTRY(n) \ 267 .globl n; \ 268 n: 269 270 #define _GLOBAL(n) \ 271 .text; \ 272 .stabs __stringify(n:F-1),N_FUN,0,0,n;\ 273 .globl n; \ 274 n: 275 276 #define _KPROBE(n) \ 277 .section ".kprobes.text","a"; \ 278 .globl n; \ 279 n: 280 281 #endif 282 283 /* 284 * LOAD_REG_IMMEDIATE(rn, expr) 285 * Loads the value of the constant expression 'expr' into register 'rn' 286 * using immediate instructions only. Use this when it's important not 287 * to reference other data (i.e. on ppc64 when the TOC pointer is not 288 * valid) and when 'expr' is a constant or absolute address. 289 * 290 * LOAD_REG_ADDR(rn, name) 291 * Loads the address of label 'name' into register 'rn'. Use this when 292 * you don't particularly need immediate instructions only, but you need 293 * the whole address in one register (e.g. it's a structure address and 294 * you want to access various offsets within it). On ppc32 this is 295 * identical to LOAD_REG_IMMEDIATE. 296 * 297 * LOAD_REG_ADDR_PIC(rn, name) 298 * Loads the address of label 'name' into register 'run'. Use this when 299 * the kernel doesn't run at the linked or relocated address. Please 300 * note that this macro will clobber the lr register. 301 * 302 * LOAD_REG_ADDRBASE(rn, name) 303 * ADDROFF(name) 304 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into 305 * register 'rn'. ADDROFF(name) returns the remainder of the address as 306 * a constant expression. ADDROFF(name) is a signed expression < 16 bits 307 * in size, so is suitable for use directly as an offset in load and store 308 * instructions. Use this when loading/storing a single word or less as: 309 * LOAD_REG_ADDRBASE(rX, name) 310 * ld rY,ADDROFF(name)(rX) 311 */ 312 313 /* Be careful, this will clobber the lr register. */ 314 #define LOAD_REG_ADDR_PIC(reg, name) \ 315 bl 0f; \ 316 0: mflr reg; \ 317 addis reg,reg,(name - 0b)@ha; \ 318 addi reg,reg,(name - 0b)@l; 319 320 #ifdef __powerpc64__ 321 #define LOAD_REG_IMMEDIATE(reg,expr) \ 322 lis reg,(expr)@highest; \ 323 ori reg,reg,(expr)@higher; \ 324 rldicr reg,reg,32,31; \ 325 oris reg,reg,(expr)@h; \ 326 ori reg,reg,(expr)@l; 327 328 #define LOAD_REG_ADDR(reg,name) \ 329 ld reg,name@got(r2) 330 331 #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name) 332 #define ADDROFF(name) 0 333 334 /* offsets for stack frame layout */ 335 #define LRSAVE 16 336 337 #else /* 32-bit */ 338 339 #define LOAD_REG_IMMEDIATE(reg,expr) \ 340 lis reg,(expr)@ha; \ 341 addi reg,reg,(expr)@l; 342 343 #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name) 344 345 #define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha 346 #define ADDROFF(name) name@l 347 348 /* offsets for stack frame layout */ 349 #define LRSAVE 4 350 351 #endif 352 353 /* various errata or part fixups */ 354 #ifdef CONFIG_PPC601_SYNC_FIX 355 #define SYNC \ 356 BEGIN_FTR_SECTION \ 357 sync; \ 358 isync; \ 359 END_FTR_SECTION_IFSET(CPU_FTR_601) 360 #define SYNC_601 \ 361 BEGIN_FTR_SECTION \ 362 sync; \ 363 END_FTR_SECTION_IFSET(CPU_FTR_601) 364 #define ISYNC_601 \ 365 BEGIN_FTR_SECTION \ 366 isync; \ 367 END_FTR_SECTION_IFSET(CPU_FTR_601) 368 #else 369 #define SYNC 370 #define SYNC_601 371 #define ISYNC_601 372 #endif 373 374 #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E) 375 #define MFTB(dest) \ 376 90: mfspr dest, SPRN_TBRL; \ 377 BEGIN_FTR_SECTION_NESTED(96); \ 378 cmpwi dest,0; \ 379 beq- 90b; \ 380 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) 381 #elif defined(CONFIG_8xx) 382 #define MFTB(dest) mftb dest 383 #else 384 #define MFTB(dest) mfspr dest, SPRN_TBRL 385 #endif 386 387 #ifndef CONFIG_SMP 388 #define TLBSYNC 389 #else /* CONFIG_SMP */ 390 /* tlbsync is not implemented on 601 */ 391 #define TLBSYNC \ 392 BEGIN_FTR_SECTION \ 393 tlbsync; \ 394 sync; \ 395 END_FTR_SECTION_IFCLR(CPU_FTR_601) 396 #endif 397 398 #ifdef CONFIG_PPC64 399 #define MTOCRF(FXM, RS) \ 400 BEGIN_FTR_SECTION_NESTED(848); \ 401 mtcrf (FXM), RS; \ 402 FTR_SECTION_ELSE_NESTED(848); \ 403 mtocrf (FXM), RS; \ 404 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848) 405 406 /* 407 * PPR restore macros used in entry_64.S 408 * Used for P7 or later processors 409 */ 410 #define HMT_MEDIUM_LOW_HAS_PPR \ 411 BEGIN_FTR_SECTION_NESTED(944) \ 412 HMT_MEDIUM_LOW; \ 413 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,944) 414 415 #define SET_DEFAULT_THREAD_PPR(ra, rb) \ 416 BEGIN_FTR_SECTION_NESTED(945) \ 417 lis ra,INIT_PPR@highest; /* default ppr=3 */ \ 418 ld rb,PACACURRENT(r13); \ 419 sldi ra,ra,32; /* 11- 13 bits are used for ppr */ \ 420 std ra,TASKTHREADPPR(rb); \ 421 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,945) 422 423 #endif 424 425 /* 426 * This instruction is not implemented on the PPC 603 or 601; however, on 427 * the 403GCX and 405GP tlbia IS defined and tlbie is not. 428 * All of these instructions exist in the 8xx, they have magical powers, 429 * and they must be used. 430 */ 431 432 #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx) 433 #define tlbia \ 434 li r4,1024; \ 435 mtctr r4; \ 436 lis r4,KERNELBASE@h; \ 437 0: tlbie r4; \ 438 addi r4,r4,0x1000; \ 439 bdnz 0b 440 #endif 441 442 443 #ifdef CONFIG_IBM440EP_ERR42 444 #define PPC440EP_ERR42 isync 445 #else 446 #define PPC440EP_ERR42 447 #endif 448 449 /* The following stops all load and store data streams associated with stream 450 * ID (ie. streams created explicitly). The embedded and server mnemonics for 451 * dcbt are different so we use machine "power4" here explicitly. 452 */ 453 #define DCBT_STOP_ALL_STREAM_IDS(scratch) \ 454 .machine push ; \ 455 .machine "power4" ; \ 456 lis scratch,0x60000000@h; \ 457 dcbt r0,scratch,0b01010; \ 458 .machine pop 459 460 /* 461 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them 462 * keep the address intact to be compatible with code shared with 463 * 32-bit classic. 464 * 465 * On the other hand, I find it useful to have them behave as expected 466 * by their name (ie always do the addition) on 64-bit BookE 467 */ 468 #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64) 469 #define toreal(rd) 470 #define fromreal(rd) 471 472 /* 473 * We use addis to ensure compatibility with the "classic" ppc versions of 474 * these macros, which use rs = 0 to get the tophys offset in rd, rather than 475 * converting the address in r0, and so this version has to do that too 476 * (i.e. set register rd to 0 when rs == 0). 477 */ 478 #define tophys(rd,rs) \ 479 addis rd,rs,0 480 481 #define tovirt(rd,rs) \ 482 addis rd,rs,0 483 484 #elif defined(CONFIG_PPC64) 485 #define toreal(rd) /* we can access c000... in real mode */ 486 #define fromreal(rd) 487 488 #define tophys(rd,rs) \ 489 clrldi rd,rs,2 490 491 #define tovirt(rd,rs) \ 492 rotldi rd,rs,16; \ 493 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\ 494 rotldi rd,rd,48 495 #else 496 /* 497 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the 498 * physical base address of RAM at compile time. 499 */ 500 #define toreal(rd) tophys(rd,rd) 501 #define fromreal(rd) tovirt(rd,rd) 502 503 #define tophys(rd,rs) \ 504 0: addis rd,rs,-PAGE_OFFSET@h; \ 505 .section ".vtop_fixup","aw"; \ 506 .align 1; \ 507 .long 0b; \ 508 .previous 509 510 #define tovirt(rd,rs) \ 511 0: addis rd,rs,PAGE_OFFSET@h; \ 512 .section ".ptov_fixup","aw"; \ 513 .align 1; \ 514 .long 0b; \ 515 .previous 516 #endif 517 518 #ifdef CONFIG_PPC_BOOK3S_64 519 #define RFI rfid 520 #define MTMSRD(r) mtmsrd r 521 #define MTMSR_EERI(reg) mtmsrd reg,1 522 #else 523 #define FIX_SRR1(ra, rb) 524 #ifndef CONFIG_40x 525 #define RFI rfi 526 #else 527 #define RFI rfi; b . /* Prevent prefetch past rfi */ 528 #endif 529 #define MTMSRD(r) mtmsr r 530 #define MTMSR_EERI(reg) mtmsr reg 531 #define CLR_TOP32(r) 532 #endif 533 534 #endif /* __KERNEL__ */ 535 536 /* The boring bits... */ 537 538 /* Condition Register Bit Fields */ 539 540 #define cr0 0 541 #define cr1 1 542 #define cr2 2 543 #define cr3 3 544 #define cr4 4 545 #define cr5 5 546 #define cr6 6 547 #define cr7 7 548 549 550 /* 551 * General Purpose Registers (GPRs) 552 * 553 * The lower case r0-r31 should be used in preference to the upper 554 * case R0-R31 as they provide more error checking in the assembler. 555 * Use R0-31 only when really nessesary. 556 */ 557 558 #define r0 %r0 559 #define r1 %r1 560 #define r2 %r2 561 #define r3 %r3 562 #define r4 %r4 563 #define r5 %r5 564 #define r6 %r6 565 #define r7 %r7 566 #define r8 %r8 567 #define r9 %r9 568 #define r10 %r10 569 #define r11 %r11 570 #define r12 %r12 571 #define r13 %r13 572 #define r14 %r14 573 #define r15 %r15 574 #define r16 %r16 575 #define r17 %r17 576 #define r18 %r18 577 #define r19 %r19 578 #define r20 %r20 579 #define r21 %r21 580 #define r22 %r22 581 #define r23 %r23 582 #define r24 %r24 583 #define r25 %r25 584 #define r26 %r26 585 #define r27 %r27 586 #define r28 %r28 587 #define r29 %r29 588 #define r30 %r30 589 #define r31 %r31 590 591 592 /* Floating Point Registers (FPRs) */ 593 594 #define fr0 0 595 #define fr1 1 596 #define fr2 2 597 #define fr3 3 598 #define fr4 4 599 #define fr5 5 600 #define fr6 6 601 #define fr7 7 602 #define fr8 8 603 #define fr9 9 604 #define fr10 10 605 #define fr11 11 606 #define fr12 12 607 #define fr13 13 608 #define fr14 14 609 #define fr15 15 610 #define fr16 16 611 #define fr17 17 612 #define fr18 18 613 #define fr19 19 614 #define fr20 20 615 #define fr21 21 616 #define fr22 22 617 #define fr23 23 618 #define fr24 24 619 #define fr25 25 620 #define fr26 26 621 #define fr27 27 622 #define fr28 28 623 #define fr29 29 624 #define fr30 30 625 #define fr31 31 626 627 /* AltiVec Registers (VPRs) */ 628 629 #define vr0 0 630 #define vr1 1 631 #define vr2 2 632 #define vr3 3 633 #define vr4 4 634 #define vr5 5 635 #define vr6 6 636 #define vr7 7 637 #define vr8 8 638 #define vr9 9 639 #define vr10 10 640 #define vr11 11 641 #define vr12 12 642 #define vr13 13 643 #define vr14 14 644 #define vr15 15 645 #define vr16 16 646 #define vr17 17 647 #define vr18 18 648 #define vr19 19 649 #define vr20 20 650 #define vr21 21 651 #define vr22 22 652 #define vr23 23 653 #define vr24 24 654 #define vr25 25 655 #define vr26 26 656 #define vr27 27 657 #define vr28 28 658 #define vr29 29 659 #define vr30 30 660 #define vr31 31 661 662 /* VSX Registers (VSRs) */ 663 664 #define vsr0 0 665 #define vsr1 1 666 #define vsr2 2 667 #define vsr3 3 668 #define vsr4 4 669 #define vsr5 5 670 #define vsr6 6 671 #define vsr7 7 672 #define vsr8 8 673 #define vsr9 9 674 #define vsr10 10 675 #define vsr11 11 676 #define vsr12 12 677 #define vsr13 13 678 #define vsr14 14 679 #define vsr15 15 680 #define vsr16 16 681 #define vsr17 17 682 #define vsr18 18 683 #define vsr19 19 684 #define vsr20 20 685 #define vsr21 21 686 #define vsr22 22 687 #define vsr23 23 688 #define vsr24 24 689 #define vsr25 25 690 #define vsr26 26 691 #define vsr27 27 692 #define vsr28 28 693 #define vsr29 29 694 #define vsr30 30 695 #define vsr31 31 696 #define vsr32 32 697 #define vsr33 33 698 #define vsr34 34 699 #define vsr35 35 700 #define vsr36 36 701 #define vsr37 37 702 #define vsr38 38 703 #define vsr39 39 704 #define vsr40 40 705 #define vsr41 41 706 #define vsr42 42 707 #define vsr43 43 708 #define vsr44 44 709 #define vsr45 45 710 #define vsr46 46 711 #define vsr47 47 712 #define vsr48 48 713 #define vsr49 49 714 #define vsr50 50 715 #define vsr51 51 716 #define vsr52 52 717 #define vsr53 53 718 #define vsr54 54 719 #define vsr55 55 720 #define vsr56 56 721 #define vsr57 57 722 #define vsr58 58 723 #define vsr59 59 724 #define vsr60 60 725 #define vsr61 61 726 #define vsr62 62 727 #define vsr63 63 728 729 /* SPE Registers (EVPRs) */ 730 731 #define evr0 0 732 #define evr1 1 733 #define evr2 2 734 #define evr3 3 735 #define evr4 4 736 #define evr5 5 737 #define evr6 6 738 #define evr7 7 739 #define evr8 8 740 #define evr9 9 741 #define evr10 10 742 #define evr11 11 743 #define evr12 12 744 #define evr13 13 745 #define evr14 14 746 #define evr15 15 747 #define evr16 16 748 #define evr17 17 749 #define evr18 18 750 #define evr19 19 751 #define evr20 20 752 #define evr21 21 753 #define evr22 22 754 #define evr23 23 755 #define evr24 24 756 #define evr25 25 757 #define evr26 26 758 #define evr27 27 759 #define evr28 28 760 #define evr29 29 761 #define evr30 30 762 #define evr31 31 763 764 /* some stab codes */ 765 #define N_FUN 36 766 #define N_RSYM 64 767 #define N_SLINE 68 768 #define N_SO 100 769 770 /* 771 * Create an endian fixup trampoline 772 * 773 * This starts with a "tdi 0,0,0x48" instruction which is 774 * essentially a "trap never", and thus akin to a nop. 775 * 776 * The opcode for this instruction read with the wrong endian 777 * however results in a b . + 8 778 * 779 * So essentially we use that trick to execute the following 780 * trampoline in "reverse endian" if we are running with the 781 * MSR_LE bit set the "wrong" way for whatever endianness the 782 * kernel is built for. 783 */ 784 785 #ifdef CONFIG_PPC_BOOK3E 786 #define FIXUP_ENDIAN 787 #else 788 #define FIXUP_ENDIAN \ 789 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ 790 b $+36; /* Skip trampoline if endian is good */ \ 791 .long 0x05009f42; /* bcl 20,31,$+4 */ \ 792 .long 0xa602487d; /* mflr r10 */ \ 793 .long 0x1c004a39; /* addi r10,r10,28 */ \ 794 .long 0xa600607d; /* mfmsr r11 */ \ 795 .long 0x01006b69; /* xori r11,r11,1 */ \ 796 .long 0xa6035a7d; /* mtsrr0 r10 */ \ 797 .long 0xa6037b7d; /* mtsrr1 r11 */ \ 798 .long 0x2400004c /* rfid */ 799 #endif /* !CONFIG_PPC_BOOK3E */ 800 #endif /* __ASSEMBLY__ */ 801 #endif /* _ASM_POWERPC_PPC_ASM_H */ 802