1 /* 2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. 3 */ 4 #ifndef _ASM_POWERPC_PPC_ASM_H 5 #define _ASM_POWERPC_PPC_ASM_H 6 7 #include <linux/stringify.h> 8 #include <asm/asm-compat.h> 9 #include <asm/processor.h> 10 #include <asm/ppc-opcode.h> 11 #include <asm/firmware.h> 12 13 #ifndef __ASSEMBLY__ 14 #error __FILE__ should only be used in assembler files 15 #else 16 17 #define SZL (BITS_PER_LONG/8) 18 19 /* 20 * Stuff for accurate CPU time accounting. 21 * These macros handle transitions between user and system state 22 * in exception entry and exit and accumulate time to the 23 * user_time and system_time fields in the paca. 24 */ 25 26 #ifndef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE 27 #define ACCOUNT_CPU_USER_ENTRY(ptr, ra, rb) 28 #define ACCOUNT_CPU_USER_EXIT(ptr, ra, rb) 29 #define ACCOUNT_STOLEN_TIME 30 #else 31 #define ACCOUNT_CPU_USER_ENTRY(ptr, ra, rb) \ 32 MFTB(ra); /* get timebase */ \ 33 PPC_LL rb, ACCOUNT_STARTTIME_USER(ptr); \ 34 PPC_STL ra, ACCOUNT_STARTTIME(ptr); \ 35 subf rb,rb,ra; /* subtract start value */ \ 36 PPC_LL ra, ACCOUNT_USER_TIME(ptr); \ 37 add ra,ra,rb; /* add on to user time */ \ 38 PPC_STL ra, ACCOUNT_USER_TIME(ptr); \ 39 40 #define ACCOUNT_CPU_USER_EXIT(ptr, ra, rb) \ 41 MFTB(ra); /* get timebase */ \ 42 PPC_LL rb, ACCOUNT_STARTTIME(ptr); \ 43 PPC_STL ra, ACCOUNT_STARTTIME_USER(ptr); \ 44 subf rb,rb,ra; /* subtract start value */ \ 45 PPC_LL ra, ACCOUNT_SYSTEM_TIME(ptr); \ 46 add ra,ra,rb; /* add on to system time */ \ 47 PPC_STL ra, ACCOUNT_SYSTEM_TIME(ptr) 48 49 #ifdef CONFIG_PPC_SPLPAR 50 #define ACCOUNT_STOLEN_TIME \ 51 BEGIN_FW_FTR_SECTION; \ 52 beq 33f; \ 53 /* from user - see if there are any DTL entries to process */ \ 54 ld r10,PACALPPACAPTR(r13); /* get ptr to VPA */ \ 55 ld r11,PACA_DTL_RIDX(r13); /* get log read index */ \ 56 addi r10,r10,LPPACA_DTLIDX; \ 57 LDX_BE r10,0,r10; /* get log write index */ \ 58 cmpd cr1,r11,r10; \ 59 beq+ cr1,33f; \ 60 bl accumulate_stolen_time; \ 61 ld r12,_MSR(r1); \ 62 andi. r10,r12,MSR_PR; /* Restore cr0 (coming from user) */ \ 63 33: \ 64 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR) 65 66 #else /* CONFIG_PPC_SPLPAR */ 67 #define ACCOUNT_STOLEN_TIME 68 69 #endif /* CONFIG_PPC_SPLPAR */ 70 71 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */ 72 73 /* 74 * Macros for storing registers into and loading registers from 75 * exception frames. 76 */ 77 #ifdef __powerpc64__ 78 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base) 79 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base) 80 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) 81 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) 82 #else 83 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) 84 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) 85 #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \ 86 SAVE_10GPRS(22, base) 87 #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \ 88 REST_10GPRS(22, base) 89 #endif 90 91 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) 92 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) 93 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) 94 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) 95 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) 96 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) 97 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) 98 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) 99 100 #define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base) 101 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) 102 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) 103 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) 104 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) 105 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) 106 #define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base) 107 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) 108 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) 109 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) 110 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) 111 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) 112 113 #define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b 114 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) 115 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) 116 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) 117 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) 118 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) 119 #define REST_VR(n,b,base) li b,16*(n); lvx n,base,b 120 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) 121 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) 122 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) 123 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) 124 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) 125 126 #ifdef __BIG_ENDIAN__ 127 #define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base) 128 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base) 129 #else 130 #define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \ 131 STXVD2X(n,b,base); \ 132 XXSWAPD(n,n) 133 134 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \ 135 XXSWAPD(n,n) 136 #endif 137 /* Save the lower 32 VSRs in the thread VSR region */ 138 #define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b) 139 #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) 140 #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base) 141 #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base) 142 #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base) 143 #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) 144 #define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b) 145 #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base) 146 #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base) 147 #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base) 148 #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base) 149 #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base) 150 151 /* 152 * b = base register for addressing, o = base offset from register of 1st EVR 153 * n = first EVR, s = scratch 154 */ 155 #define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b) 156 #define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o) 157 #define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o) 158 #define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o) 159 #define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o) 160 #define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o) 161 #define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n 162 #define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o) 163 #define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o) 164 #define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o) 165 #define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o) 166 #define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o) 167 168 /* Macros to adjust thread priority for hardware multithreading */ 169 #define HMT_VERY_LOW or 31,31,31 # very low priority 170 #define HMT_LOW or 1,1,1 171 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority 172 #define HMT_MEDIUM or 2,2,2 173 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority 174 #define HMT_HIGH or 3,3,3 175 #define HMT_EXTRA_HIGH or 7,7,7 # power7 only 176 177 #ifdef CONFIG_PPC64 178 #define ULONG_SIZE 8 179 #else 180 #define ULONG_SIZE 4 181 #endif 182 #define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE)) 183 #define VCPU_GPR(n) __VCPU_GPR(__REG_##n) 184 185 #ifdef __KERNEL__ 186 #ifdef CONFIG_PPC64 187 188 #define STACKFRAMESIZE 256 189 #define __STK_REG(i) (112 + ((i)-14)*8) 190 #define STK_REG(i) __STK_REG(__REG_##i) 191 192 #ifdef PPC64_ELF_ABI_v2 193 #define STK_GOT 24 194 #define __STK_PARAM(i) (32 + ((i)-3)*8) 195 #else 196 #define STK_GOT 40 197 #define __STK_PARAM(i) (48 + ((i)-3)*8) 198 #endif 199 #define STK_PARAM(i) __STK_PARAM(__REG_##i) 200 201 #ifdef PPC64_ELF_ABI_v2 202 203 #define _GLOBAL(name) \ 204 .align 2 ; \ 205 .type name,@function; \ 206 .globl name; \ 207 name: 208 209 #define _GLOBAL_TOC(name) \ 210 .align 2 ; \ 211 .type name,@function; \ 212 .globl name; \ 213 name: \ 214 0: addis r2,r12,(.TOC.-0b)@ha; \ 215 addi r2,r2,(.TOC.-0b)@l; \ 216 .localentry name,.-name 217 218 #define DOTSYM(a) a 219 220 #else 221 222 #define XGLUE(a,b) a##b 223 #define GLUE(a,b) XGLUE(a,b) 224 225 #define _GLOBAL(name) \ 226 .align 2 ; \ 227 .globl name; \ 228 .globl GLUE(.,name); \ 229 .pushsection ".opd","aw"; \ 230 name: \ 231 .quad GLUE(.,name); \ 232 .quad .TOC.@tocbase; \ 233 .quad 0; \ 234 .popsection; \ 235 .type GLUE(.,name),@function; \ 236 GLUE(.,name): 237 238 #define _GLOBAL_TOC(name) _GLOBAL(name) 239 240 #define DOTSYM(a) GLUE(.,a) 241 242 #endif 243 244 #else /* 32-bit */ 245 246 #define _ENTRY(n) \ 247 .globl n; \ 248 n: 249 250 #define _GLOBAL(n) \ 251 .stabs __stringify(n:F-1),N_FUN,0,0,n;\ 252 .globl n; \ 253 n: 254 255 #define _GLOBAL_TOC(name) _GLOBAL(name) 256 257 #endif 258 259 /* 260 * __kprobes (the C annotation) puts the symbol into the .kprobes.text 261 * section, which gets emitted at the end of regular text. 262 * 263 * _ASM_NOKPROBE_SYMBOL and NOKPROBE_SYMBOL just adds the symbol to 264 * a blacklist. The former is for core kprobe functions/data, the 265 * latter is for those that incdentially must be excluded from probing 266 * and allows them to be linked at more optimal location within text. 267 */ 268 #define _ASM_NOKPROBE_SYMBOL(entry) \ 269 .pushsection "_kprobe_blacklist","aw"; \ 270 PPC_LONG (entry) ; \ 271 .popsection 272 273 #define FUNC_START(name) _GLOBAL(name) 274 #define FUNC_END(name) 275 276 /* 277 * LOAD_REG_IMMEDIATE(rn, expr) 278 * Loads the value of the constant expression 'expr' into register 'rn' 279 * using immediate instructions only. Use this when it's important not 280 * to reference other data (i.e. on ppc64 when the TOC pointer is not 281 * valid) and when 'expr' is a constant or absolute address. 282 * 283 * LOAD_REG_ADDR(rn, name) 284 * Loads the address of label 'name' into register 'rn'. Use this when 285 * you don't particularly need immediate instructions only, but you need 286 * the whole address in one register (e.g. it's a structure address and 287 * you want to access various offsets within it). On ppc32 this is 288 * identical to LOAD_REG_IMMEDIATE. 289 * 290 * LOAD_REG_ADDR_PIC(rn, name) 291 * Loads the address of label 'name' into register 'run'. Use this when 292 * the kernel doesn't run at the linked or relocated address. Please 293 * note that this macro will clobber the lr register. 294 * 295 * LOAD_REG_ADDRBASE(rn, name) 296 * ADDROFF(name) 297 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into 298 * register 'rn'. ADDROFF(name) returns the remainder of the address as 299 * a constant expression. ADDROFF(name) is a signed expression < 16 bits 300 * in size, so is suitable for use directly as an offset in load and store 301 * instructions. Use this when loading/storing a single word or less as: 302 * LOAD_REG_ADDRBASE(rX, name) 303 * ld rY,ADDROFF(name)(rX) 304 */ 305 306 /* Be careful, this will clobber the lr register. */ 307 #define LOAD_REG_ADDR_PIC(reg, name) \ 308 bl 0f; \ 309 0: mflr reg; \ 310 addis reg,reg,(name - 0b)@ha; \ 311 addi reg,reg,(name - 0b)@l; 312 313 #ifdef __powerpc64__ 314 #ifdef HAVE_AS_ATHIGH 315 #define __AS_ATHIGH high 316 #else 317 #define __AS_ATHIGH h 318 #endif 319 #define LOAD_REG_IMMEDIATE(reg,expr) \ 320 lis reg,(expr)@highest; \ 321 ori reg,reg,(expr)@higher; \ 322 rldicr reg,reg,32,31; \ 323 oris reg,reg,(expr)@__AS_ATHIGH; \ 324 ori reg,reg,(expr)@l; 325 326 #define LOAD_REG_ADDR(reg,name) \ 327 ld reg,name@got(r2) 328 329 #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name) 330 #define ADDROFF(name) 0 331 332 /* offsets for stack frame layout */ 333 #define LRSAVE 16 334 335 #else /* 32-bit */ 336 337 #define LOAD_REG_IMMEDIATE(reg,expr) \ 338 lis reg,(expr)@ha; \ 339 addi reg,reg,(expr)@l; 340 341 #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name) 342 343 #define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha 344 #define ADDROFF(name) name@l 345 346 /* offsets for stack frame layout */ 347 #define LRSAVE 4 348 349 #endif 350 351 /* various errata or part fixups */ 352 #ifdef CONFIG_PPC601_SYNC_FIX 353 #define SYNC \ 354 BEGIN_FTR_SECTION \ 355 sync; \ 356 isync; \ 357 END_FTR_SECTION_IFSET(CPU_FTR_601) 358 #define SYNC_601 \ 359 BEGIN_FTR_SECTION \ 360 sync; \ 361 END_FTR_SECTION_IFSET(CPU_FTR_601) 362 #define ISYNC_601 \ 363 BEGIN_FTR_SECTION \ 364 isync; \ 365 END_FTR_SECTION_IFSET(CPU_FTR_601) 366 #else 367 #define SYNC 368 #define SYNC_601 369 #define ISYNC_601 370 #endif 371 372 #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E) 373 #define MFTB(dest) \ 374 90: mfspr dest, SPRN_TBRL; \ 375 BEGIN_FTR_SECTION_NESTED(96); \ 376 cmpwi dest,0; \ 377 beq- 90b; \ 378 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) 379 #elif defined(CONFIG_8xx) 380 #define MFTB(dest) mftb dest 381 #else 382 #define MFTB(dest) mfspr dest, SPRN_TBRL 383 #endif 384 385 #ifndef CONFIG_SMP 386 #define TLBSYNC 387 #else /* CONFIG_SMP */ 388 /* tlbsync is not implemented on 601 */ 389 #define TLBSYNC \ 390 BEGIN_FTR_SECTION \ 391 tlbsync; \ 392 sync; \ 393 END_FTR_SECTION_IFCLR(CPU_FTR_601) 394 #endif 395 396 #ifdef CONFIG_PPC64 397 #define MTOCRF(FXM, RS) \ 398 BEGIN_FTR_SECTION_NESTED(848); \ 399 mtcrf (FXM), RS; \ 400 FTR_SECTION_ELSE_NESTED(848); \ 401 mtocrf (FXM), RS; \ 402 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848) 403 #endif 404 405 /* 406 * This instruction is not implemented on the PPC 603 or 601; however, on 407 * the 403GCX and 405GP tlbia IS defined and tlbie is not. 408 * All of these instructions exist in the 8xx, they have magical powers, 409 * and they must be used. 410 */ 411 412 #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx) 413 #define tlbia \ 414 li r4,1024; \ 415 mtctr r4; \ 416 lis r4,KERNELBASE@h; \ 417 .machine push; \ 418 .machine "power4"; \ 419 0: tlbie r4; \ 420 .machine pop; \ 421 addi r4,r4,0x1000; \ 422 bdnz 0b 423 #endif 424 425 426 #ifdef CONFIG_IBM440EP_ERR42 427 #define PPC440EP_ERR42 isync 428 #else 429 #define PPC440EP_ERR42 430 #endif 431 432 /* The following stops all load and store data streams associated with stream 433 * ID (ie. streams created explicitly). The embedded and server mnemonics for 434 * dcbt are different so we use machine "power4" here explicitly. 435 */ 436 #define DCBT_STOP_ALL_STREAM_IDS(scratch) \ 437 .machine push ; \ 438 .machine "power4" ; \ 439 lis scratch,0x60000000@h; \ 440 dcbt r0,scratch,0b01010; \ 441 .machine pop 442 443 /* 444 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them 445 * keep the address intact to be compatible with code shared with 446 * 32-bit classic. 447 * 448 * On the other hand, I find it useful to have them behave as expected 449 * by their name (ie always do the addition) on 64-bit BookE 450 */ 451 #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64) 452 #define toreal(rd) 453 #define fromreal(rd) 454 455 /* 456 * We use addis to ensure compatibility with the "classic" ppc versions of 457 * these macros, which use rs = 0 to get the tophys offset in rd, rather than 458 * converting the address in r0, and so this version has to do that too 459 * (i.e. set register rd to 0 when rs == 0). 460 */ 461 #define tophys(rd,rs) \ 462 addis rd,rs,0 463 464 #define tovirt(rd,rs) \ 465 addis rd,rs,0 466 467 #elif defined(CONFIG_PPC64) 468 #define toreal(rd) /* we can access c000... in real mode */ 469 #define fromreal(rd) 470 471 #define tophys(rd,rs) \ 472 clrldi rd,rs,2 473 474 #define tovirt(rd,rs) \ 475 rotldi rd,rs,16; \ 476 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\ 477 rotldi rd,rd,48 478 #else 479 /* 480 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the 481 * physical base address of RAM at compile time. 482 */ 483 #define toreal(rd) tophys(rd,rd) 484 #define fromreal(rd) tovirt(rd,rd) 485 486 #define tophys(rd,rs) \ 487 0: addis rd,rs,-PAGE_OFFSET@h; \ 488 .section ".vtop_fixup","aw"; \ 489 .align 1; \ 490 .long 0b; \ 491 .previous 492 493 #define tovirt(rd,rs) \ 494 0: addis rd,rs,PAGE_OFFSET@h; \ 495 .section ".ptov_fixup","aw"; \ 496 .align 1; \ 497 .long 0b; \ 498 .previous 499 #endif 500 501 #ifdef CONFIG_PPC_BOOK3S_64 502 #define RFI rfid 503 #define MTMSRD(r) mtmsrd r 504 #define MTMSR_EERI(reg) mtmsrd reg,1 505 #else 506 #define FIX_SRR1(ra, rb) 507 #ifndef CONFIG_40x 508 #define RFI rfi 509 #else 510 #define RFI rfi; b . /* Prevent prefetch past rfi */ 511 #endif 512 #define MTMSRD(r) mtmsr r 513 #define MTMSR_EERI(reg) mtmsr reg 514 #endif 515 516 #endif /* __KERNEL__ */ 517 518 /* The boring bits... */ 519 520 /* Condition Register Bit Fields */ 521 522 #define cr0 0 523 #define cr1 1 524 #define cr2 2 525 #define cr3 3 526 #define cr4 4 527 #define cr5 5 528 #define cr6 6 529 #define cr7 7 530 531 532 /* 533 * General Purpose Registers (GPRs) 534 * 535 * The lower case r0-r31 should be used in preference to the upper 536 * case R0-R31 as they provide more error checking in the assembler. 537 * Use R0-31 only when really nessesary. 538 */ 539 540 #define r0 %r0 541 #define r1 %r1 542 #define r2 %r2 543 #define r3 %r3 544 #define r4 %r4 545 #define r5 %r5 546 #define r6 %r6 547 #define r7 %r7 548 #define r8 %r8 549 #define r9 %r9 550 #define r10 %r10 551 #define r11 %r11 552 #define r12 %r12 553 #define r13 %r13 554 #define r14 %r14 555 #define r15 %r15 556 #define r16 %r16 557 #define r17 %r17 558 #define r18 %r18 559 #define r19 %r19 560 #define r20 %r20 561 #define r21 %r21 562 #define r22 %r22 563 #define r23 %r23 564 #define r24 %r24 565 #define r25 %r25 566 #define r26 %r26 567 #define r27 %r27 568 #define r28 %r28 569 #define r29 %r29 570 #define r30 %r30 571 #define r31 %r31 572 573 574 /* Floating Point Registers (FPRs) */ 575 576 #define fr0 0 577 #define fr1 1 578 #define fr2 2 579 #define fr3 3 580 #define fr4 4 581 #define fr5 5 582 #define fr6 6 583 #define fr7 7 584 #define fr8 8 585 #define fr9 9 586 #define fr10 10 587 #define fr11 11 588 #define fr12 12 589 #define fr13 13 590 #define fr14 14 591 #define fr15 15 592 #define fr16 16 593 #define fr17 17 594 #define fr18 18 595 #define fr19 19 596 #define fr20 20 597 #define fr21 21 598 #define fr22 22 599 #define fr23 23 600 #define fr24 24 601 #define fr25 25 602 #define fr26 26 603 #define fr27 27 604 #define fr28 28 605 #define fr29 29 606 #define fr30 30 607 #define fr31 31 608 609 /* AltiVec Registers (VPRs) */ 610 611 #define v0 0 612 #define v1 1 613 #define v2 2 614 #define v3 3 615 #define v4 4 616 #define v5 5 617 #define v6 6 618 #define v7 7 619 #define v8 8 620 #define v9 9 621 #define v10 10 622 #define v11 11 623 #define v12 12 624 #define v13 13 625 #define v14 14 626 #define v15 15 627 #define v16 16 628 #define v17 17 629 #define v18 18 630 #define v19 19 631 #define v20 20 632 #define v21 21 633 #define v22 22 634 #define v23 23 635 #define v24 24 636 #define v25 25 637 #define v26 26 638 #define v27 27 639 #define v28 28 640 #define v29 29 641 #define v30 30 642 #define v31 31 643 644 /* VSX Registers (VSRs) */ 645 646 #define vs0 0 647 #define vs1 1 648 #define vs2 2 649 #define vs3 3 650 #define vs4 4 651 #define vs5 5 652 #define vs6 6 653 #define vs7 7 654 #define vs8 8 655 #define vs9 9 656 #define vs10 10 657 #define vs11 11 658 #define vs12 12 659 #define vs13 13 660 #define vs14 14 661 #define vs15 15 662 #define vs16 16 663 #define vs17 17 664 #define vs18 18 665 #define vs19 19 666 #define vs20 20 667 #define vs21 21 668 #define vs22 22 669 #define vs23 23 670 #define vs24 24 671 #define vs25 25 672 #define vs26 26 673 #define vs27 27 674 #define vs28 28 675 #define vs29 29 676 #define vs30 30 677 #define vs31 31 678 #define vs32 32 679 #define vs33 33 680 #define vs34 34 681 #define vs35 35 682 #define vs36 36 683 #define vs37 37 684 #define vs38 38 685 #define vs39 39 686 #define vs40 40 687 #define vs41 41 688 #define vs42 42 689 #define vs43 43 690 #define vs44 44 691 #define vs45 45 692 #define vs46 46 693 #define vs47 47 694 #define vs48 48 695 #define vs49 49 696 #define vs50 50 697 #define vs51 51 698 #define vs52 52 699 #define vs53 53 700 #define vs54 54 701 #define vs55 55 702 #define vs56 56 703 #define vs57 57 704 #define vs58 58 705 #define vs59 59 706 #define vs60 60 707 #define vs61 61 708 #define vs62 62 709 #define vs63 63 710 711 /* SPE Registers (EVPRs) */ 712 713 #define evr0 0 714 #define evr1 1 715 #define evr2 2 716 #define evr3 3 717 #define evr4 4 718 #define evr5 5 719 #define evr6 6 720 #define evr7 7 721 #define evr8 8 722 #define evr9 9 723 #define evr10 10 724 #define evr11 11 725 #define evr12 12 726 #define evr13 13 727 #define evr14 14 728 #define evr15 15 729 #define evr16 16 730 #define evr17 17 731 #define evr18 18 732 #define evr19 19 733 #define evr20 20 734 #define evr21 21 735 #define evr22 22 736 #define evr23 23 737 #define evr24 24 738 #define evr25 25 739 #define evr26 26 740 #define evr27 27 741 #define evr28 28 742 #define evr29 29 743 #define evr30 30 744 #define evr31 31 745 746 /* some stab codes */ 747 #define N_FUN 36 748 #define N_RSYM 64 749 #define N_SLINE 68 750 #define N_SO 100 751 752 /* 753 * Create an endian fixup trampoline 754 * 755 * This starts with a "tdi 0,0,0x48" instruction which is 756 * essentially a "trap never", and thus akin to a nop. 757 * 758 * The opcode for this instruction read with the wrong endian 759 * however results in a b . + 8 760 * 761 * So essentially we use that trick to execute the following 762 * trampoline in "reverse endian" if we are running with the 763 * MSR_LE bit set the "wrong" way for whatever endianness the 764 * kernel is built for. 765 */ 766 767 #ifdef CONFIG_PPC_BOOK3E 768 #define FIXUP_ENDIAN 769 #else 770 #define FIXUP_ENDIAN \ 771 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ 772 b $+36; /* Skip trampoline if endian is good */ \ 773 .long 0x05009f42; /* bcl 20,31,$+4 */ \ 774 .long 0xa602487d; /* mflr r10 */ \ 775 .long 0x1c004a39; /* addi r10,r10,28 */ \ 776 .long 0xa600607d; /* mfmsr r11 */ \ 777 .long 0x01006b69; /* xori r11,r11,1 */ \ 778 .long 0xa6035a7d; /* mtsrr0 r10 */ \ 779 .long 0xa6037b7d; /* mtsrr1 r11 */ \ 780 .long 0x2400004c /* rfid */ 781 #endif /* !CONFIG_PPC_BOOK3E */ 782 #endif /* __ASSEMBLY__ */ 783 #endif /* _ASM_POWERPC_PPC_ASM_H */ 784