1 /* 2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. 3 */ 4 #ifndef _ASM_POWERPC_PPC_ASM_H 5 #define _ASM_POWERPC_PPC_ASM_H 6 7 #include <linux/stringify.h> 8 #include <asm/asm-compat.h> 9 #include <asm/processor.h> 10 #include <asm/ppc-opcode.h> 11 #include <asm/firmware.h> 12 #include <asm/feature-fixups.h> 13 #include <asm/extable.h> 14 15 #ifdef __ASSEMBLY__ 16 17 #define SZL (BITS_PER_LONG/8) 18 19 /* 20 * This expands to a sequence of operations with reg incrementing from 21 * start to end inclusive, of this form: 22 * 23 * op reg, (offset + (width * reg))(base) 24 * 25 * Note that offset is not the offset of the first operation unless start 26 * is zero (or width is zero). 27 */ 28 .macro OP_REGS op, width, start, end, base, offset 29 .Lreg=\start 30 .rept (\end - \start + 1) 31 \op .Lreg, \offset + \width * .Lreg(\base) 32 .Lreg=.Lreg+1 33 .endr 34 .endm 35 36 /* 37 * This expands to a sequence of register clears for regs start to end 38 * inclusive, of the form: 39 * 40 * li rN, 0 41 */ 42 .macro ZEROIZE_REGS start, end 43 .Lreg=\start 44 .rept (\end - \start + 1) 45 li .Lreg, 0 46 .Lreg=.Lreg+1 47 .endr 48 .endm 49 50 /* 51 * Macros for storing registers into and loading registers from 52 * exception frames. 53 */ 54 #ifdef __powerpc64__ 55 #define SAVE_GPRS(start, end, base) OP_REGS std, 8, start, end, base, GPR0 56 #define REST_GPRS(start, end, base) OP_REGS ld, 8, start, end, base, GPR0 57 #define SAVE_NVGPRS(base) SAVE_GPRS(14, 31, base) 58 #define REST_NVGPRS(base) REST_GPRS(14, 31, base) 59 #else 60 #define SAVE_GPRS(start, end, base) OP_REGS stw, 4, start, end, base, GPR0 61 #define REST_GPRS(start, end, base) OP_REGS lwz, 4, start, end, base, GPR0 62 #define SAVE_NVGPRS(base) SAVE_GPRS(13, 31, base) 63 #define REST_NVGPRS(base) REST_GPRS(13, 31, base) 64 #endif 65 66 #define ZEROIZE_GPRS(start, end) ZEROIZE_REGS start, end 67 #ifdef __powerpc64__ 68 #define ZEROIZE_NVGPRS() ZEROIZE_GPRS(14, 31) 69 #else 70 #define ZEROIZE_NVGPRS() ZEROIZE_GPRS(13, 31) 71 #endif 72 #define ZEROIZE_GPR(n) ZEROIZE_GPRS(n, n) 73 74 #define SAVE_GPR(n, base) SAVE_GPRS(n, n, base) 75 #define REST_GPR(n, base) REST_GPRS(n, n, base) 76 77 /* macros for handling user register sanitisation */ 78 #ifdef CONFIG_INTERRUPT_SANITIZE_REGISTERS 79 #define SANITIZE_SYSCALL_GPRS() ZEROIZE_GPR(0); \ 80 ZEROIZE_GPRS(5, 12); \ 81 ZEROIZE_NVGPRS() 82 #define SANITIZE_GPR(n) ZEROIZE_GPR(n) 83 #define SANITIZE_GPRS(start, end) ZEROIZE_GPRS(start, end) 84 #define SANITIZE_NVGPRS() ZEROIZE_NVGPRS() 85 #define SANITIZE_RESTORE_NVGPRS() REST_NVGPRS(r1) 86 #define HANDLER_RESTORE_NVGPRS() 87 #else 88 #define SANITIZE_SYSCALL_GPRS() 89 #define SANITIZE_GPR(n) 90 #define SANITIZE_GPRS(start, end) 91 #define SANITIZE_NVGPRS() 92 #define SANITIZE_RESTORE_NVGPRS() 93 #define HANDLER_RESTORE_NVGPRS() REST_NVGPRS(r1) 94 #endif /* CONFIG_INTERRUPT_SANITIZE_REGISTERS */ 95 96 #define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base) 97 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) 98 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) 99 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) 100 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) 101 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) 102 #define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base) 103 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) 104 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) 105 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) 106 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) 107 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) 108 109 #define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b 110 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) 111 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) 112 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) 113 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) 114 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) 115 #define REST_VR(n,b,base) li b,16*(n); lvx n,base,b 116 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) 117 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) 118 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) 119 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) 120 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) 121 122 #ifdef __BIG_ENDIAN__ 123 #define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base) 124 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base) 125 #else 126 #define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \ 127 STXVD2X(n,b,base); \ 128 XXSWAPD(n,n) 129 130 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \ 131 XXSWAPD(n,n) 132 #endif 133 /* Save the lower 32 VSRs in the thread VSR region */ 134 #define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b) 135 #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) 136 #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base) 137 #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base) 138 #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base) 139 #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) 140 #define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b) 141 #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base) 142 #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base) 143 #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base) 144 #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base) 145 #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base) 146 147 /* 148 * b = base register for addressing, o = base offset from register of 1st EVR 149 * n = first EVR, s = scratch 150 */ 151 #define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b) 152 #define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o) 153 #define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o) 154 #define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o) 155 #define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o) 156 #define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o) 157 #define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n 158 #define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o) 159 #define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o) 160 #define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o) 161 #define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o) 162 #define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o) 163 164 /* Macros to adjust thread priority for hardware multithreading */ 165 #define HMT_VERY_LOW or 31,31,31 # very low priority 166 #define HMT_LOW or 1,1,1 167 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority 168 #define HMT_MEDIUM or 2,2,2 169 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority 170 #define HMT_HIGH or 3,3,3 171 #define HMT_EXTRA_HIGH or 7,7,7 # power7 only 172 173 #ifdef CONFIG_PPC64 174 #define ULONG_SIZE 8 175 #else 176 #define ULONG_SIZE 4 177 #endif 178 #define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE)) 179 #define VCPU_GPR(n) __VCPU_GPR(__REG_##n) 180 181 #ifdef __KERNEL__ 182 183 /* 184 * Used to name C functions called from asm 185 */ 186 #ifdef CONFIG_PPC_KERNEL_PCREL 187 #define CFUNC(name) name@notoc 188 #else 189 #define CFUNC(name) name 190 #endif 191 192 /* 193 * We use __powerpc64__ here because we want the compat VDSO to use the 32-bit 194 * version below in the else case of the ifdef. 195 */ 196 #ifdef __powerpc64__ 197 198 #define STACKFRAMESIZE 256 199 #define __STK_REG(i) (112 + ((i)-14)*8) 200 #define STK_REG(i) __STK_REG(__REG_##i) 201 202 #ifdef CONFIG_PPC64_ELF_ABI_V2 203 #define STK_GOT 24 204 #define __STK_PARAM(i) (32 + ((i)-3)*8) 205 #else 206 #define STK_GOT 40 207 #define __STK_PARAM(i) (48 + ((i)-3)*8) 208 #endif 209 #define STK_PARAM(i) __STK_PARAM(__REG_##i) 210 211 #ifdef CONFIG_PPC64_ELF_ABI_V2 212 213 #define _GLOBAL(name) \ 214 .align 2 ; \ 215 .type name,@function; \ 216 .globl name; \ 217 name: 218 219 #ifdef CONFIG_PPC_KERNEL_PCREL 220 #define _GLOBAL_TOC _GLOBAL 221 #else 222 #define _GLOBAL_TOC(name) \ 223 .align 2 ; \ 224 .type name,@function; \ 225 .globl name; \ 226 name: \ 227 0: addis r2,r12,(.TOC.-0b)@ha; \ 228 addi r2,r2,(.TOC.-0b)@l; \ 229 .localentry name,.-name 230 #endif 231 232 #define DOTSYM(a) a 233 234 #else 235 236 #define XGLUE(a,b) a##b 237 #define GLUE(a,b) XGLUE(a,b) 238 239 #define _GLOBAL(name) \ 240 .align 2 ; \ 241 .globl name; \ 242 .globl GLUE(.,name); \ 243 .pushsection ".opd","aw"; \ 244 name: \ 245 .quad GLUE(.,name); \ 246 .quad .TOC.@tocbase; \ 247 .quad 0; \ 248 .popsection; \ 249 .type GLUE(.,name),@function; \ 250 GLUE(.,name): 251 252 #define _GLOBAL_TOC(name) _GLOBAL(name) 253 254 #define DOTSYM(a) GLUE(.,a) 255 256 #endif 257 258 #else /* 32-bit */ 259 260 #define _GLOBAL(n) \ 261 .globl n; \ 262 n: 263 264 #define _GLOBAL_TOC(name) _GLOBAL(name) 265 266 #define DOTSYM(a) a 267 268 #endif 269 270 /* 271 * __kprobes (the C annotation) puts the symbol into the .kprobes.text 272 * section, which gets emitted at the end of regular text. 273 * 274 * _ASM_NOKPROBE_SYMBOL and NOKPROBE_SYMBOL just adds the symbol to 275 * a blacklist. The former is for core kprobe functions/data, the 276 * latter is for those that incdentially must be excluded from probing 277 * and allows them to be linked at more optimal location within text. 278 */ 279 #ifdef CONFIG_KPROBES 280 #define _ASM_NOKPROBE_SYMBOL(entry) \ 281 .pushsection "_kprobe_blacklist","aw"; \ 282 PPC_LONG (entry) ; \ 283 .popsection 284 #else 285 #define _ASM_NOKPROBE_SYMBOL(entry) 286 #endif 287 288 #define FUNC_START(name) _GLOBAL(name) 289 #define FUNC_END(name) 290 291 /* 292 * LOAD_REG_IMMEDIATE(rn, expr) 293 * Loads the value of the constant expression 'expr' into register 'rn' 294 * using immediate instructions only. Use this when it's important not 295 * to reference other data (i.e. on ppc64 when the TOC pointer is not 296 * valid) and when 'expr' is a constant or absolute address. 297 * 298 * LOAD_REG_ADDR(rn, name) 299 * Loads the address of label 'name' into register 'rn'. Use this when 300 * you don't particularly need immediate instructions only, but you need 301 * the whole address in one register (e.g. it's a structure address and 302 * you want to access various offsets within it). On ppc32 this is 303 * identical to LOAD_REG_IMMEDIATE. 304 * 305 * LOAD_REG_ADDR_PIC(rn, name) 306 * Loads the address of label 'name' into register 'run'. Use this when 307 * the kernel doesn't run at the linked or relocated address. Please 308 * note that this macro will clobber the lr register. 309 * 310 * LOAD_REG_ADDRBASE(rn, name) 311 * ADDROFF(name) 312 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into 313 * register 'rn'. ADDROFF(name) returns the remainder of the address as 314 * a constant expression. ADDROFF(name) is a signed expression < 16 bits 315 * in size, so is suitable for use directly as an offset in load and store 316 * instructions. Use this when loading/storing a single word or less as: 317 * LOAD_REG_ADDRBASE(rX, name) 318 * ld rY,ADDROFF(name)(rX) 319 */ 320 321 /* Be careful, this will clobber the lr register. */ 322 #define LOAD_REG_ADDR_PIC(reg, name) \ 323 bcl 20,31,$+4; \ 324 0: mflr reg; \ 325 addis reg,reg,(name - 0b)@ha; \ 326 addi reg,reg,(name - 0b)@l; 327 328 #if defined(__powerpc64__) && defined(HAVE_AS_ATHIGH) 329 #define __AS_ATHIGH high 330 #else 331 #define __AS_ATHIGH h 332 #endif 333 334 .macro __LOAD_REG_IMMEDIATE_32 r, x 335 .if (\x) >= 0x8000 || (\x) < -0x8000 336 lis \r, (\x)@__AS_ATHIGH 337 .if (\x) & 0xffff != 0 338 ori \r, \r, (\x)@l 339 .endif 340 .else 341 li \r, (\x)@l 342 .endif 343 .endm 344 345 .macro __LOAD_REG_IMMEDIATE r, x 346 .if (\x) >= 0x80000000 || (\x) < -0x80000000 347 __LOAD_REG_IMMEDIATE_32 \r, (\x) >> 32 348 sldi \r, \r, 32 349 .if (\x) & 0xffff0000 != 0 350 oris \r, \r, (\x)@__AS_ATHIGH 351 .endif 352 .if (\x) & 0xffff != 0 353 ori \r, \r, (\x)@l 354 .endif 355 .else 356 __LOAD_REG_IMMEDIATE_32 \r, \x 357 .endif 358 .endm 359 360 #ifdef __powerpc64__ 361 362 #ifdef CONFIG_PPC_KERNEL_PCREL 363 #define __LOAD_PACA_TOC(reg) \ 364 li reg,-1 365 #else 366 #define __LOAD_PACA_TOC(reg) \ 367 ld reg,PACATOC(r13) 368 #endif 369 370 #define LOAD_PACA_TOC() \ 371 __LOAD_PACA_TOC(r2) 372 373 #define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE reg, expr 374 375 #define LOAD_REG_IMMEDIATE_SYM(reg, tmp, expr) \ 376 lis tmp, (expr)@highest; \ 377 lis reg, (expr)@__AS_ATHIGH; \ 378 ori tmp, tmp, (expr)@higher; \ 379 ori reg, reg, (expr)@l; \ 380 rldimi reg, tmp, 32, 0 381 382 #ifdef CONFIG_PPC_KERNEL_PCREL 383 #define LOAD_REG_ADDR(reg,name) \ 384 pla reg,name@pcrel 385 386 #else 387 #define LOAD_REG_ADDR(reg,name) \ 388 addis reg,r2,name@toc@ha; \ 389 addi reg,reg,name@toc@l 390 #endif 391 392 #ifdef CONFIG_PPC_BOOK3E_64 393 /* 394 * This is used in register-constrained interrupt handlers. Not to be used 395 * by BOOK3S. ld complains with "got/toc optimization is not supported" if r2 396 * is not used for the TOC offset, so use @got(tocreg). If the interrupt 397 * handlers saved r2 instead, LOAD_REG_ADDR could be used. 398 */ 399 #define LOAD_REG_ADDR_ALTTOC(reg,tocreg,name) \ 400 ld reg,name@got(tocreg) 401 #endif 402 403 #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name) 404 #define ADDROFF(name) 0 405 406 /* offsets for stack frame layout */ 407 #define LRSAVE 16 408 409 #else /* 32-bit */ 410 411 #define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE_32 reg, expr 412 413 #define LOAD_REG_IMMEDIATE_SYM(reg,expr) \ 414 lis reg,(expr)@ha; \ 415 addi reg,reg,(expr)@l; 416 417 #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE_SYM(reg, name) 418 419 #define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha 420 #define ADDROFF(name) name@l 421 422 /* offsets for stack frame layout */ 423 #define LRSAVE 4 424 425 #endif 426 427 /* various errata or part fixups */ 428 #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_E500) 429 #define MFTB(dest) \ 430 90: mfspr dest, SPRN_TBRL; \ 431 BEGIN_FTR_SECTION_NESTED(96); \ 432 cmpwi dest,0; \ 433 beq- 90b; \ 434 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) 435 #else 436 #define MFTB(dest) MFTBL(dest) 437 #endif 438 439 #ifdef CONFIG_PPC_8xx 440 #define MFTBL(dest) mftb dest 441 #define MFTBU(dest) mftbu dest 442 #else 443 #define MFTBL(dest) mfspr dest, SPRN_TBRL 444 #define MFTBU(dest) mfspr dest, SPRN_TBRU 445 #endif 446 447 #ifndef CONFIG_SMP 448 #define TLBSYNC 449 #else 450 #define TLBSYNC tlbsync; sync 451 #endif 452 453 #ifdef CONFIG_PPC64 454 #define MTOCRF(FXM, RS) \ 455 BEGIN_FTR_SECTION_NESTED(848); \ 456 mtcrf (FXM), RS; \ 457 FTR_SECTION_ELSE_NESTED(848); \ 458 mtocrf (FXM), RS; \ 459 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848) 460 #endif 461 462 /* 463 * This instruction is not implemented on the PPC 603 or 601; however, on 464 * the 403GCX and 405GP tlbia IS defined and tlbie is not. 465 * All of these instructions exist in the 8xx, they have magical powers, 466 * and they must be used. 467 */ 468 469 #if !defined(CONFIG_4xx) && !defined(CONFIG_PPC_8xx) 470 #define tlbia \ 471 li r4,1024; \ 472 mtctr r4; \ 473 lis r4,KERNELBASE@h; \ 474 .machine push; \ 475 .machine "power4"; \ 476 0: tlbie r4; \ 477 .machine pop; \ 478 addi r4,r4,0x1000; \ 479 bdnz 0b 480 #endif 481 482 483 #ifdef CONFIG_IBM440EP_ERR42 484 #define PPC440EP_ERR42 isync 485 #else 486 #define PPC440EP_ERR42 487 #endif 488 489 /* The following stops all load and store data streams associated with stream 490 * ID (ie. streams created explicitly). The embedded and server mnemonics for 491 * dcbt are different so this must only be used for server. 492 */ 493 #define DCBT_BOOK3S_STOP_ALL_STREAM_IDS(scratch) \ 494 lis scratch,0x60000000@h; \ 495 dcbt 0,scratch,0b01010 496 497 /* 498 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them 499 * keep the address intact to be compatible with code shared with 500 * 32-bit classic. 501 * 502 * On the other hand, I find it useful to have them behave as expected 503 * by their name (ie always do the addition) on 64-bit BookE 504 */ 505 #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64) 506 #define toreal(rd) 507 #define fromreal(rd) 508 509 /* 510 * We use addis to ensure compatibility with the "classic" ppc versions of 511 * these macros, which use rs = 0 to get the tophys offset in rd, rather than 512 * converting the address in r0, and so this version has to do that too 513 * (i.e. set register rd to 0 when rs == 0). 514 */ 515 #define tophys(rd,rs) \ 516 addis rd,rs,0 517 518 #define tovirt(rd,rs) \ 519 addis rd,rs,0 520 521 #elif defined(CONFIG_PPC64) 522 #define toreal(rd) /* we can access c000... in real mode */ 523 #define fromreal(rd) 524 525 #define tophys(rd,rs) \ 526 clrldi rd,rs,2 527 528 #define tovirt(rd,rs) \ 529 rotldi rd,rs,16; \ 530 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\ 531 rotldi rd,rd,48 532 #else 533 #define toreal(rd) tophys(rd,rd) 534 #define fromreal(rd) tovirt(rd,rd) 535 536 #define tophys(rd, rs) addis rd, rs, -PAGE_OFFSET@h 537 #define tovirt(rd, rs) addis rd, rs, PAGE_OFFSET@h 538 #endif 539 540 #ifdef CONFIG_PPC_BOOK3S_64 541 #define MTMSRD(r) mtmsrd r 542 #define MTMSR_EERI(reg) mtmsrd reg,1 543 #else 544 #define MTMSRD(r) mtmsr r 545 #define MTMSR_EERI(reg) mtmsr reg 546 #endif 547 548 #endif /* __KERNEL__ */ 549 550 /* The boring bits... */ 551 552 /* Condition Register Bit Fields */ 553 554 #define cr0 0 555 #define cr1 1 556 #define cr2 2 557 #define cr3 3 558 #define cr4 4 559 #define cr5 5 560 #define cr6 6 561 #define cr7 7 562 563 564 /* 565 * General Purpose Registers (GPRs) 566 * 567 * The lower case r0-r31 should be used in preference to the upper 568 * case R0-R31 as they provide more error checking in the assembler. 569 * Use R0-31 only when really nessesary. 570 */ 571 572 #define r0 %r0 573 #define r1 %r1 574 #define r2 %r2 575 #define r3 %r3 576 #define r4 %r4 577 #define r5 %r5 578 #define r6 %r6 579 #define r7 %r7 580 #define r8 %r8 581 #define r9 %r9 582 #define r10 %r10 583 #define r11 %r11 584 #define r12 %r12 585 #define r13 %r13 586 #define r14 %r14 587 #define r15 %r15 588 #define r16 %r16 589 #define r17 %r17 590 #define r18 %r18 591 #define r19 %r19 592 #define r20 %r20 593 #define r21 %r21 594 #define r22 %r22 595 #define r23 %r23 596 #define r24 %r24 597 #define r25 %r25 598 #define r26 %r26 599 #define r27 %r27 600 #define r28 %r28 601 #define r29 %r29 602 #define r30 %r30 603 #define r31 %r31 604 605 606 /* Floating Point Registers (FPRs) */ 607 608 #define fr0 0 609 #define fr1 1 610 #define fr2 2 611 #define fr3 3 612 #define fr4 4 613 #define fr5 5 614 #define fr6 6 615 #define fr7 7 616 #define fr8 8 617 #define fr9 9 618 #define fr10 10 619 #define fr11 11 620 #define fr12 12 621 #define fr13 13 622 #define fr14 14 623 #define fr15 15 624 #define fr16 16 625 #define fr17 17 626 #define fr18 18 627 #define fr19 19 628 #define fr20 20 629 #define fr21 21 630 #define fr22 22 631 #define fr23 23 632 #define fr24 24 633 #define fr25 25 634 #define fr26 26 635 #define fr27 27 636 #define fr28 28 637 #define fr29 29 638 #define fr30 30 639 #define fr31 31 640 641 /* AltiVec Registers (VPRs) */ 642 643 #define v0 0 644 #define v1 1 645 #define v2 2 646 #define v3 3 647 #define v4 4 648 #define v5 5 649 #define v6 6 650 #define v7 7 651 #define v8 8 652 #define v9 9 653 #define v10 10 654 #define v11 11 655 #define v12 12 656 #define v13 13 657 #define v14 14 658 #define v15 15 659 #define v16 16 660 #define v17 17 661 #define v18 18 662 #define v19 19 663 #define v20 20 664 #define v21 21 665 #define v22 22 666 #define v23 23 667 #define v24 24 668 #define v25 25 669 #define v26 26 670 #define v27 27 671 #define v28 28 672 #define v29 29 673 #define v30 30 674 #define v31 31 675 676 /* VSX Registers (VSRs) */ 677 678 #define vs0 0 679 #define vs1 1 680 #define vs2 2 681 #define vs3 3 682 #define vs4 4 683 #define vs5 5 684 #define vs6 6 685 #define vs7 7 686 #define vs8 8 687 #define vs9 9 688 #define vs10 10 689 #define vs11 11 690 #define vs12 12 691 #define vs13 13 692 #define vs14 14 693 #define vs15 15 694 #define vs16 16 695 #define vs17 17 696 #define vs18 18 697 #define vs19 19 698 #define vs20 20 699 #define vs21 21 700 #define vs22 22 701 #define vs23 23 702 #define vs24 24 703 #define vs25 25 704 #define vs26 26 705 #define vs27 27 706 #define vs28 28 707 #define vs29 29 708 #define vs30 30 709 #define vs31 31 710 #define vs32 32 711 #define vs33 33 712 #define vs34 34 713 #define vs35 35 714 #define vs36 36 715 #define vs37 37 716 #define vs38 38 717 #define vs39 39 718 #define vs40 40 719 #define vs41 41 720 #define vs42 42 721 #define vs43 43 722 #define vs44 44 723 #define vs45 45 724 #define vs46 46 725 #define vs47 47 726 #define vs48 48 727 #define vs49 49 728 #define vs50 50 729 #define vs51 51 730 #define vs52 52 731 #define vs53 53 732 #define vs54 54 733 #define vs55 55 734 #define vs56 56 735 #define vs57 57 736 #define vs58 58 737 #define vs59 59 738 #define vs60 60 739 #define vs61 61 740 #define vs62 62 741 #define vs63 63 742 743 /* SPE Registers (EVPRs) */ 744 745 #define evr0 0 746 #define evr1 1 747 #define evr2 2 748 #define evr3 3 749 #define evr4 4 750 #define evr5 5 751 #define evr6 6 752 #define evr7 7 753 #define evr8 8 754 #define evr9 9 755 #define evr10 10 756 #define evr11 11 757 #define evr12 12 758 #define evr13 13 759 #define evr14 14 760 #define evr15 15 761 #define evr16 16 762 #define evr17 17 763 #define evr18 18 764 #define evr19 19 765 #define evr20 20 766 #define evr21 21 767 #define evr22 22 768 #define evr23 23 769 #define evr24 24 770 #define evr25 25 771 #define evr26 26 772 #define evr27 27 773 #define evr28 28 774 #define evr29 29 775 #define evr30 30 776 #define evr31 31 777 778 #define RFSCV .long 0x4c0000a4 779 780 /* 781 * Create an endian fixup trampoline 782 * 783 * This starts with a "tdi 0,0,0x48" instruction which is 784 * essentially a "trap never", and thus akin to a nop. 785 * 786 * The opcode for this instruction read with the wrong endian 787 * however results in a b . + 8 788 * 789 * So essentially we use that trick to execute the following 790 * trampoline in "reverse endian" if we are running with the 791 * MSR_LE bit set the "wrong" way for whatever endianness the 792 * kernel is built for. 793 */ 794 795 #ifdef CONFIG_PPC_BOOK3E_64 796 #define FIXUP_ENDIAN 797 #else 798 /* 799 * This version may be used in HV or non-HV context. 800 * MSR[EE] must be disabled. 801 */ 802 #define FIXUP_ENDIAN \ 803 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ 804 b 191f; /* Skip trampoline if endian is good */ \ 805 .long 0xa600607d; /* mfmsr r11 */ \ 806 .long 0x01006b69; /* xori r11,r11,1 */ \ 807 .long 0x00004039; /* li r10,0 */ \ 808 .long 0x6401417d; /* mtmsrd r10,1 */ \ 809 .long 0x05009f42; /* bcl 20,31,$+4 */ \ 810 .long 0xa602487d; /* mflr r10 */ \ 811 .long 0x14004a39; /* addi r10,r10,20 */ \ 812 .long 0xa6035a7d; /* mtsrr0 r10 */ \ 813 .long 0xa6037b7d; /* mtsrr1 r11 */ \ 814 .long 0x2400004c; /* rfid */ \ 815 191: 816 817 /* 818 * This version that may only be used with MSR[HV]=1 819 * - Does not clear MSR[RI], so more robust. 820 * - Slightly smaller and faster. 821 */ 822 #define FIXUP_ENDIAN_HV \ 823 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ 824 b 191f; /* Skip trampoline if endian is good */ \ 825 .long 0xa600607d; /* mfmsr r11 */ \ 826 .long 0x01006b69; /* xori r11,r11,1 */ \ 827 .long 0x05009f42; /* bcl 20,31,$+4 */ \ 828 .long 0xa602487d; /* mflr r10 */ \ 829 .long 0x14004a39; /* addi r10,r10,20 */ \ 830 .long 0xa64b5a7d; /* mthsrr0 r10 */ \ 831 .long 0xa64b7b7d; /* mthsrr1 r11 */ \ 832 .long 0x2402004c; /* hrfid */ \ 833 191: 834 835 #endif /* !CONFIG_PPC_BOOK3E_64 */ 836 837 #endif /* __ASSEMBLY__ */ 838 839 #define SOFT_MASK_TABLE(_start, _end) \ 840 stringify_in_c(.section __soft_mask_table,"a";)\ 841 stringify_in_c(.balign 8;) \ 842 stringify_in_c(.llong (_start);) \ 843 stringify_in_c(.llong (_end);) \ 844 stringify_in_c(.previous) 845 846 #define RESTART_TABLE(_start, _end, _target) \ 847 stringify_in_c(.section __restart_table,"a";)\ 848 stringify_in_c(.balign 8;) \ 849 stringify_in_c(.llong (_start);) \ 850 stringify_in_c(.llong (_end);) \ 851 stringify_in_c(.llong (_target);) \ 852 stringify_in_c(.previous) 853 854 #ifdef CONFIG_PPC_E500 855 #define BTB_FLUSH(reg) \ 856 lis reg,BUCSR_INIT@h; \ 857 ori reg,reg,BUCSR_INIT@l; \ 858 mtspr SPRN_BUCSR,reg; \ 859 isync; 860 #else 861 #define BTB_FLUSH(reg) 862 #endif /* CONFIG_PPC_E500 */ 863 864 #if defined(CONFIG_PPC64_ELF_ABI_V1) 865 #define STACK_FRAME_PARAMS 48 866 #elif defined(CONFIG_PPC64_ELF_ABI_V2) 867 #define STACK_FRAME_PARAMS 32 868 #elif defined(CONFIG_PPC32) 869 #define STACK_FRAME_PARAMS 8 870 #endif 871 872 #endif /* _ASM_POWERPC_PPC_ASM_H */ 873