1 /* 2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. 3 */ 4 #ifndef _ASM_POWERPC_PPC_ASM_H 5 #define _ASM_POWERPC_PPC_ASM_H 6 7 #include <linux/init.h> 8 #include <linux/stringify.h> 9 #include <asm/asm-compat.h> 10 #include <asm/processor.h> 11 #include <asm/ppc-opcode.h> 12 #include <asm/firmware.h> 13 14 #ifndef __ASSEMBLY__ 15 #error __FILE__ should only be used in assembler files 16 #else 17 18 #define SZL (BITS_PER_LONG/8) 19 20 /* 21 * Stuff for accurate CPU time accounting. 22 * These macros handle transitions between user and system state 23 * in exception entry and exit and accumulate time to the 24 * user_time and system_time fields in the paca. 25 */ 26 27 #ifndef CONFIG_VIRT_CPU_ACCOUNTING 28 #define ACCOUNT_CPU_USER_ENTRY(ra, rb) 29 #define ACCOUNT_CPU_USER_EXIT(ra, rb) 30 #define ACCOUNT_STOLEN_TIME 31 #else 32 #define ACCOUNT_CPU_USER_ENTRY(ra, rb) \ 33 beq 2f; /* if from kernel mode */ \ 34 MFTB(ra); /* get timebase */ \ 35 ld rb,PACA_STARTTIME_USER(r13); \ 36 std ra,PACA_STARTTIME(r13); \ 37 subf rb,rb,ra; /* subtract start value */ \ 38 ld ra,PACA_USER_TIME(r13); \ 39 add ra,ra,rb; /* add on to user time */ \ 40 std ra,PACA_USER_TIME(r13); \ 41 2: 42 43 #define ACCOUNT_CPU_USER_EXIT(ra, rb) \ 44 MFTB(ra); /* get timebase */ \ 45 ld rb,PACA_STARTTIME(r13); \ 46 std ra,PACA_STARTTIME_USER(r13); \ 47 subf rb,rb,ra; /* subtract start value */ \ 48 ld ra,PACA_SYSTEM_TIME(r13); \ 49 add ra,ra,rb; /* add on to system time */ \ 50 std ra,PACA_SYSTEM_TIME(r13) 51 52 #ifdef CONFIG_PPC_SPLPAR 53 #define ACCOUNT_STOLEN_TIME \ 54 BEGIN_FW_FTR_SECTION; \ 55 beq 33f; \ 56 /* from user - see if there are any DTL entries to process */ \ 57 ld r10,PACALPPACAPTR(r13); /* get ptr to VPA */ \ 58 ld r11,PACA_DTL_RIDX(r13); /* get log read index */ \ 59 ld r10,LPPACA_DTLIDX(r10); /* get log write index */ \ 60 cmpd cr1,r11,r10; \ 61 beq+ cr1,33f; \ 62 bl .accumulate_stolen_time; \ 63 33: \ 64 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR) 65 66 #else /* CONFIG_PPC_SPLPAR */ 67 #define ACCOUNT_STOLEN_TIME 68 69 #endif /* CONFIG_PPC_SPLPAR */ 70 71 #endif /* CONFIG_VIRT_CPU_ACCOUNTING */ 72 73 /* 74 * Macros for storing registers into and loading registers from 75 * exception frames. 76 */ 77 #ifdef __powerpc64__ 78 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base) 79 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base) 80 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) 81 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) 82 #else 83 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) 84 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) 85 #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \ 86 SAVE_10GPRS(22, base) 87 #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \ 88 REST_10GPRS(22, base) 89 #endif 90 91 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) 92 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) 93 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) 94 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) 95 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) 96 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) 97 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) 98 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) 99 100 #define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) 101 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) 102 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) 103 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) 104 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) 105 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) 106 #define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) 107 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) 108 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) 109 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) 110 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) 111 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) 112 113 #define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,base,b 114 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) 115 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) 116 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) 117 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) 118 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) 119 #define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,base,b 120 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) 121 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) 122 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) 123 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) 124 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) 125 126 /* Save the lower 32 VSRs in the thread VSR region */ 127 #define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,base,b) 128 #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) 129 #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base) 130 #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base) 131 #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base) 132 #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) 133 #define REST_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,base,b) 134 #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base) 135 #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base) 136 #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base) 137 #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base) 138 #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base) 139 /* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */ 140 #define SAVE_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,base,b) 141 #define SAVE_2VSRSU(n,b,base) SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base) 142 #define SAVE_4VSRSU(n,b,base) SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base) 143 #define SAVE_8VSRSU(n,b,base) SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base) 144 #define SAVE_16VSRSU(n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base) 145 #define SAVE_32VSRSU(n,b,base) SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base) 146 #define REST_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,base,b) 147 #define REST_2VSRSU(n,b,base) REST_VSRU(n,b,base); REST_VSRU(n+1,b,base) 148 #define REST_4VSRSU(n,b,base) REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base) 149 #define REST_8VSRSU(n,b,base) REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base) 150 #define REST_16VSRSU(n,b,base) REST_8VSRSU(n,b,base); REST_8VSRSU(n+8,b,base) 151 #define REST_32VSRSU(n,b,base) REST_16VSRSU(n,b,base); REST_16VSRSU(n+16,b,base) 152 153 #define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base) 154 #define SAVE_2EVRS(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base) 155 #define SAVE_4EVRS(n,s,base) SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base) 156 #define SAVE_8EVRS(n,s,base) SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base) 157 #define SAVE_16EVRS(n,s,base) SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base) 158 #define SAVE_32EVRS(n,s,base) SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base) 159 #define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n 160 #define REST_2EVRS(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base) 161 #define REST_4EVRS(n,s,base) REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base) 162 #define REST_8EVRS(n,s,base) REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base) 163 #define REST_16EVRS(n,s,base) REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base) 164 #define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base) 165 166 /* Macros to adjust thread priority for hardware multithreading */ 167 #define HMT_VERY_LOW or 31,31,31 # very low priority 168 #define HMT_LOW or 1,1,1 169 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority 170 #define HMT_MEDIUM or 2,2,2 171 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority 172 #define HMT_HIGH or 3,3,3 173 174 #ifdef __KERNEL__ 175 #ifdef CONFIG_PPC64 176 177 #define XGLUE(a,b) a##b 178 #define GLUE(a,b) XGLUE(a,b) 179 180 #define _GLOBAL(name) \ 181 .section ".text"; \ 182 .align 2 ; \ 183 .globl name; \ 184 .globl GLUE(.,name); \ 185 .section ".opd","aw"; \ 186 name: \ 187 .quad GLUE(.,name); \ 188 .quad .TOC.@tocbase; \ 189 .quad 0; \ 190 .previous; \ 191 .type GLUE(.,name),@function; \ 192 GLUE(.,name): 193 194 #define _INIT_GLOBAL(name) \ 195 __REF; \ 196 .align 2 ; \ 197 .globl name; \ 198 .globl GLUE(.,name); \ 199 .section ".opd","aw"; \ 200 name: \ 201 .quad GLUE(.,name); \ 202 .quad .TOC.@tocbase; \ 203 .quad 0; \ 204 .previous; \ 205 .type GLUE(.,name),@function; \ 206 GLUE(.,name): 207 208 #define _KPROBE(name) \ 209 .section ".kprobes.text","a"; \ 210 .align 2 ; \ 211 .globl name; \ 212 .globl GLUE(.,name); \ 213 .section ".opd","aw"; \ 214 name: \ 215 .quad GLUE(.,name); \ 216 .quad .TOC.@tocbase; \ 217 .quad 0; \ 218 .previous; \ 219 .type GLUE(.,name),@function; \ 220 GLUE(.,name): 221 222 #define _STATIC(name) \ 223 .section ".text"; \ 224 .align 2 ; \ 225 .section ".opd","aw"; \ 226 name: \ 227 .quad GLUE(.,name); \ 228 .quad .TOC.@tocbase; \ 229 .quad 0; \ 230 .previous; \ 231 .type GLUE(.,name),@function; \ 232 GLUE(.,name): 233 234 #define _INIT_STATIC(name) \ 235 __REF; \ 236 .align 2 ; \ 237 .section ".opd","aw"; \ 238 name: \ 239 .quad GLUE(.,name); \ 240 .quad .TOC.@tocbase; \ 241 .quad 0; \ 242 .previous; \ 243 .type GLUE(.,name),@function; \ 244 GLUE(.,name): 245 246 #else /* 32-bit */ 247 248 #define _ENTRY(n) \ 249 .globl n; \ 250 n: 251 252 #define _GLOBAL(n) \ 253 .text; \ 254 .stabs __stringify(n:F-1),N_FUN,0,0,n;\ 255 .globl n; \ 256 n: 257 258 #define _KPROBE(n) \ 259 .section ".kprobes.text","a"; \ 260 .globl n; \ 261 n: 262 263 #endif 264 265 /* 266 * LOAD_REG_IMMEDIATE(rn, expr) 267 * Loads the value of the constant expression 'expr' into register 'rn' 268 * using immediate instructions only. Use this when it's important not 269 * to reference other data (i.e. on ppc64 when the TOC pointer is not 270 * valid) and when 'expr' is a constant or absolute address. 271 * 272 * LOAD_REG_ADDR(rn, name) 273 * Loads the address of label 'name' into register 'rn'. Use this when 274 * you don't particularly need immediate instructions only, but you need 275 * the whole address in one register (e.g. it's a structure address and 276 * you want to access various offsets within it). On ppc32 this is 277 * identical to LOAD_REG_IMMEDIATE. 278 * 279 * LOAD_REG_ADDRBASE(rn, name) 280 * ADDROFF(name) 281 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into 282 * register 'rn'. ADDROFF(name) returns the remainder of the address as 283 * a constant expression. ADDROFF(name) is a signed expression < 16 bits 284 * in size, so is suitable for use directly as an offset in load and store 285 * instructions. Use this when loading/storing a single word or less as: 286 * LOAD_REG_ADDRBASE(rX, name) 287 * ld rY,ADDROFF(name)(rX) 288 */ 289 #ifdef __powerpc64__ 290 #define LOAD_REG_IMMEDIATE(reg,expr) \ 291 lis (reg),(expr)@highest; \ 292 ori (reg),(reg),(expr)@higher; \ 293 rldicr (reg),(reg),32,31; \ 294 oris (reg),(reg),(expr)@h; \ 295 ori (reg),(reg),(expr)@l; 296 297 #define LOAD_REG_ADDR(reg,name) \ 298 ld (reg),name@got(r2) 299 300 #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name) 301 #define ADDROFF(name) 0 302 303 /* offsets for stack frame layout */ 304 #define LRSAVE 16 305 306 #else /* 32-bit */ 307 308 #define LOAD_REG_IMMEDIATE(reg,expr) \ 309 lis (reg),(expr)@ha; \ 310 addi (reg),(reg),(expr)@l; 311 312 #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name) 313 314 #define LOAD_REG_ADDRBASE(reg, name) lis (reg),name@ha 315 #define ADDROFF(name) name@l 316 317 /* offsets for stack frame layout */ 318 #define LRSAVE 4 319 320 #endif 321 322 /* various errata or part fixups */ 323 #ifdef CONFIG_PPC601_SYNC_FIX 324 #define SYNC \ 325 BEGIN_FTR_SECTION \ 326 sync; \ 327 isync; \ 328 END_FTR_SECTION_IFSET(CPU_FTR_601) 329 #define SYNC_601 \ 330 BEGIN_FTR_SECTION \ 331 sync; \ 332 END_FTR_SECTION_IFSET(CPU_FTR_601) 333 #define ISYNC_601 \ 334 BEGIN_FTR_SECTION \ 335 isync; \ 336 END_FTR_SECTION_IFSET(CPU_FTR_601) 337 #else 338 #define SYNC 339 #define SYNC_601 340 #define ISYNC_601 341 #endif 342 343 #ifdef CONFIG_PPC_CELL 344 #define MFTB(dest) \ 345 90: mftb dest; \ 346 BEGIN_FTR_SECTION_NESTED(96); \ 347 cmpwi dest,0; \ 348 beq- 90b; \ 349 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) 350 #else 351 #define MFTB(dest) mftb dest 352 #endif 353 354 #ifndef CONFIG_SMP 355 #define TLBSYNC 356 #else /* CONFIG_SMP */ 357 /* tlbsync is not implemented on 601 */ 358 #define TLBSYNC \ 359 BEGIN_FTR_SECTION \ 360 tlbsync; \ 361 sync; \ 362 END_FTR_SECTION_IFCLR(CPU_FTR_601) 363 #endif 364 365 366 /* 367 * This instruction is not implemented on the PPC 603 or 601; however, on 368 * the 403GCX and 405GP tlbia IS defined and tlbie is not. 369 * All of these instructions exist in the 8xx, they have magical powers, 370 * and they must be used. 371 */ 372 373 #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx) 374 #define tlbia \ 375 li r4,1024; \ 376 mtctr r4; \ 377 lis r4,KERNELBASE@h; \ 378 0: tlbie r4; \ 379 addi r4,r4,0x1000; \ 380 bdnz 0b 381 #endif 382 383 384 #ifdef CONFIG_IBM440EP_ERR42 385 #define PPC440EP_ERR42 isync 386 #else 387 #define PPC440EP_ERR42 388 #endif 389 390 /* 391 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them 392 * keep the address intact to be compatible with code shared with 393 * 32-bit classic. 394 * 395 * On the other hand, I find it useful to have them behave as expected 396 * by their name (ie always do the addition) on 64-bit BookE 397 */ 398 #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64) 399 #define toreal(rd) 400 #define fromreal(rd) 401 402 /* 403 * We use addis to ensure compatibility with the "classic" ppc versions of 404 * these macros, which use rs = 0 to get the tophys offset in rd, rather than 405 * converting the address in r0, and so this version has to do that too 406 * (i.e. set register rd to 0 when rs == 0). 407 */ 408 #define tophys(rd,rs) \ 409 addis rd,rs,0 410 411 #define tovirt(rd,rs) \ 412 addis rd,rs,0 413 414 #elif defined(CONFIG_PPC64) 415 #define toreal(rd) /* we can access c000... in real mode */ 416 #define fromreal(rd) 417 418 #define tophys(rd,rs) \ 419 clrldi rd,rs,2 420 421 #define tovirt(rd,rs) \ 422 rotldi rd,rs,16; \ 423 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\ 424 rotldi rd,rd,48 425 #else 426 /* 427 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the 428 * physical base address of RAM at compile time. 429 */ 430 #define toreal(rd) tophys(rd,rd) 431 #define fromreal(rd) tovirt(rd,rd) 432 433 #define tophys(rd,rs) \ 434 0: addis rd,rs,-PAGE_OFFSET@h; \ 435 .section ".vtop_fixup","aw"; \ 436 .align 1; \ 437 .long 0b; \ 438 .previous 439 440 #define tovirt(rd,rs) \ 441 0: addis rd,rs,PAGE_OFFSET@h; \ 442 .section ".ptov_fixup","aw"; \ 443 .align 1; \ 444 .long 0b; \ 445 .previous 446 #endif 447 448 #ifdef CONFIG_PPC_BOOK3S_64 449 #define RFI rfid 450 #define MTMSRD(r) mtmsrd r 451 #else 452 #define FIX_SRR1(ra, rb) 453 #ifndef CONFIG_40x 454 #define RFI rfi 455 #else 456 #define RFI rfi; b . /* Prevent prefetch past rfi */ 457 #endif 458 #define MTMSRD(r) mtmsr r 459 #define CLR_TOP32(r) 460 #endif 461 462 #endif /* __KERNEL__ */ 463 464 /* The boring bits... */ 465 466 /* Condition Register Bit Fields */ 467 468 #define cr0 0 469 #define cr1 1 470 #define cr2 2 471 #define cr3 3 472 #define cr4 4 473 #define cr5 5 474 #define cr6 6 475 #define cr7 7 476 477 478 /* General Purpose Registers (GPRs) */ 479 480 #define r0 0 481 #define r1 1 482 #define r2 2 483 #define r3 3 484 #define r4 4 485 #define r5 5 486 #define r6 6 487 #define r7 7 488 #define r8 8 489 #define r9 9 490 #define r10 10 491 #define r11 11 492 #define r12 12 493 #define r13 13 494 #define r14 14 495 #define r15 15 496 #define r16 16 497 #define r17 17 498 #define r18 18 499 #define r19 19 500 #define r20 20 501 #define r21 21 502 #define r22 22 503 #define r23 23 504 #define r24 24 505 #define r25 25 506 #define r26 26 507 #define r27 27 508 #define r28 28 509 #define r29 29 510 #define r30 30 511 #define r31 31 512 513 514 /* Floating Point Registers (FPRs) */ 515 516 #define fr0 0 517 #define fr1 1 518 #define fr2 2 519 #define fr3 3 520 #define fr4 4 521 #define fr5 5 522 #define fr6 6 523 #define fr7 7 524 #define fr8 8 525 #define fr9 9 526 #define fr10 10 527 #define fr11 11 528 #define fr12 12 529 #define fr13 13 530 #define fr14 14 531 #define fr15 15 532 #define fr16 16 533 #define fr17 17 534 #define fr18 18 535 #define fr19 19 536 #define fr20 20 537 #define fr21 21 538 #define fr22 22 539 #define fr23 23 540 #define fr24 24 541 #define fr25 25 542 #define fr26 26 543 #define fr27 27 544 #define fr28 28 545 #define fr29 29 546 #define fr30 30 547 #define fr31 31 548 549 /* AltiVec Registers (VPRs) */ 550 551 #define vr0 0 552 #define vr1 1 553 #define vr2 2 554 #define vr3 3 555 #define vr4 4 556 #define vr5 5 557 #define vr6 6 558 #define vr7 7 559 #define vr8 8 560 #define vr9 9 561 #define vr10 10 562 #define vr11 11 563 #define vr12 12 564 #define vr13 13 565 #define vr14 14 566 #define vr15 15 567 #define vr16 16 568 #define vr17 17 569 #define vr18 18 570 #define vr19 19 571 #define vr20 20 572 #define vr21 21 573 #define vr22 22 574 #define vr23 23 575 #define vr24 24 576 #define vr25 25 577 #define vr26 26 578 #define vr27 27 579 #define vr28 28 580 #define vr29 29 581 #define vr30 30 582 #define vr31 31 583 584 /* VSX Registers (VSRs) */ 585 586 #define vsr0 0 587 #define vsr1 1 588 #define vsr2 2 589 #define vsr3 3 590 #define vsr4 4 591 #define vsr5 5 592 #define vsr6 6 593 #define vsr7 7 594 #define vsr8 8 595 #define vsr9 9 596 #define vsr10 10 597 #define vsr11 11 598 #define vsr12 12 599 #define vsr13 13 600 #define vsr14 14 601 #define vsr15 15 602 #define vsr16 16 603 #define vsr17 17 604 #define vsr18 18 605 #define vsr19 19 606 #define vsr20 20 607 #define vsr21 21 608 #define vsr22 22 609 #define vsr23 23 610 #define vsr24 24 611 #define vsr25 25 612 #define vsr26 26 613 #define vsr27 27 614 #define vsr28 28 615 #define vsr29 29 616 #define vsr30 30 617 #define vsr31 31 618 #define vsr32 32 619 #define vsr33 33 620 #define vsr34 34 621 #define vsr35 35 622 #define vsr36 36 623 #define vsr37 37 624 #define vsr38 38 625 #define vsr39 39 626 #define vsr40 40 627 #define vsr41 41 628 #define vsr42 42 629 #define vsr43 43 630 #define vsr44 44 631 #define vsr45 45 632 #define vsr46 46 633 #define vsr47 47 634 #define vsr48 48 635 #define vsr49 49 636 #define vsr50 50 637 #define vsr51 51 638 #define vsr52 52 639 #define vsr53 53 640 #define vsr54 54 641 #define vsr55 55 642 #define vsr56 56 643 #define vsr57 57 644 #define vsr58 58 645 #define vsr59 59 646 #define vsr60 60 647 #define vsr61 61 648 #define vsr62 62 649 #define vsr63 63 650 651 /* SPE Registers (EVPRs) */ 652 653 #define evr0 0 654 #define evr1 1 655 #define evr2 2 656 #define evr3 3 657 #define evr4 4 658 #define evr5 5 659 #define evr6 6 660 #define evr7 7 661 #define evr8 8 662 #define evr9 9 663 #define evr10 10 664 #define evr11 11 665 #define evr12 12 666 #define evr13 13 667 #define evr14 14 668 #define evr15 15 669 #define evr16 16 670 #define evr17 17 671 #define evr18 18 672 #define evr19 19 673 #define evr20 20 674 #define evr21 21 675 #define evr22 22 676 #define evr23 23 677 #define evr24 24 678 #define evr25 25 679 #define evr26 26 680 #define evr27 27 681 #define evr28 28 682 #define evr29 29 683 #define evr30 30 684 #define evr31 31 685 686 /* some stab codes */ 687 #define N_FUN 36 688 #define N_RSYM 64 689 #define N_SLINE 68 690 #define N_SO 100 691 692 #endif /* __ASSEMBLY__ */ 693 694 #endif /* _ASM_POWERPC_PPC_ASM_H */ 695