1 /* 2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. 3 */ 4 #ifndef _ASM_POWERPC_PPC_ASM_H 5 #define _ASM_POWERPC_PPC_ASM_H 6 7 #include <linux/stringify.h> 8 #include <asm/asm-compat.h> 9 #include <asm/processor.h> 10 #include <asm/ppc-opcode.h> 11 #include <asm/firmware.h> 12 #include <asm/feature-fixups.h> 13 14 #ifdef __ASSEMBLY__ 15 16 #define SZL (BITS_PER_LONG/8) 17 18 /* 19 * Stuff for accurate CPU time accounting. 20 * These macros handle transitions between user and system state 21 * in exception entry and exit and accumulate time to the 22 * user_time and system_time fields in the paca. 23 */ 24 25 #ifndef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE 26 #define ACCOUNT_CPU_USER_ENTRY(ptr, ra, rb) 27 #define ACCOUNT_CPU_USER_EXIT(ptr, ra, rb) 28 #else 29 #define ACCOUNT_CPU_USER_ENTRY(ptr, ra, rb) \ 30 MFTB(ra); /* get timebase */ \ 31 PPC_LL rb, ACCOUNT_STARTTIME_USER(ptr); \ 32 PPC_STL ra, ACCOUNT_STARTTIME(ptr); \ 33 subf rb,rb,ra; /* subtract start value */ \ 34 PPC_LL ra, ACCOUNT_USER_TIME(ptr); \ 35 add ra,ra,rb; /* add on to user time */ \ 36 PPC_STL ra, ACCOUNT_USER_TIME(ptr); \ 37 38 #define ACCOUNT_CPU_USER_EXIT(ptr, ra, rb) \ 39 MFTB(ra); /* get timebase */ \ 40 PPC_LL rb, ACCOUNT_STARTTIME(ptr); \ 41 PPC_STL ra, ACCOUNT_STARTTIME_USER(ptr); \ 42 subf rb,rb,ra; /* subtract start value */ \ 43 PPC_LL ra, ACCOUNT_SYSTEM_TIME(ptr); \ 44 add ra,ra,rb; /* add on to system time */ \ 45 PPC_STL ra, ACCOUNT_SYSTEM_TIME(ptr) 46 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */ 47 48 /* 49 * Macros for storing registers into and loading registers from 50 * exception frames. 51 */ 52 #ifdef __powerpc64__ 53 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base) 54 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base) 55 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) 56 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) 57 #else 58 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) 59 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) 60 #define SAVE_NVGPRS(base) stmw 13, GPR0+4*13(base) 61 #define REST_NVGPRS(base) lmw 13, GPR0+4*13(base) 62 #endif 63 64 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) 65 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) 66 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) 67 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) 68 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) 69 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) 70 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) 71 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) 72 73 #define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base) 74 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) 75 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) 76 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) 77 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) 78 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) 79 #define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base) 80 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) 81 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) 82 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) 83 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) 84 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) 85 86 #define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b 87 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) 88 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) 89 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) 90 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) 91 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) 92 #define REST_VR(n,b,base) li b,16*(n); lvx n,base,b 93 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) 94 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) 95 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) 96 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) 97 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) 98 99 #ifdef __BIG_ENDIAN__ 100 #define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base) 101 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base) 102 #else 103 #define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \ 104 STXVD2X(n,b,base); \ 105 XXSWAPD(n,n) 106 107 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \ 108 XXSWAPD(n,n) 109 #endif 110 /* Save the lower 32 VSRs in the thread VSR region */ 111 #define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b) 112 #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) 113 #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base) 114 #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base) 115 #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base) 116 #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) 117 #define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b) 118 #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base) 119 #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base) 120 #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base) 121 #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base) 122 #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base) 123 124 /* 125 * b = base register for addressing, o = base offset from register of 1st EVR 126 * n = first EVR, s = scratch 127 */ 128 #define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b) 129 #define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o) 130 #define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o) 131 #define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o) 132 #define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o) 133 #define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o) 134 #define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n 135 #define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o) 136 #define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o) 137 #define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o) 138 #define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o) 139 #define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o) 140 141 /* Macros to adjust thread priority for hardware multithreading */ 142 #define HMT_VERY_LOW or 31,31,31 # very low priority 143 #define HMT_LOW or 1,1,1 144 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority 145 #define HMT_MEDIUM or 2,2,2 146 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority 147 #define HMT_HIGH or 3,3,3 148 #define HMT_EXTRA_HIGH or 7,7,7 # power7 only 149 150 #ifdef CONFIG_PPC64 151 #define ULONG_SIZE 8 152 #else 153 #define ULONG_SIZE 4 154 #endif 155 #define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE)) 156 #define VCPU_GPR(n) __VCPU_GPR(__REG_##n) 157 158 #ifdef __KERNEL__ 159 160 /* 161 * We use __powerpc64__ here because we want the compat VDSO to use the 32-bit 162 * version below in the else case of the ifdef. 163 */ 164 #ifdef __powerpc64__ 165 166 #define STACKFRAMESIZE 256 167 #define __STK_REG(i) (112 + ((i)-14)*8) 168 #define STK_REG(i) __STK_REG(__REG_##i) 169 170 #ifdef PPC64_ELF_ABI_v2 171 #define STK_GOT 24 172 #define __STK_PARAM(i) (32 + ((i)-3)*8) 173 #else 174 #define STK_GOT 40 175 #define __STK_PARAM(i) (48 + ((i)-3)*8) 176 #endif 177 #define STK_PARAM(i) __STK_PARAM(__REG_##i) 178 179 #ifdef PPC64_ELF_ABI_v2 180 181 #define _GLOBAL(name) \ 182 .align 2 ; \ 183 .type name,@function; \ 184 .globl name; \ 185 name: 186 187 #define _GLOBAL_TOC(name) \ 188 .align 2 ; \ 189 .type name,@function; \ 190 .globl name; \ 191 name: \ 192 0: addis r2,r12,(.TOC.-0b)@ha; \ 193 addi r2,r2,(.TOC.-0b)@l; \ 194 .localentry name,.-name 195 196 #define DOTSYM(a) a 197 198 #else 199 200 #define XGLUE(a,b) a##b 201 #define GLUE(a,b) XGLUE(a,b) 202 203 #define _GLOBAL(name) \ 204 .align 2 ; \ 205 .globl name; \ 206 .globl GLUE(.,name); \ 207 .pushsection ".opd","aw"; \ 208 name: \ 209 .quad GLUE(.,name); \ 210 .quad .TOC.@tocbase; \ 211 .quad 0; \ 212 .popsection; \ 213 .type GLUE(.,name),@function; \ 214 GLUE(.,name): 215 216 #define _GLOBAL_TOC(name) _GLOBAL(name) 217 218 #define DOTSYM(a) GLUE(.,a) 219 220 #endif 221 222 #else /* 32-bit */ 223 224 #define _ENTRY(n) \ 225 .globl n; \ 226 n: 227 228 #define _GLOBAL(n) \ 229 .stabs __stringify(n:F-1),N_FUN,0,0,n;\ 230 .globl n; \ 231 n: 232 233 #define _GLOBAL_TOC(name) _GLOBAL(name) 234 235 #define DOTSYM(a) a 236 237 #endif 238 239 /* 240 * __kprobes (the C annotation) puts the symbol into the .kprobes.text 241 * section, which gets emitted at the end of regular text. 242 * 243 * _ASM_NOKPROBE_SYMBOL and NOKPROBE_SYMBOL just adds the symbol to 244 * a blacklist. The former is for core kprobe functions/data, the 245 * latter is for those that incdentially must be excluded from probing 246 * and allows them to be linked at more optimal location within text. 247 */ 248 #ifdef CONFIG_KPROBES 249 #define _ASM_NOKPROBE_SYMBOL(entry) \ 250 .pushsection "_kprobe_blacklist","aw"; \ 251 PPC_LONG (entry) ; \ 252 .popsection 253 #else 254 #define _ASM_NOKPROBE_SYMBOL(entry) 255 #endif 256 257 #define FUNC_START(name) _GLOBAL(name) 258 #define FUNC_END(name) 259 260 /* 261 * LOAD_REG_IMMEDIATE(rn, expr) 262 * Loads the value of the constant expression 'expr' into register 'rn' 263 * using immediate instructions only. Use this when it's important not 264 * to reference other data (i.e. on ppc64 when the TOC pointer is not 265 * valid) and when 'expr' is a constant or absolute address. 266 * 267 * LOAD_REG_ADDR(rn, name) 268 * Loads the address of label 'name' into register 'rn'. Use this when 269 * you don't particularly need immediate instructions only, but you need 270 * the whole address in one register (e.g. it's a structure address and 271 * you want to access various offsets within it). On ppc32 this is 272 * identical to LOAD_REG_IMMEDIATE. 273 * 274 * LOAD_REG_ADDR_PIC(rn, name) 275 * Loads the address of label 'name' into register 'run'. Use this when 276 * the kernel doesn't run at the linked or relocated address. Please 277 * note that this macro will clobber the lr register. 278 * 279 * LOAD_REG_ADDRBASE(rn, name) 280 * ADDROFF(name) 281 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into 282 * register 'rn'. ADDROFF(name) returns the remainder of the address as 283 * a constant expression. ADDROFF(name) is a signed expression < 16 bits 284 * in size, so is suitable for use directly as an offset in load and store 285 * instructions. Use this when loading/storing a single word or less as: 286 * LOAD_REG_ADDRBASE(rX, name) 287 * ld rY,ADDROFF(name)(rX) 288 */ 289 290 /* Be careful, this will clobber the lr register. */ 291 #define LOAD_REG_ADDR_PIC(reg, name) \ 292 bl 0f; \ 293 0: mflr reg; \ 294 addis reg,reg,(name - 0b)@ha; \ 295 addi reg,reg,(name - 0b)@l; 296 297 #if defined(__powerpc64__) && defined(HAVE_AS_ATHIGH) 298 #define __AS_ATHIGH high 299 #else 300 #define __AS_ATHIGH h 301 #endif 302 303 .macro __LOAD_REG_IMMEDIATE_32 r, x 304 .if (\x) >= 0x8000 || (\x) < -0x8000 305 lis \r, (\x)@__AS_ATHIGH 306 .if (\x) & 0xffff != 0 307 ori \r, \r, (\x)@l 308 .endif 309 .else 310 li \r, (\x)@l 311 .endif 312 .endm 313 314 .macro __LOAD_REG_IMMEDIATE r, x 315 .if (\x) >= 0x80000000 || (\x) < -0x80000000 316 __LOAD_REG_IMMEDIATE_32 \r, (\x) >> 32 317 sldi \r, \r, 32 318 .if (\x) & 0xffff0000 != 0 319 oris \r, \r, (\x)@__AS_ATHIGH 320 .endif 321 .if (\x) & 0xffff != 0 322 ori \r, \r, (\x)@l 323 .endif 324 .else 325 __LOAD_REG_IMMEDIATE_32 \r, \x 326 .endif 327 .endm 328 329 #ifdef __powerpc64__ 330 331 #define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE reg, expr 332 333 #define LOAD_REG_IMMEDIATE_SYM(reg, tmp, expr) \ 334 lis tmp, (expr)@highest; \ 335 lis reg, (expr)@__AS_ATHIGH; \ 336 ori tmp, tmp, (expr)@higher; \ 337 ori reg, reg, (expr)@l; \ 338 rldimi reg, tmp, 32, 0 339 340 #define LOAD_REG_ADDR(reg,name) \ 341 ld reg,name@got(r2) 342 343 #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name) 344 #define ADDROFF(name) 0 345 346 /* offsets for stack frame layout */ 347 #define LRSAVE 16 348 349 #else /* 32-bit */ 350 351 #define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE_32 reg, expr 352 353 #define LOAD_REG_IMMEDIATE_SYM(reg,expr) \ 354 lis reg,(expr)@ha; \ 355 addi reg,reg,(expr)@l; 356 357 #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE_SYM(reg, name) 358 359 #define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha 360 #define ADDROFF(name) name@l 361 362 /* offsets for stack frame layout */ 363 #define LRSAVE 4 364 365 #endif 366 367 /* various errata or part fixups */ 368 #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E) 369 #define MFTB(dest) \ 370 90: mfspr dest, SPRN_TBRL; \ 371 BEGIN_FTR_SECTION_NESTED(96); \ 372 cmpwi dest,0; \ 373 beq- 90b; \ 374 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) 375 #else 376 #define MFTB(dest) MFTBL(dest) 377 #endif 378 379 #ifdef CONFIG_PPC_8xx 380 #define MFTBL(dest) mftb dest 381 #define MFTBU(dest) mftbu dest 382 #else 383 #define MFTBL(dest) mfspr dest, SPRN_TBRL 384 #define MFTBU(dest) mfspr dest, SPRN_TBRU 385 #endif 386 387 #ifndef CONFIG_SMP 388 #define TLBSYNC 389 #else 390 #define TLBSYNC tlbsync; sync 391 #endif 392 393 #ifdef CONFIG_PPC64 394 #define MTOCRF(FXM, RS) \ 395 BEGIN_FTR_SECTION_NESTED(848); \ 396 mtcrf (FXM), RS; \ 397 FTR_SECTION_ELSE_NESTED(848); \ 398 mtocrf (FXM), RS; \ 399 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848) 400 #endif 401 402 /* 403 * This instruction is not implemented on the PPC 603 or 601; however, on 404 * the 403GCX and 405GP tlbia IS defined and tlbie is not. 405 * All of these instructions exist in the 8xx, they have magical powers, 406 * and they must be used. 407 */ 408 409 #if !defined(CONFIG_4xx) && !defined(CONFIG_PPC_8xx) 410 #define tlbia \ 411 li r4,1024; \ 412 mtctr r4; \ 413 lis r4,KERNELBASE@h; \ 414 .machine push; \ 415 .machine "power4"; \ 416 0: tlbie r4; \ 417 .machine pop; \ 418 addi r4,r4,0x1000; \ 419 bdnz 0b 420 #endif 421 422 423 #ifdef CONFIG_IBM440EP_ERR42 424 #define PPC440EP_ERR42 isync 425 #else 426 #define PPC440EP_ERR42 427 #endif 428 429 /* The following stops all load and store data streams associated with stream 430 * ID (ie. streams created explicitly). The embedded and server mnemonics for 431 * dcbt are different so this must only be used for server. 432 */ 433 #define DCBT_BOOK3S_STOP_ALL_STREAM_IDS(scratch) \ 434 lis scratch,0x60000000@h; \ 435 dcbt 0,scratch,0b01010 436 437 /* 438 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them 439 * keep the address intact to be compatible with code shared with 440 * 32-bit classic. 441 * 442 * On the other hand, I find it useful to have them behave as expected 443 * by their name (ie always do the addition) on 64-bit BookE 444 */ 445 #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64) 446 #define toreal(rd) 447 #define fromreal(rd) 448 449 /* 450 * We use addis to ensure compatibility with the "classic" ppc versions of 451 * these macros, which use rs = 0 to get the tophys offset in rd, rather than 452 * converting the address in r0, and so this version has to do that too 453 * (i.e. set register rd to 0 when rs == 0). 454 */ 455 #define tophys(rd,rs) \ 456 addis rd,rs,0 457 458 #define tovirt(rd,rs) \ 459 addis rd,rs,0 460 461 #elif defined(CONFIG_PPC64) 462 #define toreal(rd) /* we can access c000... in real mode */ 463 #define fromreal(rd) 464 465 #define tophys(rd,rs) \ 466 clrldi rd,rs,2 467 468 #define tovirt(rd,rs) \ 469 rotldi rd,rs,16; \ 470 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\ 471 rotldi rd,rd,48 472 #else 473 #define toreal(rd) tophys(rd,rd) 474 #define fromreal(rd) tovirt(rd,rd) 475 476 #define tophys(rd, rs) addis rd, rs, -PAGE_OFFSET@h 477 #define tovirt(rd, rs) addis rd, rs, PAGE_OFFSET@h 478 #endif 479 480 #ifdef CONFIG_PPC_BOOK3S_64 481 #define MTMSRD(r) mtmsrd r 482 #define MTMSR_EERI(reg) mtmsrd reg,1 483 #else 484 #define MTMSRD(r) mtmsr r 485 #define MTMSR_EERI(reg) mtmsr reg 486 #endif 487 488 #endif /* __KERNEL__ */ 489 490 /* The boring bits... */ 491 492 /* Condition Register Bit Fields */ 493 494 #define cr0 0 495 #define cr1 1 496 #define cr2 2 497 #define cr3 3 498 #define cr4 4 499 #define cr5 5 500 #define cr6 6 501 #define cr7 7 502 503 504 /* 505 * General Purpose Registers (GPRs) 506 * 507 * The lower case r0-r31 should be used in preference to the upper 508 * case R0-R31 as they provide more error checking in the assembler. 509 * Use R0-31 only when really nessesary. 510 */ 511 512 #define r0 %r0 513 #define r1 %r1 514 #define r2 %r2 515 #define r3 %r3 516 #define r4 %r4 517 #define r5 %r5 518 #define r6 %r6 519 #define r7 %r7 520 #define r8 %r8 521 #define r9 %r9 522 #define r10 %r10 523 #define r11 %r11 524 #define r12 %r12 525 #define r13 %r13 526 #define r14 %r14 527 #define r15 %r15 528 #define r16 %r16 529 #define r17 %r17 530 #define r18 %r18 531 #define r19 %r19 532 #define r20 %r20 533 #define r21 %r21 534 #define r22 %r22 535 #define r23 %r23 536 #define r24 %r24 537 #define r25 %r25 538 #define r26 %r26 539 #define r27 %r27 540 #define r28 %r28 541 #define r29 %r29 542 #define r30 %r30 543 #define r31 %r31 544 545 546 /* Floating Point Registers (FPRs) */ 547 548 #define fr0 0 549 #define fr1 1 550 #define fr2 2 551 #define fr3 3 552 #define fr4 4 553 #define fr5 5 554 #define fr6 6 555 #define fr7 7 556 #define fr8 8 557 #define fr9 9 558 #define fr10 10 559 #define fr11 11 560 #define fr12 12 561 #define fr13 13 562 #define fr14 14 563 #define fr15 15 564 #define fr16 16 565 #define fr17 17 566 #define fr18 18 567 #define fr19 19 568 #define fr20 20 569 #define fr21 21 570 #define fr22 22 571 #define fr23 23 572 #define fr24 24 573 #define fr25 25 574 #define fr26 26 575 #define fr27 27 576 #define fr28 28 577 #define fr29 29 578 #define fr30 30 579 #define fr31 31 580 581 /* AltiVec Registers (VPRs) */ 582 583 #define v0 0 584 #define v1 1 585 #define v2 2 586 #define v3 3 587 #define v4 4 588 #define v5 5 589 #define v6 6 590 #define v7 7 591 #define v8 8 592 #define v9 9 593 #define v10 10 594 #define v11 11 595 #define v12 12 596 #define v13 13 597 #define v14 14 598 #define v15 15 599 #define v16 16 600 #define v17 17 601 #define v18 18 602 #define v19 19 603 #define v20 20 604 #define v21 21 605 #define v22 22 606 #define v23 23 607 #define v24 24 608 #define v25 25 609 #define v26 26 610 #define v27 27 611 #define v28 28 612 #define v29 29 613 #define v30 30 614 #define v31 31 615 616 /* VSX Registers (VSRs) */ 617 618 #define vs0 0 619 #define vs1 1 620 #define vs2 2 621 #define vs3 3 622 #define vs4 4 623 #define vs5 5 624 #define vs6 6 625 #define vs7 7 626 #define vs8 8 627 #define vs9 9 628 #define vs10 10 629 #define vs11 11 630 #define vs12 12 631 #define vs13 13 632 #define vs14 14 633 #define vs15 15 634 #define vs16 16 635 #define vs17 17 636 #define vs18 18 637 #define vs19 19 638 #define vs20 20 639 #define vs21 21 640 #define vs22 22 641 #define vs23 23 642 #define vs24 24 643 #define vs25 25 644 #define vs26 26 645 #define vs27 27 646 #define vs28 28 647 #define vs29 29 648 #define vs30 30 649 #define vs31 31 650 #define vs32 32 651 #define vs33 33 652 #define vs34 34 653 #define vs35 35 654 #define vs36 36 655 #define vs37 37 656 #define vs38 38 657 #define vs39 39 658 #define vs40 40 659 #define vs41 41 660 #define vs42 42 661 #define vs43 43 662 #define vs44 44 663 #define vs45 45 664 #define vs46 46 665 #define vs47 47 666 #define vs48 48 667 #define vs49 49 668 #define vs50 50 669 #define vs51 51 670 #define vs52 52 671 #define vs53 53 672 #define vs54 54 673 #define vs55 55 674 #define vs56 56 675 #define vs57 57 676 #define vs58 58 677 #define vs59 59 678 #define vs60 60 679 #define vs61 61 680 #define vs62 62 681 #define vs63 63 682 683 /* SPE Registers (EVPRs) */ 684 685 #define evr0 0 686 #define evr1 1 687 #define evr2 2 688 #define evr3 3 689 #define evr4 4 690 #define evr5 5 691 #define evr6 6 692 #define evr7 7 693 #define evr8 8 694 #define evr9 9 695 #define evr10 10 696 #define evr11 11 697 #define evr12 12 698 #define evr13 13 699 #define evr14 14 700 #define evr15 15 701 #define evr16 16 702 #define evr17 17 703 #define evr18 18 704 #define evr19 19 705 #define evr20 20 706 #define evr21 21 707 #define evr22 22 708 #define evr23 23 709 #define evr24 24 710 #define evr25 25 711 #define evr26 26 712 #define evr27 27 713 #define evr28 28 714 #define evr29 29 715 #define evr30 30 716 #define evr31 31 717 718 /* some stab codes */ 719 #define N_FUN 36 720 #define N_RSYM 64 721 #define N_SLINE 68 722 #define N_SO 100 723 724 #define RFSCV .long 0x4c0000a4 725 726 /* 727 * Create an endian fixup trampoline 728 * 729 * This starts with a "tdi 0,0,0x48" instruction which is 730 * essentially a "trap never", and thus akin to a nop. 731 * 732 * The opcode for this instruction read with the wrong endian 733 * however results in a b . + 8 734 * 735 * So essentially we use that trick to execute the following 736 * trampoline in "reverse endian" if we are running with the 737 * MSR_LE bit set the "wrong" way for whatever endianness the 738 * kernel is built for. 739 */ 740 741 #ifdef CONFIG_PPC_BOOK3E 742 #define FIXUP_ENDIAN 743 #else 744 /* 745 * This version may be used in HV or non-HV context. 746 * MSR[EE] must be disabled. 747 */ 748 #define FIXUP_ENDIAN \ 749 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ 750 b 191f; /* Skip trampoline if endian is good */ \ 751 .long 0xa600607d; /* mfmsr r11 */ \ 752 .long 0x01006b69; /* xori r11,r11,1 */ \ 753 .long 0x00004039; /* li r10,0 */ \ 754 .long 0x6401417d; /* mtmsrd r10,1 */ \ 755 .long 0x05009f42; /* bcl 20,31,$+4 */ \ 756 .long 0xa602487d; /* mflr r10 */ \ 757 .long 0x14004a39; /* addi r10,r10,20 */ \ 758 .long 0xa6035a7d; /* mtsrr0 r10 */ \ 759 .long 0xa6037b7d; /* mtsrr1 r11 */ \ 760 .long 0x2400004c; /* rfid */ \ 761 191: 762 763 /* 764 * This version that may only be used with MSR[HV]=1 765 * - Does not clear MSR[RI], so more robust. 766 * - Slightly smaller and faster. 767 */ 768 #define FIXUP_ENDIAN_HV \ 769 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ 770 b 191f; /* Skip trampoline if endian is good */ \ 771 .long 0xa600607d; /* mfmsr r11 */ \ 772 .long 0x01006b69; /* xori r11,r11,1 */ \ 773 .long 0x05009f42; /* bcl 20,31,$+4 */ \ 774 .long 0xa602487d; /* mflr r10 */ \ 775 .long 0x14004a39; /* addi r10,r10,20 */ \ 776 .long 0xa64b5a7d; /* mthsrr0 r10 */ \ 777 .long 0xa64b7b7d; /* mthsrr1 r11 */ \ 778 .long 0x2402004c; /* hrfid */ \ 779 191: 780 781 #endif /* !CONFIG_PPC_BOOK3E */ 782 783 #endif /* __ASSEMBLY__ */ 784 785 /* 786 * Helper macro for exception table entries 787 */ 788 #define EX_TABLE(_fault, _target) \ 789 stringify_in_c(.section __ex_table,"a";)\ 790 stringify_in_c(.balign 4;) \ 791 stringify_in_c(.long (_fault) - . ;) \ 792 stringify_in_c(.long (_target) - . ;) \ 793 stringify_in_c(.previous) 794 795 #ifdef CONFIG_PPC_FSL_BOOK3E 796 #define BTB_FLUSH(reg) \ 797 lis reg,BUCSR_INIT@h; \ 798 ori reg,reg,BUCSR_INIT@l; \ 799 mtspr SPRN_BUCSR,reg; \ 800 isync; 801 #else 802 #define BTB_FLUSH(reg) 803 #endif /* CONFIG_PPC_FSL_BOOK3E */ 804 805 #endif /* _ASM_POWERPC_PPC_ASM_H */ 806