1 /* 2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. 3 */ 4 #ifndef _ASM_POWERPC_PPC_ASM_H 5 #define _ASM_POWERPC_PPC_ASM_H 6 7 #include <linux/stringify.h> 8 #include <asm/asm-compat.h> 9 #include <asm/processor.h> 10 #include <asm/ppc-opcode.h> 11 #include <asm/firmware.h> 12 13 #ifndef __ASSEMBLY__ 14 #error __FILE__ should only be used in assembler files 15 #else 16 17 #define SZL (BITS_PER_LONG/8) 18 19 /* 20 * Stuff for accurate CPU time accounting. 21 * These macros handle transitions between user and system state 22 * in exception entry and exit and accumulate time to the 23 * user_time and system_time fields in the paca. 24 */ 25 26 #ifndef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE 27 #define ACCOUNT_CPU_USER_ENTRY(ra, rb) 28 #define ACCOUNT_CPU_USER_EXIT(ra, rb) 29 #define ACCOUNT_STOLEN_TIME 30 #else 31 #define ACCOUNT_CPU_USER_ENTRY(ra, rb) \ 32 MFTB(ra); /* get timebase */ \ 33 ld rb,PACA_STARTTIME_USER(r13); \ 34 std ra,PACA_STARTTIME(r13); \ 35 subf rb,rb,ra; /* subtract start value */ \ 36 ld ra,PACA_USER_TIME(r13); \ 37 add ra,ra,rb; /* add on to user time */ \ 38 std ra,PACA_USER_TIME(r13); \ 39 40 #define ACCOUNT_CPU_USER_EXIT(ra, rb) \ 41 MFTB(ra); /* get timebase */ \ 42 ld rb,PACA_STARTTIME(r13); \ 43 std ra,PACA_STARTTIME_USER(r13); \ 44 subf rb,rb,ra; /* subtract start value */ \ 45 ld ra,PACA_SYSTEM_TIME(r13); \ 46 add ra,ra,rb; /* add on to system time */ \ 47 std ra,PACA_SYSTEM_TIME(r13) 48 49 #ifdef CONFIG_PPC_SPLPAR 50 #define ACCOUNT_STOLEN_TIME \ 51 BEGIN_FW_FTR_SECTION; \ 52 beq 33f; \ 53 /* from user - see if there are any DTL entries to process */ \ 54 ld r10,PACALPPACAPTR(r13); /* get ptr to VPA */ \ 55 ld r11,PACA_DTL_RIDX(r13); /* get log read index */ \ 56 addi r10,r10,LPPACA_DTLIDX; \ 57 LDX_BE r10,0,r10; /* get log write index */ \ 58 cmpd cr1,r11,r10; \ 59 beq+ cr1,33f; \ 60 bl accumulate_stolen_time; \ 61 ld r12,_MSR(r1); \ 62 andi. r10,r12,MSR_PR; /* Restore cr0 (coming from user) */ \ 63 33: \ 64 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR) 65 66 #else /* CONFIG_PPC_SPLPAR */ 67 #define ACCOUNT_STOLEN_TIME 68 69 #endif /* CONFIG_PPC_SPLPAR */ 70 71 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */ 72 73 /* 74 * Macros for storing registers into and loading registers from 75 * exception frames. 76 */ 77 #ifdef __powerpc64__ 78 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base) 79 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base) 80 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) 81 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) 82 #else 83 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) 84 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) 85 #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \ 86 SAVE_10GPRS(22, base) 87 #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \ 88 REST_10GPRS(22, base) 89 #endif 90 91 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) 92 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) 93 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) 94 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) 95 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) 96 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) 97 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) 98 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) 99 100 #define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base) 101 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) 102 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) 103 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) 104 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) 105 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) 106 #define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base) 107 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) 108 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) 109 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) 110 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) 111 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) 112 113 #define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b 114 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) 115 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) 116 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) 117 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) 118 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) 119 #define REST_VR(n,b,base) li b,16*(n); lvx n,base,b 120 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) 121 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) 122 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) 123 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) 124 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) 125 126 #ifdef __BIG_ENDIAN__ 127 #define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base) 128 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base) 129 #else 130 #define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \ 131 STXVD2X(n,b,base); \ 132 XXSWAPD(n,n) 133 134 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \ 135 XXSWAPD(n,n) 136 #endif 137 /* Save the lower 32 VSRs in the thread VSR region */ 138 #define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b) 139 #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) 140 #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base) 141 #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base) 142 #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base) 143 #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) 144 #define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b) 145 #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base) 146 #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base) 147 #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base) 148 #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base) 149 #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base) 150 151 /* 152 * b = base register for addressing, o = base offset from register of 1st EVR 153 * n = first EVR, s = scratch 154 */ 155 #define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b) 156 #define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o) 157 #define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o) 158 #define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o) 159 #define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o) 160 #define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o) 161 #define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n 162 #define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o) 163 #define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o) 164 #define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o) 165 #define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o) 166 #define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o) 167 168 /* Macros to adjust thread priority for hardware multithreading */ 169 #define HMT_VERY_LOW or 31,31,31 # very low priority 170 #define HMT_LOW or 1,1,1 171 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority 172 #define HMT_MEDIUM or 2,2,2 173 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority 174 #define HMT_HIGH or 3,3,3 175 #define HMT_EXTRA_HIGH or 7,7,7 # power7 only 176 177 #ifdef CONFIG_PPC64 178 #define ULONG_SIZE 8 179 #else 180 #define ULONG_SIZE 4 181 #endif 182 #define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE)) 183 #define VCPU_GPR(n) __VCPU_GPR(__REG_##n) 184 185 #ifdef __KERNEL__ 186 #ifdef CONFIG_PPC64 187 188 #define STACKFRAMESIZE 256 189 #define __STK_REG(i) (112 + ((i)-14)*8) 190 #define STK_REG(i) __STK_REG(__REG_##i) 191 192 #if defined(_CALL_ELF) && _CALL_ELF == 2 193 #define STK_GOT 24 194 #define __STK_PARAM(i) (32 + ((i)-3)*8) 195 #else 196 #define STK_GOT 40 197 #define __STK_PARAM(i) (48 + ((i)-3)*8) 198 #endif 199 #define STK_PARAM(i) __STK_PARAM(__REG_##i) 200 201 #if defined(_CALL_ELF) && _CALL_ELF == 2 202 203 #define _GLOBAL(name) \ 204 .section ".text"; \ 205 .align 2 ; \ 206 .type name,@function; \ 207 .globl name; \ 208 name: 209 210 #define _GLOBAL_TOC(name) \ 211 .section ".text"; \ 212 .align 2 ; \ 213 .type name,@function; \ 214 .globl name; \ 215 name: \ 216 0: addis r2,r12,(.TOC.-0b)@ha; \ 217 addi r2,r2,(.TOC.-0b)@l; \ 218 .localentry name,.-name 219 220 #define _KPROBE(name) \ 221 .section ".kprobes.text","a"; \ 222 .align 2 ; \ 223 .type name,@function; \ 224 .globl name; \ 225 name: 226 227 #define DOTSYM(a) a 228 229 #else 230 231 #define XGLUE(a,b) a##b 232 #define GLUE(a,b) XGLUE(a,b) 233 234 #define _GLOBAL(name) \ 235 .section ".text"; \ 236 .align 2 ; \ 237 .globl name; \ 238 .globl GLUE(.,name); \ 239 .section ".opd","aw"; \ 240 name: \ 241 .quad GLUE(.,name); \ 242 .quad .TOC.@tocbase; \ 243 .quad 0; \ 244 .previous; \ 245 .type GLUE(.,name),@function; \ 246 GLUE(.,name): 247 248 #define _GLOBAL_TOC(name) _GLOBAL(name) 249 250 #define _KPROBE(name) \ 251 .section ".kprobes.text","a"; \ 252 .align 2 ; \ 253 .globl name; \ 254 .globl GLUE(.,name); \ 255 .section ".opd","aw"; \ 256 name: \ 257 .quad GLUE(.,name); \ 258 .quad .TOC.@tocbase; \ 259 .quad 0; \ 260 .previous; \ 261 .type GLUE(.,name),@function; \ 262 GLUE(.,name): 263 264 #define DOTSYM(a) GLUE(.,a) 265 266 #endif 267 268 #else /* 32-bit */ 269 270 #define _ENTRY(n) \ 271 .globl n; \ 272 n: 273 274 #define _GLOBAL(n) \ 275 .text; \ 276 .stabs __stringify(n:F-1),N_FUN,0,0,n;\ 277 .globl n; \ 278 n: 279 280 #define _GLOBAL_TOC(name) _GLOBAL(name) 281 282 #define _KPROBE(n) \ 283 .section ".kprobes.text","a"; \ 284 .globl n; \ 285 n: 286 287 #endif 288 289 /* 290 * LOAD_REG_IMMEDIATE(rn, expr) 291 * Loads the value of the constant expression 'expr' into register 'rn' 292 * using immediate instructions only. Use this when it's important not 293 * to reference other data (i.e. on ppc64 when the TOC pointer is not 294 * valid) and when 'expr' is a constant or absolute address. 295 * 296 * LOAD_REG_ADDR(rn, name) 297 * Loads the address of label 'name' into register 'rn'. Use this when 298 * you don't particularly need immediate instructions only, but you need 299 * the whole address in one register (e.g. it's a structure address and 300 * you want to access various offsets within it). On ppc32 this is 301 * identical to LOAD_REG_IMMEDIATE. 302 * 303 * LOAD_REG_ADDR_PIC(rn, name) 304 * Loads the address of label 'name' into register 'run'. Use this when 305 * the kernel doesn't run at the linked or relocated address. Please 306 * note that this macro will clobber the lr register. 307 * 308 * LOAD_REG_ADDRBASE(rn, name) 309 * ADDROFF(name) 310 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into 311 * register 'rn'. ADDROFF(name) returns the remainder of the address as 312 * a constant expression. ADDROFF(name) is a signed expression < 16 bits 313 * in size, so is suitable for use directly as an offset in load and store 314 * instructions. Use this when loading/storing a single word or less as: 315 * LOAD_REG_ADDRBASE(rX, name) 316 * ld rY,ADDROFF(name)(rX) 317 */ 318 319 /* Be careful, this will clobber the lr register. */ 320 #define LOAD_REG_ADDR_PIC(reg, name) \ 321 bl 0f; \ 322 0: mflr reg; \ 323 addis reg,reg,(name - 0b)@ha; \ 324 addi reg,reg,(name - 0b)@l; 325 326 #ifdef __powerpc64__ 327 #ifdef HAVE_AS_ATHIGH 328 #define __AS_ATHIGH high 329 #else 330 #define __AS_ATHIGH h 331 #endif 332 #define LOAD_REG_IMMEDIATE(reg,expr) \ 333 lis reg,(expr)@highest; \ 334 ori reg,reg,(expr)@higher; \ 335 rldicr reg,reg,32,31; \ 336 oris reg,reg,(expr)@__AS_ATHIGH; \ 337 ori reg,reg,(expr)@l; 338 339 #define LOAD_REG_ADDR(reg,name) \ 340 ld reg,name@got(r2) 341 342 #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name) 343 #define ADDROFF(name) 0 344 345 /* offsets for stack frame layout */ 346 #define LRSAVE 16 347 348 #else /* 32-bit */ 349 350 #define LOAD_REG_IMMEDIATE(reg,expr) \ 351 lis reg,(expr)@ha; \ 352 addi reg,reg,(expr)@l; 353 354 #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name) 355 356 #define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha 357 #define ADDROFF(name) name@l 358 359 /* offsets for stack frame layout */ 360 #define LRSAVE 4 361 362 #endif 363 364 /* various errata or part fixups */ 365 #ifdef CONFIG_PPC601_SYNC_FIX 366 #define SYNC \ 367 BEGIN_FTR_SECTION \ 368 sync; \ 369 isync; \ 370 END_FTR_SECTION_IFSET(CPU_FTR_601) 371 #define SYNC_601 \ 372 BEGIN_FTR_SECTION \ 373 sync; \ 374 END_FTR_SECTION_IFSET(CPU_FTR_601) 375 #define ISYNC_601 \ 376 BEGIN_FTR_SECTION \ 377 isync; \ 378 END_FTR_SECTION_IFSET(CPU_FTR_601) 379 #else 380 #define SYNC 381 #define SYNC_601 382 #define ISYNC_601 383 #endif 384 385 #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E) 386 #define MFTB(dest) \ 387 90: mfspr dest, SPRN_TBRL; \ 388 BEGIN_FTR_SECTION_NESTED(96); \ 389 cmpwi dest,0; \ 390 beq- 90b; \ 391 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) 392 #elif defined(CONFIG_8xx) 393 #define MFTB(dest) mftb dest 394 #else 395 #define MFTB(dest) mfspr dest, SPRN_TBRL 396 #endif 397 398 #ifndef CONFIG_SMP 399 #define TLBSYNC 400 #else /* CONFIG_SMP */ 401 /* tlbsync is not implemented on 601 */ 402 #define TLBSYNC \ 403 BEGIN_FTR_SECTION \ 404 tlbsync; \ 405 sync; \ 406 END_FTR_SECTION_IFCLR(CPU_FTR_601) 407 #endif 408 409 #ifdef CONFIG_PPC64 410 #define MTOCRF(FXM, RS) \ 411 BEGIN_FTR_SECTION_NESTED(848); \ 412 mtcrf (FXM), RS; \ 413 FTR_SECTION_ELSE_NESTED(848); \ 414 mtocrf (FXM), RS; \ 415 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848) 416 #endif 417 418 /* 419 * This instruction is not implemented on the PPC 603 or 601; however, on 420 * the 403GCX and 405GP tlbia IS defined and tlbie is not. 421 * All of these instructions exist in the 8xx, they have magical powers, 422 * and they must be used. 423 */ 424 425 #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx) 426 #define tlbia \ 427 li r4,1024; \ 428 mtctr r4; \ 429 lis r4,KERNELBASE@h; \ 430 .machine push; \ 431 .machine "power4"; \ 432 0: tlbie r4; \ 433 .machine pop; \ 434 addi r4,r4,0x1000; \ 435 bdnz 0b 436 #endif 437 438 439 #ifdef CONFIG_IBM440EP_ERR42 440 #define PPC440EP_ERR42 isync 441 #else 442 #define PPC440EP_ERR42 443 #endif 444 445 /* The following stops all load and store data streams associated with stream 446 * ID (ie. streams created explicitly). The embedded and server mnemonics for 447 * dcbt are different so we use machine "power4" here explicitly. 448 */ 449 #define DCBT_STOP_ALL_STREAM_IDS(scratch) \ 450 .machine push ; \ 451 .machine "power4" ; \ 452 lis scratch,0x60000000@h; \ 453 dcbt r0,scratch,0b01010; \ 454 .machine pop 455 456 /* 457 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them 458 * keep the address intact to be compatible with code shared with 459 * 32-bit classic. 460 * 461 * On the other hand, I find it useful to have them behave as expected 462 * by their name (ie always do the addition) on 64-bit BookE 463 */ 464 #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64) 465 #define toreal(rd) 466 #define fromreal(rd) 467 468 /* 469 * We use addis to ensure compatibility with the "classic" ppc versions of 470 * these macros, which use rs = 0 to get the tophys offset in rd, rather than 471 * converting the address in r0, and so this version has to do that too 472 * (i.e. set register rd to 0 when rs == 0). 473 */ 474 #define tophys(rd,rs) \ 475 addis rd,rs,0 476 477 #define tovirt(rd,rs) \ 478 addis rd,rs,0 479 480 #elif defined(CONFIG_PPC64) 481 #define toreal(rd) /* we can access c000... in real mode */ 482 #define fromreal(rd) 483 484 #define tophys(rd,rs) \ 485 clrldi rd,rs,2 486 487 #define tovirt(rd,rs) \ 488 rotldi rd,rs,16; \ 489 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\ 490 rotldi rd,rd,48 491 #else 492 /* 493 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the 494 * physical base address of RAM at compile time. 495 */ 496 #define toreal(rd) tophys(rd,rd) 497 #define fromreal(rd) tovirt(rd,rd) 498 499 #define tophys(rd,rs) \ 500 0: addis rd,rs,-PAGE_OFFSET@h; \ 501 .section ".vtop_fixup","aw"; \ 502 .align 1; \ 503 .long 0b; \ 504 .previous 505 506 #define tovirt(rd,rs) \ 507 0: addis rd,rs,PAGE_OFFSET@h; \ 508 .section ".ptov_fixup","aw"; \ 509 .align 1; \ 510 .long 0b; \ 511 .previous 512 #endif 513 514 #ifdef CONFIG_PPC_BOOK3S_64 515 #define RFI rfid 516 #define MTMSRD(r) mtmsrd r 517 #define MTMSR_EERI(reg) mtmsrd reg,1 518 #else 519 #define FIX_SRR1(ra, rb) 520 #ifndef CONFIG_40x 521 #define RFI rfi 522 #else 523 #define RFI rfi; b . /* Prevent prefetch past rfi */ 524 #endif 525 #define MTMSRD(r) mtmsr r 526 #define MTMSR_EERI(reg) mtmsr reg 527 #define CLR_TOP32(r) 528 #endif 529 530 #endif /* __KERNEL__ */ 531 532 /* The boring bits... */ 533 534 /* Condition Register Bit Fields */ 535 536 #define cr0 0 537 #define cr1 1 538 #define cr2 2 539 #define cr3 3 540 #define cr4 4 541 #define cr5 5 542 #define cr6 6 543 #define cr7 7 544 545 546 /* 547 * General Purpose Registers (GPRs) 548 * 549 * The lower case r0-r31 should be used in preference to the upper 550 * case R0-R31 as they provide more error checking in the assembler. 551 * Use R0-31 only when really nessesary. 552 */ 553 554 #define r0 %r0 555 #define r1 %r1 556 #define r2 %r2 557 #define r3 %r3 558 #define r4 %r4 559 #define r5 %r5 560 #define r6 %r6 561 #define r7 %r7 562 #define r8 %r8 563 #define r9 %r9 564 #define r10 %r10 565 #define r11 %r11 566 #define r12 %r12 567 #define r13 %r13 568 #define r14 %r14 569 #define r15 %r15 570 #define r16 %r16 571 #define r17 %r17 572 #define r18 %r18 573 #define r19 %r19 574 #define r20 %r20 575 #define r21 %r21 576 #define r22 %r22 577 #define r23 %r23 578 #define r24 %r24 579 #define r25 %r25 580 #define r26 %r26 581 #define r27 %r27 582 #define r28 %r28 583 #define r29 %r29 584 #define r30 %r30 585 #define r31 %r31 586 587 588 /* Floating Point Registers (FPRs) */ 589 590 #define fr0 0 591 #define fr1 1 592 #define fr2 2 593 #define fr3 3 594 #define fr4 4 595 #define fr5 5 596 #define fr6 6 597 #define fr7 7 598 #define fr8 8 599 #define fr9 9 600 #define fr10 10 601 #define fr11 11 602 #define fr12 12 603 #define fr13 13 604 #define fr14 14 605 #define fr15 15 606 #define fr16 16 607 #define fr17 17 608 #define fr18 18 609 #define fr19 19 610 #define fr20 20 611 #define fr21 21 612 #define fr22 22 613 #define fr23 23 614 #define fr24 24 615 #define fr25 25 616 #define fr26 26 617 #define fr27 27 618 #define fr28 28 619 #define fr29 29 620 #define fr30 30 621 #define fr31 31 622 623 /* AltiVec Registers (VPRs) */ 624 625 #define v0 0 626 #define v1 1 627 #define v2 2 628 #define v3 3 629 #define v4 4 630 #define v5 5 631 #define v6 6 632 #define v7 7 633 #define v8 8 634 #define v9 9 635 #define v10 10 636 #define v11 11 637 #define v12 12 638 #define v13 13 639 #define v14 14 640 #define v15 15 641 #define v16 16 642 #define v17 17 643 #define v18 18 644 #define v19 19 645 #define v20 20 646 #define v21 21 647 #define v22 22 648 #define v23 23 649 #define v24 24 650 #define v25 25 651 #define v26 26 652 #define v27 27 653 #define v28 28 654 #define v29 29 655 #define v30 30 656 #define v31 31 657 658 /* VSX Registers (VSRs) */ 659 660 #define vs0 0 661 #define vs1 1 662 #define vs2 2 663 #define vs3 3 664 #define vs4 4 665 #define vs5 5 666 #define vs6 6 667 #define vs7 7 668 #define vs8 8 669 #define vs9 9 670 #define vs10 10 671 #define vs11 11 672 #define vs12 12 673 #define vs13 13 674 #define vs14 14 675 #define vs15 15 676 #define vs16 16 677 #define vs17 17 678 #define vs18 18 679 #define vs19 19 680 #define vs20 20 681 #define vs21 21 682 #define vs22 22 683 #define vs23 23 684 #define vs24 24 685 #define vs25 25 686 #define vs26 26 687 #define vs27 27 688 #define vs28 28 689 #define vs29 29 690 #define vs30 30 691 #define vs31 31 692 #define vs32 32 693 #define vs33 33 694 #define vs34 34 695 #define vs35 35 696 #define vs36 36 697 #define vs37 37 698 #define vs38 38 699 #define vs39 39 700 #define vs40 40 701 #define vs41 41 702 #define vs42 42 703 #define vs43 43 704 #define vs44 44 705 #define vs45 45 706 #define vs46 46 707 #define vs47 47 708 #define vs48 48 709 #define vs49 49 710 #define vs50 50 711 #define vs51 51 712 #define vs52 52 713 #define vs53 53 714 #define vs54 54 715 #define vs55 55 716 #define vs56 56 717 #define vs57 57 718 #define vs58 58 719 #define vs59 59 720 #define vs60 60 721 #define vs61 61 722 #define vs62 62 723 #define vs63 63 724 725 /* SPE Registers (EVPRs) */ 726 727 #define evr0 0 728 #define evr1 1 729 #define evr2 2 730 #define evr3 3 731 #define evr4 4 732 #define evr5 5 733 #define evr6 6 734 #define evr7 7 735 #define evr8 8 736 #define evr9 9 737 #define evr10 10 738 #define evr11 11 739 #define evr12 12 740 #define evr13 13 741 #define evr14 14 742 #define evr15 15 743 #define evr16 16 744 #define evr17 17 745 #define evr18 18 746 #define evr19 19 747 #define evr20 20 748 #define evr21 21 749 #define evr22 22 750 #define evr23 23 751 #define evr24 24 752 #define evr25 25 753 #define evr26 26 754 #define evr27 27 755 #define evr28 28 756 #define evr29 29 757 #define evr30 30 758 #define evr31 31 759 760 /* some stab codes */ 761 #define N_FUN 36 762 #define N_RSYM 64 763 #define N_SLINE 68 764 #define N_SO 100 765 766 /* 767 * Create an endian fixup trampoline 768 * 769 * This starts with a "tdi 0,0,0x48" instruction which is 770 * essentially a "trap never", and thus akin to a nop. 771 * 772 * The opcode for this instruction read with the wrong endian 773 * however results in a b . + 8 774 * 775 * So essentially we use that trick to execute the following 776 * trampoline in "reverse endian" if we are running with the 777 * MSR_LE bit set the "wrong" way for whatever endianness the 778 * kernel is built for. 779 */ 780 781 #ifdef CONFIG_PPC_BOOK3E 782 #define FIXUP_ENDIAN 783 #else 784 #define FIXUP_ENDIAN \ 785 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ 786 b $+36; /* Skip trampoline if endian is good */ \ 787 .long 0x05009f42; /* bcl 20,31,$+4 */ \ 788 .long 0xa602487d; /* mflr r10 */ \ 789 .long 0x1c004a39; /* addi r10,r10,28 */ \ 790 .long 0xa600607d; /* mfmsr r11 */ \ 791 .long 0x01006b69; /* xori r11,r11,1 */ \ 792 .long 0xa6035a7d; /* mtsrr0 r10 */ \ 793 .long 0xa6037b7d; /* mtsrr1 r11 */ \ 794 .long 0x2400004c /* rfid */ 795 #endif /* !CONFIG_PPC_BOOK3E */ 796 #endif /* __ASSEMBLY__ */ 797 #endif /* _ASM_POWERPC_PPC_ASM_H */ 798