1 /* 2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. 3 */ 4 #ifndef _ASM_POWERPC_PPC_ASM_H 5 #define _ASM_POWERPC_PPC_ASM_H 6 7 #include <linux/stringify.h> 8 #include <asm/asm-compat.h> 9 #include <asm/processor.h> 10 #include <asm/ppc-opcode.h> 11 #include <asm/firmware.h> 12 13 #ifndef __ASSEMBLY__ 14 #error __FILE__ should only be used in assembler files 15 #else 16 17 #define SZL (BITS_PER_LONG/8) 18 19 /* 20 * Stuff for accurate CPU time accounting. 21 * These macros handle transitions between user and system state 22 * in exception entry and exit and accumulate time to the 23 * user_time and system_time fields in the paca. 24 */ 25 26 #ifndef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE 27 #define ACCOUNT_CPU_USER_ENTRY(ra, rb) 28 #define ACCOUNT_CPU_USER_EXIT(ra, rb) 29 #define ACCOUNT_STOLEN_TIME 30 #else 31 #define ACCOUNT_CPU_USER_ENTRY(ra, rb) \ 32 MFTB(ra); /* get timebase */ \ 33 ld rb,PACA_STARTTIME_USER(r13); \ 34 std ra,PACA_STARTTIME(r13); \ 35 subf rb,rb,ra; /* subtract start value */ \ 36 ld ra,PACA_USER_TIME(r13); \ 37 add ra,ra,rb; /* add on to user time */ \ 38 std ra,PACA_USER_TIME(r13); \ 39 40 #define ACCOUNT_CPU_USER_EXIT(ra, rb) \ 41 MFTB(ra); /* get timebase */ \ 42 ld rb,PACA_STARTTIME(r13); \ 43 std ra,PACA_STARTTIME_USER(r13); \ 44 subf rb,rb,ra; /* subtract start value */ \ 45 ld ra,PACA_SYSTEM_TIME(r13); \ 46 add ra,ra,rb; /* add on to system time */ \ 47 std ra,PACA_SYSTEM_TIME(r13) 48 49 #ifdef CONFIG_PPC_SPLPAR 50 #define ACCOUNT_STOLEN_TIME \ 51 BEGIN_FW_FTR_SECTION; \ 52 beq 33f; \ 53 /* from user - see if there are any DTL entries to process */ \ 54 ld r10,PACALPPACAPTR(r13); /* get ptr to VPA */ \ 55 ld r11,PACA_DTL_RIDX(r13); /* get log read index */ \ 56 addi r10,r10,LPPACA_DTLIDX; \ 57 LDX_BE r10,0,r10; /* get log write index */ \ 58 cmpd cr1,r11,r10; \ 59 beq+ cr1,33f; \ 60 bl accumulate_stolen_time; \ 61 ld r12,_MSR(r1); \ 62 andi. r10,r12,MSR_PR; /* Restore cr0 (coming from user) */ \ 63 33: \ 64 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR) 65 66 #else /* CONFIG_PPC_SPLPAR */ 67 #define ACCOUNT_STOLEN_TIME 68 69 #endif /* CONFIG_PPC_SPLPAR */ 70 71 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */ 72 73 /* 74 * Macros for storing registers into and loading registers from 75 * exception frames. 76 */ 77 #ifdef __powerpc64__ 78 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base) 79 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base) 80 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) 81 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) 82 #else 83 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) 84 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) 85 #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \ 86 SAVE_10GPRS(22, base) 87 #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \ 88 REST_10GPRS(22, base) 89 #endif 90 91 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) 92 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) 93 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) 94 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) 95 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) 96 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) 97 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) 98 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) 99 100 #define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base) 101 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) 102 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) 103 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) 104 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) 105 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) 106 #define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base) 107 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) 108 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) 109 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) 110 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) 111 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) 112 113 #define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b 114 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) 115 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) 116 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) 117 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) 118 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) 119 #define REST_VR(n,b,base) li b,16*(n); lvx n,base,b 120 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) 121 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) 122 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) 123 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) 124 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) 125 126 #ifdef __BIG_ENDIAN__ 127 #define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base) 128 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base) 129 #else 130 #define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \ 131 STXVD2X(n,b,base); \ 132 XXSWAPD(n,n) 133 134 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \ 135 XXSWAPD(n,n) 136 #endif 137 /* Save the lower 32 VSRs in the thread VSR region */ 138 #define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b) 139 #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) 140 #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base) 141 #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base) 142 #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base) 143 #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) 144 #define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b) 145 #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base) 146 #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base) 147 #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base) 148 #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base) 149 #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base) 150 151 /* 152 * b = base register for addressing, o = base offset from register of 1st EVR 153 * n = first EVR, s = scratch 154 */ 155 #define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b) 156 #define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o) 157 #define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o) 158 #define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o) 159 #define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o) 160 #define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o) 161 #define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n 162 #define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o) 163 #define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o) 164 #define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o) 165 #define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o) 166 #define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o) 167 168 /* Macros to adjust thread priority for hardware multithreading */ 169 #define HMT_VERY_LOW or 31,31,31 # very low priority 170 #define HMT_LOW or 1,1,1 171 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority 172 #define HMT_MEDIUM or 2,2,2 173 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority 174 #define HMT_HIGH or 3,3,3 175 #define HMT_EXTRA_HIGH or 7,7,7 # power7 only 176 177 #ifdef CONFIG_PPC64 178 #define ULONG_SIZE 8 179 #else 180 #define ULONG_SIZE 4 181 #endif 182 #define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE)) 183 #define VCPU_GPR(n) __VCPU_GPR(__REG_##n) 184 185 #ifdef __KERNEL__ 186 #ifdef CONFIG_PPC64 187 188 #define STACKFRAMESIZE 256 189 #define __STK_REG(i) (112 + ((i)-14)*8) 190 #define STK_REG(i) __STK_REG(__REG_##i) 191 192 #if defined(_CALL_ELF) && _CALL_ELF == 2 193 #define STK_GOT 24 194 #define __STK_PARAM(i) (32 + ((i)-3)*8) 195 #else 196 #define STK_GOT 40 197 #define __STK_PARAM(i) (48 + ((i)-3)*8) 198 #endif 199 #define STK_PARAM(i) __STK_PARAM(__REG_##i) 200 201 #if defined(_CALL_ELF) && _CALL_ELF == 2 202 203 #define _GLOBAL(name) \ 204 .section ".text"; \ 205 .align 2 ; \ 206 .type name,@function; \ 207 .globl name; \ 208 name: 209 210 #define _GLOBAL_TOC(name) \ 211 .section ".text"; \ 212 .align 2 ; \ 213 .type name,@function; \ 214 .globl name; \ 215 name: \ 216 0: addis r2,r12,(.TOC.-0b)@ha; \ 217 addi r2,r2,(.TOC.-0b)@l; \ 218 .localentry name,.-name 219 220 #define _KPROBE(name) \ 221 .section ".kprobes.text","a"; \ 222 .align 2 ; \ 223 .type name,@function; \ 224 .globl name; \ 225 name: 226 227 #define DOTSYM(a) a 228 229 #else 230 231 #define XGLUE(a,b) a##b 232 #define GLUE(a,b) XGLUE(a,b) 233 234 #define _GLOBAL(name) \ 235 .section ".text"; \ 236 .align 2 ; \ 237 .globl name; \ 238 .globl GLUE(.,name); \ 239 .section ".opd","aw"; \ 240 name: \ 241 .quad GLUE(.,name); \ 242 .quad .TOC.@tocbase; \ 243 .quad 0; \ 244 .previous; \ 245 .type GLUE(.,name),@function; \ 246 GLUE(.,name): 247 248 #define _GLOBAL_TOC(name) _GLOBAL(name) 249 250 #define _KPROBE(name) \ 251 .section ".kprobes.text","a"; \ 252 .align 2 ; \ 253 .globl name; \ 254 .globl GLUE(.,name); \ 255 .section ".opd","aw"; \ 256 name: \ 257 .quad GLUE(.,name); \ 258 .quad .TOC.@tocbase; \ 259 .quad 0; \ 260 .previous; \ 261 .type GLUE(.,name),@function; \ 262 GLUE(.,name): 263 264 #define DOTSYM(a) GLUE(.,a) 265 266 #endif 267 268 #else /* 32-bit */ 269 270 #define _ENTRY(n) \ 271 .globl n; \ 272 n: 273 274 #define _GLOBAL(n) \ 275 .text; \ 276 .stabs __stringify(n:F-1),N_FUN,0,0,n;\ 277 .globl n; \ 278 n: 279 280 #define _KPROBE(n) \ 281 .section ".kprobes.text","a"; \ 282 .globl n; \ 283 n: 284 285 #endif 286 287 /* 288 * LOAD_REG_IMMEDIATE(rn, expr) 289 * Loads the value of the constant expression 'expr' into register 'rn' 290 * using immediate instructions only. Use this when it's important not 291 * to reference other data (i.e. on ppc64 when the TOC pointer is not 292 * valid) and when 'expr' is a constant or absolute address. 293 * 294 * LOAD_REG_ADDR(rn, name) 295 * Loads the address of label 'name' into register 'rn'. Use this when 296 * you don't particularly need immediate instructions only, but you need 297 * the whole address in one register (e.g. it's a structure address and 298 * you want to access various offsets within it). On ppc32 this is 299 * identical to LOAD_REG_IMMEDIATE. 300 * 301 * LOAD_REG_ADDR_PIC(rn, name) 302 * Loads the address of label 'name' into register 'run'. Use this when 303 * the kernel doesn't run at the linked or relocated address. Please 304 * note that this macro will clobber the lr register. 305 * 306 * LOAD_REG_ADDRBASE(rn, name) 307 * ADDROFF(name) 308 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into 309 * register 'rn'. ADDROFF(name) returns the remainder of the address as 310 * a constant expression. ADDROFF(name) is a signed expression < 16 bits 311 * in size, so is suitable for use directly as an offset in load and store 312 * instructions. Use this when loading/storing a single word or less as: 313 * LOAD_REG_ADDRBASE(rX, name) 314 * ld rY,ADDROFF(name)(rX) 315 */ 316 317 /* Be careful, this will clobber the lr register. */ 318 #define LOAD_REG_ADDR_PIC(reg, name) \ 319 bl 0f; \ 320 0: mflr reg; \ 321 addis reg,reg,(name - 0b)@ha; \ 322 addi reg,reg,(name - 0b)@l; 323 324 #ifdef __powerpc64__ 325 #ifdef HAVE_AS_ATHIGH 326 #define __AS_ATHIGH high 327 #else 328 #define __AS_ATHIGH h 329 #endif 330 #define LOAD_REG_IMMEDIATE(reg,expr) \ 331 lis reg,(expr)@highest; \ 332 ori reg,reg,(expr)@higher; \ 333 rldicr reg,reg,32,31; \ 334 oris reg,reg,(expr)@__AS_ATHIGH; \ 335 ori reg,reg,(expr)@l; 336 337 #define LOAD_REG_ADDR(reg,name) \ 338 ld reg,name@got(r2) 339 340 #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name) 341 #define ADDROFF(name) 0 342 343 /* offsets for stack frame layout */ 344 #define LRSAVE 16 345 346 #else /* 32-bit */ 347 348 #define LOAD_REG_IMMEDIATE(reg,expr) \ 349 lis reg,(expr)@ha; \ 350 addi reg,reg,(expr)@l; 351 352 #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name) 353 354 #define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha 355 #define ADDROFF(name) name@l 356 357 /* offsets for stack frame layout */ 358 #define LRSAVE 4 359 360 #endif 361 362 /* various errata or part fixups */ 363 #ifdef CONFIG_PPC601_SYNC_FIX 364 #define SYNC \ 365 BEGIN_FTR_SECTION \ 366 sync; \ 367 isync; \ 368 END_FTR_SECTION_IFSET(CPU_FTR_601) 369 #define SYNC_601 \ 370 BEGIN_FTR_SECTION \ 371 sync; \ 372 END_FTR_SECTION_IFSET(CPU_FTR_601) 373 #define ISYNC_601 \ 374 BEGIN_FTR_SECTION \ 375 isync; \ 376 END_FTR_SECTION_IFSET(CPU_FTR_601) 377 #else 378 #define SYNC 379 #define SYNC_601 380 #define ISYNC_601 381 #endif 382 383 #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E) 384 #define MFTB(dest) \ 385 90: mfspr dest, SPRN_TBRL; \ 386 BEGIN_FTR_SECTION_NESTED(96); \ 387 cmpwi dest,0; \ 388 beq- 90b; \ 389 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) 390 #elif defined(CONFIG_8xx) 391 #define MFTB(dest) mftb dest 392 #else 393 #define MFTB(dest) mfspr dest, SPRN_TBRL 394 #endif 395 396 #ifndef CONFIG_SMP 397 #define TLBSYNC 398 #else /* CONFIG_SMP */ 399 /* tlbsync is not implemented on 601 */ 400 #define TLBSYNC \ 401 BEGIN_FTR_SECTION \ 402 tlbsync; \ 403 sync; \ 404 END_FTR_SECTION_IFCLR(CPU_FTR_601) 405 #endif 406 407 #ifdef CONFIG_PPC64 408 #define MTOCRF(FXM, RS) \ 409 BEGIN_FTR_SECTION_NESTED(848); \ 410 mtcrf (FXM), RS; \ 411 FTR_SECTION_ELSE_NESTED(848); \ 412 mtocrf (FXM), RS; \ 413 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848) 414 415 /* 416 * PPR restore macros used in entry_64.S 417 * Used for P7 or later processors 418 */ 419 #define HMT_MEDIUM_LOW_HAS_PPR \ 420 BEGIN_FTR_SECTION_NESTED(944) \ 421 HMT_MEDIUM_LOW; \ 422 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,944) 423 424 #define SET_DEFAULT_THREAD_PPR(ra, rb) \ 425 BEGIN_FTR_SECTION_NESTED(945) \ 426 lis ra,INIT_PPR@highest; /* default ppr=3 */ \ 427 ld rb,PACACURRENT(r13); \ 428 sldi ra,ra,32; /* 11- 13 bits are used for ppr */ \ 429 std ra,TASKTHREADPPR(rb); \ 430 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,945) 431 432 #endif 433 434 /* 435 * This instruction is not implemented on the PPC 603 or 601; however, on 436 * the 403GCX and 405GP tlbia IS defined and tlbie is not. 437 * All of these instructions exist in the 8xx, they have magical powers, 438 * and they must be used. 439 */ 440 441 #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx) 442 #define tlbia \ 443 li r4,1024; \ 444 mtctr r4; \ 445 lis r4,KERNELBASE@h; \ 446 0: tlbie r4; \ 447 addi r4,r4,0x1000; \ 448 bdnz 0b 449 #endif 450 451 452 #ifdef CONFIG_IBM440EP_ERR42 453 #define PPC440EP_ERR42 isync 454 #else 455 #define PPC440EP_ERR42 456 #endif 457 458 /* The following stops all load and store data streams associated with stream 459 * ID (ie. streams created explicitly). The embedded and server mnemonics for 460 * dcbt are different so we use machine "power4" here explicitly. 461 */ 462 #define DCBT_STOP_ALL_STREAM_IDS(scratch) \ 463 .machine push ; \ 464 .machine "power4" ; \ 465 lis scratch,0x60000000@h; \ 466 dcbt r0,scratch,0b01010; \ 467 .machine pop 468 469 /* 470 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them 471 * keep the address intact to be compatible with code shared with 472 * 32-bit classic. 473 * 474 * On the other hand, I find it useful to have them behave as expected 475 * by their name (ie always do the addition) on 64-bit BookE 476 */ 477 #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64) 478 #define toreal(rd) 479 #define fromreal(rd) 480 481 /* 482 * We use addis to ensure compatibility with the "classic" ppc versions of 483 * these macros, which use rs = 0 to get the tophys offset in rd, rather than 484 * converting the address in r0, and so this version has to do that too 485 * (i.e. set register rd to 0 when rs == 0). 486 */ 487 #define tophys(rd,rs) \ 488 addis rd,rs,0 489 490 #define tovirt(rd,rs) \ 491 addis rd,rs,0 492 493 #elif defined(CONFIG_PPC64) 494 #define toreal(rd) /* we can access c000... in real mode */ 495 #define fromreal(rd) 496 497 #define tophys(rd,rs) \ 498 clrldi rd,rs,2 499 500 #define tovirt(rd,rs) \ 501 rotldi rd,rs,16; \ 502 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\ 503 rotldi rd,rd,48 504 #else 505 /* 506 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the 507 * physical base address of RAM at compile time. 508 */ 509 #define toreal(rd) tophys(rd,rd) 510 #define fromreal(rd) tovirt(rd,rd) 511 512 #define tophys(rd,rs) \ 513 0: addis rd,rs,-PAGE_OFFSET@h; \ 514 .section ".vtop_fixup","aw"; \ 515 .align 1; \ 516 .long 0b; \ 517 .previous 518 519 #define tovirt(rd,rs) \ 520 0: addis rd,rs,PAGE_OFFSET@h; \ 521 .section ".ptov_fixup","aw"; \ 522 .align 1; \ 523 .long 0b; \ 524 .previous 525 #endif 526 527 #ifdef CONFIG_PPC_BOOK3S_64 528 #define RFI rfid 529 #define MTMSRD(r) mtmsrd r 530 #define MTMSR_EERI(reg) mtmsrd reg,1 531 #else 532 #define FIX_SRR1(ra, rb) 533 #ifndef CONFIG_40x 534 #define RFI rfi 535 #else 536 #define RFI rfi; b . /* Prevent prefetch past rfi */ 537 #endif 538 #define MTMSRD(r) mtmsr r 539 #define MTMSR_EERI(reg) mtmsr reg 540 #define CLR_TOP32(r) 541 #endif 542 543 #endif /* __KERNEL__ */ 544 545 /* The boring bits... */ 546 547 /* Condition Register Bit Fields */ 548 549 #define cr0 0 550 #define cr1 1 551 #define cr2 2 552 #define cr3 3 553 #define cr4 4 554 #define cr5 5 555 #define cr6 6 556 #define cr7 7 557 558 559 /* 560 * General Purpose Registers (GPRs) 561 * 562 * The lower case r0-r31 should be used in preference to the upper 563 * case R0-R31 as they provide more error checking in the assembler. 564 * Use R0-31 only when really nessesary. 565 */ 566 567 #define r0 %r0 568 #define r1 %r1 569 #define r2 %r2 570 #define r3 %r3 571 #define r4 %r4 572 #define r5 %r5 573 #define r6 %r6 574 #define r7 %r7 575 #define r8 %r8 576 #define r9 %r9 577 #define r10 %r10 578 #define r11 %r11 579 #define r12 %r12 580 #define r13 %r13 581 #define r14 %r14 582 #define r15 %r15 583 #define r16 %r16 584 #define r17 %r17 585 #define r18 %r18 586 #define r19 %r19 587 #define r20 %r20 588 #define r21 %r21 589 #define r22 %r22 590 #define r23 %r23 591 #define r24 %r24 592 #define r25 %r25 593 #define r26 %r26 594 #define r27 %r27 595 #define r28 %r28 596 #define r29 %r29 597 #define r30 %r30 598 #define r31 %r31 599 600 601 /* Floating Point Registers (FPRs) */ 602 603 #define fr0 0 604 #define fr1 1 605 #define fr2 2 606 #define fr3 3 607 #define fr4 4 608 #define fr5 5 609 #define fr6 6 610 #define fr7 7 611 #define fr8 8 612 #define fr9 9 613 #define fr10 10 614 #define fr11 11 615 #define fr12 12 616 #define fr13 13 617 #define fr14 14 618 #define fr15 15 619 #define fr16 16 620 #define fr17 17 621 #define fr18 18 622 #define fr19 19 623 #define fr20 20 624 #define fr21 21 625 #define fr22 22 626 #define fr23 23 627 #define fr24 24 628 #define fr25 25 629 #define fr26 26 630 #define fr27 27 631 #define fr28 28 632 #define fr29 29 633 #define fr30 30 634 #define fr31 31 635 636 /* AltiVec Registers (VPRs) */ 637 638 #define vr0 0 639 #define vr1 1 640 #define vr2 2 641 #define vr3 3 642 #define vr4 4 643 #define vr5 5 644 #define vr6 6 645 #define vr7 7 646 #define vr8 8 647 #define vr9 9 648 #define vr10 10 649 #define vr11 11 650 #define vr12 12 651 #define vr13 13 652 #define vr14 14 653 #define vr15 15 654 #define vr16 16 655 #define vr17 17 656 #define vr18 18 657 #define vr19 19 658 #define vr20 20 659 #define vr21 21 660 #define vr22 22 661 #define vr23 23 662 #define vr24 24 663 #define vr25 25 664 #define vr26 26 665 #define vr27 27 666 #define vr28 28 667 #define vr29 29 668 #define vr30 30 669 #define vr31 31 670 671 /* VSX Registers (VSRs) */ 672 673 #define vsr0 0 674 #define vsr1 1 675 #define vsr2 2 676 #define vsr3 3 677 #define vsr4 4 678 #define vsr5 5 679 #define vsr6 6 680 #define vsr7 7 681 #define vsr8 8 682 #define vsr9 9 683 #define vsr10 10 684 #define vsr11 11 685 #define vsr12 12 686 #define vsr13 13 687 #define vsr14 14 688 #define vsr15 15 689 #define vsr16 16 690 #define vsr17 17 691 #define vsr18 18 692 #define vsr19 19 693 #define vsr20 20 694 #define vsr21 21 695 #define vsr22 22 696 #define vsr23 23 697 #define vsr24 24 698 #define vsr25 25 699 #define vsr26 26 700 #define vsr27 27 701 #define vsr28 28 702 #define vsr29 29 703 #define vsr30 30 704 #define vsr31 31 705 #define vsr32 32 706 #define vsr33 33 707 #define vsr34 34 708 #define vsr35 35 709 #define vsr36 36 710 #define vsr37 37 711 #define vsr38 38 712 #define vsr39 39 713 #define vsr40 40 714 #define vsr41 41 715 #define vsr42 42 716 #define vsr43 43 717 #define vsr44 44 718 #define vsr45 45 719 #define vsr46 46 720 #define vsr47 47 721 #define vsr48 48 722 #define vsr49 49 723 #define vsr50 50 724 #define vsr51 51 725 #define vsr52 52 726 #define vsr53 53 727 #define vsr54 54 728 #define vsr55 55 729 #define vsr56 56 730 #define vsr57 57 731 #define vsr58 58 732 #define vsr59 59 733 #define vsr60 60 734 #define vsr61 61 735 #define vsr62 62 736 #define vsr63 63 737 738 /* SPE Registers (EVPRs) */ 739 740 #define evr0 0 741 #define evr1 1 742 #define evr2 2 743 #define evr3 3 744 #define evr4 4 745 #define evr5 5 746 #define evr6 6 747 #define evr7 7 748 #define evr8 8 749 #define evr9 9 750 #define evr10 10 751 #define evr11 11 752 #define evr12 12 753 #define evr13 13 754 #define evr14 14 755 #define evr15 15 756 #define evr16 16 757 #define evr17 17 758 #define evr18 18 759 #define evr19 19 760 #define evr20 20 761 #define evr21 21 762 #define evr22 22 763 #define evr23 23 764 #define evr24 24 765 #define evr25 25 766 #define evr26 26 767 #define evr27 27 768 #define evr28 28 769 #define evr29 29 770 #define evr30 30 771 #define evr31 31 772 773 /* some stab codes */ 774 #define N_FUN 36 775 #define N_RSYM 64 776 #define N_SLINE 68 777 #define N_SO 100 778 779 /* 780 * Create an endian fixup trampoline 781 * 782 * This starts with a "tdi 0,0,0x48" instruction which is 783 * essentially a "trap never", and thus akin to a nop. 784 * 785 * The opcode for this instruction read with the wrong endian 786 * however results in a b . + 8 787 * 788 * So essentially we use that trick to execute the following 789 * trampoline in "reverse endian" if we are running with the 790 * MSR_LE bit set the "wrong" way for whatever endianness the 791 * kernel is built for. 792 */ 793 794 #ifdef CONFIG_PPC_BOOK3E 795 #define FIXUP_ENDIAN 796 #else 797 #define FIXUP_ENDIAN \ 798 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ 799 b $+36; /* Skip trampoline if endian is good */ \ 800 .long 0x05009f42; /* bcl 20,31,$+4 */ \ 801 .long 0xa602487d; /* mflr r10 */ \ 802 .long 0x1c004a39; /* addi r10,r10,28 */ \ 803 .long 0xa600607d; /* mfmsr r11 */ \ 804 .long 0x01006b69; /* xori r11,r11,1 */ \ 805 .long 0xa6035a7d; /* mtsrr0 r10 */ \ 806 .long 0xa6037b7d; /* mtsrr1 r11 */ \ 807 .long 0x2400004c /* rfid */ 808 #endif /* !CONFIG_PPC_BOOK3E */ 809 #endif /* __ASSEMBLY__ */ 810 #endif /* _ASM_POWERPC_PPC_ASM_H */ 811