1 /* 2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. 3 */ 4 #ifndef _ASM_POWERPC_PPC_ASM_H 5 #define _ASM_POWERPC_PPC_ASM_H 6 7 #include <linux/stringify.h> 8 #include <asm/asm-compat.h> 9 #include <asm/processor.h> 10 #include <asm/ppc-opcode.h> 11 #include <asm/firmware.h> 12 #include <asm/feature-fixups.h> 13 #include <asm/extable.h> 14 15 #ifdef __ASSEMBLY__ 16 17 #define SZL (BITS_PER_LONG/8) 18 19 /* 20 * This expands to a sequence of operations with reg incrementing from 21 * start to end inclusive, of this form: 22 * 23 * op reg, (offset + (width * reg))(base) 24 * 25 * Note that offset is not the offset of the first operation unless start 26 * is zero (or width is zero). 27 */ 28 .macro OP_REGS op, width, start, end, base, offset 29 .Lreg=\start 30 .rept (\end - \start + 1) 31 \op .Lreg, \offset + \width * .Lreg(\base) 32 .Lreg=.Lreg+1 33 .endr 34 .endm 35 36 /* 37 * This expands to a sequence of register clears for regs start to end 38 * inclusive, of the form: 39 * 40 * li rN, 0 41 */ 42 .macro ZEROIZE_REGS start, end 43 .Lreg=\start 44 .rept (\end - \start + 1) 45 li .Lreg, 0 46 .Lreg=.Lreg+1 47 .endr 48 .endm 49 50 /* 51 * Macros for storing registers into and loading registers from 52 * exception frames. 53 */ 54 #ifdef __powerpc64__ 55 #define SAVE_GPRS(start, end, base) OP_REGS std, 8, start, end, base, GPR0 56 #define REST_GPRS(start, end, base) OP_REGS ld, 8, start, end, base, GPR0 57 #define SAVE_NVGPRS(base) SAVE_GPRS(14, 31, base) 58 #define REST_NVGPRS(base) REST_GPRS(14, 31, base) 59 #else 60 #define SAVE_GPRS(start, end, base) OP_REGS stw, 4, start, end, base, GPR0 61 #define REST_GPRS(start, end, base) OP_REGS lwz, 4, start, end, base, GPR0 62 #define SAVE_NVGPRS(base) SAVE_GPRS(13, 31, base) 63 #define REST_NVGPRS(base) REST_GPRS(13, 31, base) 64 #endif 65 66 #define ZEROIZE_GPRS(start, end) ZEROIZE_REGS start, end 67 #ifdef __powerpc64__ 68 #define ZEROIZE_NVGPRS() ZEROIZE_GPRS(14, 31) 69 #else 70 #define ZEROIZE_NVGPRS() ZEROIZE_GPRS(13, 31) 71 #endif 72 #define ZEROIZE_GPR(n) ZEROIZE_GPRS(n, n) 73 74 #define SAVE_GPR(n, base) SAVE_GPRS(n, n, base) 75 #define REST_GPR(n, base) REST_GPRS(n, n, base) 76 77 /* macros for handling user register sanitisation */ 78 #ifdef CONFIG_INTERRUPT_SANITIZE_REGISTERS 79 #define SANITIZE_SYSCALL_GPRS() ZEROIZE_GPR(0); \ 80 ZEROIZE_GPRS(5, 12); \ 81 ZEROIZE_NVGPRS() 82 #define SANITIZE_GPR(n) ZEROIZE_GPR(n) 83 #define SANITIZE_GPRS(start, end) ZEROIZE_GPRS(start, end) 84 #define SANITIZE_NVGPRS() ZEROIZE_NVGPRS() 85 #define SANITIZE_RESTORE_NVGPRS() REST_NVGPRS(r1) 86 #define HANDLER_RESTORE_NVGPRS() 87 #else 88 #define SANITIZE_SYSCALL_GPRS() 89 #define SANITIZE_GPR(n) 90 #define SANITIZE_GPRS(start, end) 91 #define SANITIZE_NVGPRS() 92 #define SANITIZE_RESTORE_NVGPRS() 93 #define HANDLER_RESTORE_NVGPRS() REST_NVGPRS(r1) 94 #endif /* CONFIG_INTERRUPT_SANITIZE_REGISTERS */ 95 96 #define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base) 97 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) 98 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) 99 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) 100 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) 101 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) 102 #define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base) 103 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) 104 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) 105 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) 106 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) 107 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) 108 109 #define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b 110 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) 111 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) 112 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) 113 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) 114 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) 115 #define REST_VR(n,b,base) li b,16*(n); lvx n,base,b 116 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) 117 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) 118 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) 119 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) 120 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) 121 122 #ifdef __BIG_ENDIAN__ 123 #define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base) 124 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base) 125 #else 126 #define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \ 127 STXVD2X(n,b,base); \ 128 XXSWAPD(n,n) 129 130 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \ 131 XXSWAPD(n,n) 132 #endif 133 /* Save the lower 32 VSRs in the thread VSR region */ 134 #define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b) 135 #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) 136 #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base) 137 #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base) 138 #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base) 139 #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) 140 #define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b) 141 #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base) 142 #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base) 143 #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base) 144 #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base) 145 #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base) 146 147 /* 148 * b = base register for addressing, o = base offset from register of 1st EVR 149 * n = first EVR, s = scratch 150 */ 151 #define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b) 152 #define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o) 153 #define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o) 154 #define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o) 155 #define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o) 156 #define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o) 157 #define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n 158 #define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o) 159 #define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o) 160 #define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o) 161 #define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o) 162 #define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o) 163 164 /* Macros to adjust thread priority for hardware multithreading */ 165 #define HMT_VERY_LOW or 31,31,31 # very low priority 166 #define HMT_LOW or 1,1,1 167 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority 168 #define HMT_MEDIUM or 2,2,2 169 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority 170 #define HMT_HIGH or 3,3,3 171 #define HMT_EXTRA_HIGH or 7,7,7 # power7 only 172 173 #ifdef CONFIG_PPC64 174 #define ULONG_SIZE 8 175 #else 176 #define ULONG_SIZE 4 177 #endif 178 #define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE)) 179 #define VCPU_GPR(n) __VCPU_GPR(__REG_##n) 180 181 #ifdef __KERNEL__ 182 183 /* 184 * We use __powerpc64__ here because we want the compat VDSO to use the 32-bit 185 * version below in the else case of the ifdef. 186 */ 187 #ifdef __powerpc64__ 188 189 #define STACKFRAMESIZE 256 190 #define __STK_REG(i) (112 + ((i)-14)*8) 191 #define STK_REG(i) __STK_REG(__REG_##i) 192 193 #ifdef CONFIG_PPC64_ELF_ABI_V2 194 #define STK_GOT 24 195 #define __STK_PARAM(i) (32 + ((i)-3)*8) 196 #else 197 #define STK_GOT 40 198 #define __STK_PARAM(i) (48 + ((i)-3)*8) 199 #endif 200 #define STK_PARAM(i) __STK_PARAM(__REG_##i) 201 202 #ifdef CONFIG_PPC64_ELF_ABI_V2 203 204 #define _GLOBAL(name) \ 205 .align 2 ; \ 206 .type name,@function; \ 207 .globl name; \ 208 name: 209 210 #define _GLOBAL_TOC(name) \ 211 .align 2 ; \ 212 .type name,@function; \ 213 .globl name; \ 214 name: \ 215 0: addis r2,r12,(.TOC.-0b)@ha; \ 216 addi r2,r2,(.TOC.-0b)@l; \ 217 .localentry name,.-name 218 219 #define DOTSYM(a) a 220 221 #else 222 223 #define XGLUE(a,b) a##b 224 #define GLUE(a,b) XGLUE(a,b) 225 226 #define _GLOBAL(name) \ 227 .align 2 ; \ 228 .globl name; \ 229 .globl GLUE(.,name); \ 230 .pushsection ".opd","aw"; \ 231 name: \ 232 .quad GLUE(.,name); \ 233 .quad .TOC.@tocbase; \ 234 .quad 0; \ 235 .popsection; \ 236 .type GLUE(.,name),@function; \ 237 GLUE(.,name): 238 239 #define _GLOBAL_TOC(name) _GLOBAL(name) 240 241 #define DOTSYM(a) GLUE(.,a) 242 243 #endif 244 245 #else /* 32-bit */ 246 247 #define _GLOBAL(n) \ 248 .globl n; \ 249 n: 250 251 #define _GLOBAL_TOC(name) _GLOBAL(name) 252 253 #define DOTSYM(a) a 254 255 #endif 256 257 /* 258 * __kprobes (the C annotation) puts the symbol into the .kprobes.text 259 * section, which gets emitted at the end of regular text. 260 * 261 * _ASM_NOKPROBE_SYMBOL and NOKPROBE_SYMBOL just adds the symbol to 262 * a blacklist. The former is for core kprobe functions/data, the 263 * latter is for those that incdentially must be excluded from probing 264 * and allows them to be linked at more optimal location within text. 265 */ 266 #ifdef CONFIG_KPROBES 267 #define _ASM_NOKPROBE_SYMBOL(entry) \ 268 .pushsection "_kprobe_blacklist","aw"; \ 269 PPC_LONG (entry) ; \ 270 .popsection 271 #else 272 #define _ASM_NOKPROBE_SYMBOL(entry) 273 #endif 274 275 #define FUNC_START(name) _GLOBAL(name) 276 #define FUNC_END(name) 277 278 /* 279 * LOAD_REG_IMMEDIATE(rn, expr) 280 * Loads the value of the constant expression 'expr' into register 'rn' 281 * using immediate instructions only. Use this when it's important not 282 * to reference other data (i.e. on ppc64 when the TOC pointer is not 283 * valid) and when 'expr' is a constant or absolute address. 284 * 285 * LOAD_REG_ADDR(rn, name) 286 * Loads the address of label 'name' into register 'rn'. Use this when 287 * you don't particularly need immediate instructions only, but you need 288 * the whole address in one register (e.g. it's a structure address and 289 * you want to access various offsets within it). On ppc32 this is 290 * identical to LOAD_REG_IMMEDIATE. 291 * 292 * LOAD_REG_ADDR_PIC(rn, name) 293 * Loads the address of label 'name' into register 'run'. Use this when 294 * the kernel doesn't run at the linked or relocated address. Please 295 * note that this macro will clobber the lr register. 296 * 297 * LOAD_REG_ADDRBASE(rn, name) 298 * ADDROFF(name) 299 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into 300 * register 'rn'. ADDROFF(name) returns the remainder of the address as 301 * a constant expression. ADDROFF(name) is a signed expression < 16 bits 302 * in size, so is suitable for use directly as an offset in load and store 303 * instructions. Use this when loading/storing a single word or less as: 304 * LOAD_REG_ADDRBASE(rX, name) 305 * ld rY,ADDROFF(name)(rX) 306 */ 307 308 /* Be careful, this will clobber the lr register. */ 309 #define LOAD_REG_ADDR_PIC(reg, name) \ 310 bcl 20,31,$+4; \ 311 0: mflr reg; \ 312 addis reg,reg,(name - 0b)@ha; \ 313 addi reg,reg,(name - 0b)@l; 314 315 #if defined(__powerpc64__) && defined(HAVE_AS_ATHIGH) 316 #define __AS_ATHIGH high 317 #else 318 #define __AS_ATHIGH h 319 #endif 320 321 .macro __LOAD_REG_IMMEDIATE_32 r, x 322 .if (\x) >= 0x8000 || (\x) < -0x8000 323 lis \r, (\x)@__AS_ATHIGH 324 .if (\x) & 0xffff != 0 325 ori \r, \r, (\x)@l 326 .endif 327 .else 328 li \r, (\x)@l 329 .endif 330 .endm 331 332 .macro __LOAD_REG_IMMEDIATE r, x 333 .if (\x) >= 0x80000000 || (\x) < -0x80000000 334 __LOAD_REG_IMMEDIATE_32 \r, (\x) >> 32 335 sldi \r, \r, 32 336 .if (\x) & 0xffff0000 != 0 337 oris \r, \r, (\x)@__AS_ATHIGH 338 .endif 339 .if (\x) & 0xffff != 0 340 ori \r, \r, (\x)@l 341 .endif 342 .else 343 __LOAD_REG_IMMEDIATE_32 \r, \x 344 .endif 345 .endm 346 347 #ifdef __powerpc64__ 348 349 #define __LOAD_PACA_TOC(reg) \ 350 ld reg,PACATOC(r13) 351 352 #define LOAD_PACA_TOC() \ 353 __LOAD_PACA_TOC(r2) 354 355 #define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE reg, expr 356 357 #define LOAD_REG_IMMEDIATE_SYM(reg, tmp, expr) \ 358 lis tmp, (expr)@highest; \ 359 lis reg, (expr)@__AS_ATHIGH; \ 360 ori tmp, tmp, (expr)@higher; \ 361 ori reg, reg, (expr)@l; \ 362 rldimi reg, tmp, 32, 0 363 364 #define LOAD_REG_ADDR(reg,name) \ 365 addis reg,r2,name@toc@ha; \ 366 addi reg,reg,name@toc@l 367 368 #ifdef CONFIG_PPC_BOOK3E_64 369 /* 370 * This is used in register-constrained interrupt handlers. Not to be used 371 * by BOOK3S. ld complains with "got/toc optimization is not supported" if r2 372 * is not used for the TOC offset, so use @got(tocreg). If the interrupt 373 * handlers saved r2 instead, LOAD_REG_ADDR could be used. 374 */ 375 #define LOAD_REG_ADDR_ALTTOC(reg,tocreg,name) \ 376 ld reg,name@got(tocreg) 377 #endif 378 379 #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name) 380 #define ADDROFF(name) 0 381 382 /* offsets for stack frame layout */ 383 #define LRSAVE 16 384 385 #else /* 32-bit */ 386 387 #define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE_32 reg, expr 388 389 #define LOAD_REG_IMMEDIATE_SYM(reg,expr) \ 390 lis reg,(expr)@ha; \ 391 addi reg,reg,(expr)@l; 392 393 #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE_SYM(reg, name) 394 395 #define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha 396 #define ADDROFF(name) name@l 397 398 /* offsets for stack frame layout */ 399 #define LRSAVE 4 400 401 #endif 402 403 /* various errata or part fixups */ 404 #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_E500) 405 #define MFTB(dest) \ 406 90: mfspr dest, SPRN_TBRL; \ 407 BEGIN_FTR_SECTION_NESTED(96); \ 408 cmpwi dest,0; \ 409 beq- 90b; \ 410 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) 411 #else 412 #define MFTB(dest) MFTBL(dest) 413 #endif 414 415 #ifdef CONFIG_PPC_8xx 416 #define MFTBL(dest) mftb dest 417 #define MFTBU(dest) mftbu dest 418 #else 419 #define MFTBL(dest) mfspr dest, SPRN_TBRL 420 #define MFTBU(dest) mfspr dest, SPRN_TBRU 421 #endif 422 423 #ifndef CONFIG_SMP 424 #define TLBSYNC 425 #else 426 #define TLBSYNC tlbsync; sync 427 #endif 428 429 #ifdef CONFIG_PPC64 430 #define MTOCRF(FXM, RS) \ 431 BEGIN_FTR_SECTION_NESTED(848); \ 432 mtcrf (FXM), RS; \ 433 FTR_SECTION_ELSE_NESTED(848); \ 434 mtocrf (FXM), RS; \ 435 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848) 436 #endif 437 438 /* 439 * This instruction is not implemented on the PPC 603 or 601; however, on 440 * the 403GCX and 405GP tlbia IS defined and tlbie is not. 441 * All of these instructions exist in the 8xx, they have magical powers, 442 * and they must be used. 443 */ 444 445 #if !defined(CONFIG_4xx) && !defined(CONFIG_PPC_8xx) 446 #define tlbia \ 447 li r4,1024; \ 448 mtctr r4; \ 449 lis r4,KERNELBASE@h; \ 450 .machine push; \ 451 .machine "power4"; \ 452 0: tlbie r4; \ 453 .machine pop; \ 454 addi r4,r4,0x1000; \ 455 bdnz 0b 456 #endif 457 458 459 #ifdef CONFIG_IBM440EP_ERR42 460 #define PPC440EP_ERR42 isync 461 #else 462 #define PPC440EP_ERR42 463 #endif 464 465 /* The following stops all load and store data streams associated with stream 466 * ID (ie. streams created explicitly). The embedded and server mnemonics for 467 * dcbt are different so this must only be used for server. 468 */ 469 #define DCBT_BOOK3S_STOP_ALL_STREAM_IDS(scratch) \ 470 lis scratch,0x60000000@h; \ 471 dcbt 0,scratch,0b01010 472 473 /* 474 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them 475 * keep the address intact to be compatible with code shared with 476 * 32-bit classic. 477 * 478 * On the other hand, I find it useful to have them behave as expected 479 * by their name (ie always do the addition) on 64-bit BookE 480 */ 481 #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64) 482 #define toreal(rd) 483 #define fromreal(rd) 484 485 /* 486 * We use addis to ensure compatibility with the "classic" ppc versions of 487 * these macros, which use rs = 0 to get the tophys offset in rd, rather than 488 * converting the address in r0, and so this version has to do that too 489 * (i.e. set register rd to 0 when rs == 0). 490 */ 491 #define tophys(rd,rs) \ 492 addis rd,rs,0 493 494 #define tovirt(rd,rs) \ 495 addis rd,rs,0 496 497 #elif defined(CONFIG_PPC64) 498 #define toreal(rd) /* we can access c000... in real mode */ 499 #define fromreal(rd) 500 501 #define tophys(rd,rs) \ 502 clrldi rd,rs,2 503 504 #define tovirt(rd,rs) \ 505 rotldi rd,rs,16; \ 506 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\ 507 rotldi rd,rd,48 508 #else 509 #define toreal(rd) tophys(rd,rd) 510 #define fromreal(rd) tovirt(rd,rd) 511 512 #define tophys(rd, rs) addis rd, rs, -PAGE_OFFSET@h 513 #define tovirt(rd, rs) addis rd, rs, PAGE_OFFSET@h 514 #endif 515 516 #ifdef CONFIG_PPC_BOOK3S_64 517 #define MTMSRD(r) mtmsrd r 518 #define MTMSR_EERI(reg) mtmsrd reg,1 519 #else 520 #define MTMSRD(r) mtmsr r 521 #define MTMSR_EERI(reg) mtmsr reg 522 #endif 523 524 #endif /* __KERNEL__ */ 525 526 /* The boring bits... */ 527 528 /* Condition Register Bit Fields */ 529 530 #define cr0 0 531 #define cr1 1 532 #define cr2 2 533 #define cr3 3 534 #define cr4 4 535 #define cr5 5 536 #define cr6 6 537 #define cr7 7 538 539 540 /* 541 * General Purpose Registers (GPRs) 542 * 543 * The lower case r0-r31 should be used in preference to the upper 544 * case R0-R31 as they provide more error checking in the assembler. 545 * Use R0-31 only when really nessesary. 546 */ 547 548 #define r0 %r0 549 #define r1 %r1 550 #define r2 %r2 551 #define r3 %r3 552 #define r4 %r4 553 #define r5 %r5 554 #define r6 %r6 555 #define r7 %r7 556 #define r8 %r8 557 #define r9 %r9 558 #define r10 %r10 559 #define r11 %r11 560 #define r12 %r12 561 #define r13 %r13 562 #define r14 %r14 563 #define r15 %r15 564 #define r16 %r16 565 #define r17 %r17 566 #define r18 %r18 567 #define r19 %r19 568 #define r20 %r20 569 #define r21 %r21 570 #define r22 %r22 571 #define r23 %r23 572 #define r24 %r24 573 #define r25 %r25 574 #define r26 %r26 575 #define r27 %r27 576 #define r28 %r28 577 #define r29 %r29 578 #define r30 %r30 579 #define r31 %r31 580 581 582 /* Floating Point Registers (FPRs) */ 583 584 #define fr0 0 585 #define fr1 1 586 #define fr2 2 587 #define fr3 3 588 #define fr4 4 589 #define fr5 5 590 #define fr6 6 591 #define fr7 7 592 #define fr8 8 593 #define fr9 9 594 #define fr10 10 595 #define fr11 11 596 #define fr12 12 597 #define fr13 13 598 #define fr14 14 599 #define fr15 15 600 #define fr16 16 601 #define fr17 17 602 #define fr18 18 603 #define fr19 19 604 #define fr20 20 605 #define fr21 21 606 #define fr22 22 607 #define fr23 23 608 #define fr24 24 609 #define fr25 25 610 #define fr26 26 611 #define fr27 27 612 #define fr28 28 613 #define fr29 29 614 #define fr30 30 615 #define fr31 31 616 617 /* AltiVec Registers (VPRs) */ 618 619 #define v0 0 620 #define v1 1 621 #define v2 2 622 #define v3 3 623 #define v4 4 624 #define v5 5 625 #define v6 6 626 #define v7 7 627 #define v8 8 628 #define v9 9 629 #define v10 10 630 #define v11 11 631 #define v12 12 632 #define v13 13 633 #define v14 14 634 #define v15 15 635 #define v16 16 636 #define v17 17 637 #define v18 18 638 #define v19 19 639 #define v20 20 640 #define v21 21 641 #define v22 22 642 #define v23 23 643 #define v24 24 644 #define v25 25 645 #define v26 26 646 #define v27 27 647 #define v28 28 648 #define v29 29 649 #define v30 30 650 #define v31 31 651 652 /* VSX Registers (VSRs) */ 653 654 #define vs0 0 655 #define vs1 1 656 #define vs2 2 657 #define vs3 3 658 #define vs4 4 659 #define vs5 5 660 #define vs6 6 661 #define vs7 7 662 #define vs8 8 663 #define vs9 9 664 #define vs10 10 665 #define vs11 11 666 #define vs12 12 667 #define vs13 13 668 #define vs14 14 669 #define vs15 15 670 #define vs16 16 671 #define vs17 17 672 #define vs18 18 673 #define vs19 19 674 #define vs20 20 675 #define vs21 21 676 #define vs22 22 677 #define vs23 23 678 #define vs24 24 679 #define vs25 25 680 #define vs26 26 681 #define vs27 27 682 #define vs28 28 683 #define vs29 29 684 #define vs30 30 685 #define vs31 31 686 #define vs32 32 687 #define vs33 33 688 #define vs34 34 689 #define vs35 35 690 #define vs36 36 691 #define vs37 37 692 #define vs38 38 693 #define vs39 39 694 #define vs40 40 695 #define vs41 41 696 #define vs42 42 697 #define vs43 43 698 #define vs44 44 699 #define vs45 45 700 #define vs46 46 701 #define vs47 47 702 #define vs48 48 703 #define vs49 49 704 #define vs50 50 705 #define vs51 51 706 #define vs52 52 707 #define vs53 53 708 #define vs54 54 709 #define vs55 55 710 #define vs56 56 711 #define vs57 57 712 #define vs58 58 713 #define vs59 59 714 #define vs60 60 715 #define vs61 61 716 #define vs62 62 717 #define vs63 63 718 719 /* SPE Registers (EVPRs) */ 720 721 #define evr0 0 722 #define evr1 1 723 #define evr2 2 724 #define evr3 3 725 #define evr4 4 726 #define evr5 5 727 #define evr6 6 728 #define evr7 7 729 #define evr8 8 730 #define evr9 9 731 #define evr10 10 732 #define evr11 11 733 #define evr12 12 734 #define evr13 13 735 #define evr14 14 736 #define evr15 15 737 #define evr16 16 738 #define evr17 17 739 #define evr18 18 740 #define evr19 19 741 #define evr20 20 742 #define evr21 21 743 #define evr22 22 744 #define evr23 23 745 #define evr24 24 746 #define evr25 25 747 #define evr26 26 748 #define evr27 27 749 #define evr28 28 750 #define evr29 29 751 #define evr30 30 752 #define evr31 31 753 754 #define RFSCV .long 0x4c0000a4 755 756 /* 757 * Create an endian fixup trampoline 758 * 759 * This starts with a "tdi 0,0,0x48" instruction which is 760 * essentially a "trap never", and thus akin to a nop. 761 * 762 * The opcode for this instruction read with the wrong endian 763 * however results in a b . + 8 764 * 765 * So essentially we use that trick to execute the following 766 * trampoline in "reverse endian" if we are running with the 767 * MSR_LE bit set the "wrong" way for whatever endianness the 768 * kernel is built for. 769 */ 770 771 #ifdef CONFIG_PPC_BOOK3E_64 772 #define FIXUP_ENDIAN 773 #else 774 /* 775 * This version may be used in HV or non-HV context. 776 * MSR[EE] must be disabled. 777 */ 778 #define FIXUP_ENDIAN \ 779 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ 780 b 191f; /* Skip trampoline if endian is good */ \ 781 .long 0xa600607d; /* mfmsr r11 */ \ 782 .long 0x01006b69; /* xori r11,r11,1 */ \ 783 .long 0x00004039; /* li r10,0 */ \ 784 .long 0x6401417d; /* mtmsrd r10,1 */ \ 785 .long 0x05009f42; /* bcl 20,31,$+4 */ \ 786 .long 0xa602487d; /* mflr r10 */ \ 787 .long 0x14004a39; /* addi r10,r10,20 */ \ 788 .long 0xa6035a7d; /* mtsrr0 r10 */ \ 789 .long 0xa6037b7d; /* mtsrr1 r11 */ \ 790 .long 0x2400004c; /* rfid */ \ 791 191: 792 793 /* 794 * This version that may only be used with MSR[HV]=1 795 * - Does not clear MSR[RI], so more robust. 796 * - Slightly smaller and faster. 797 */ 798 #define FIXUP_ENDIAN_HV \ 799 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ 800 b 191f; /* Skip trampoline if endian is good */ \ 801 .long 0xa600607d; /* mfmsr r11 */ \ 802 .long 0x01006b69; /* xori r11,r11,1 */ \ 803 .long 0x05009f42; /* bcl 20,31,$+4 */ \ 804 .long 0xa602487d; /* mflr r10 */ \ 805 .long 0x14004a39; /* addi r10,r10,20 */ \ 806 .long 0xa64b5a7d; /* mthsrr0 r10 */ \ 807 .long 0xa64b7b7d; /* mthsrr1 r11 */ \ 808 .long 0x2402004c; /* hrfid */ \ 809 191: 810 811 #endif /* !CONFIG_PPC_BOOK3E_64 */ 812 813 #endif /* __ASSEMBLY__ */ 814 815 #define SOFT_MASK_TABLE(_start, _end) \ 816 stringify_in_c(.section __soft_mask_table,"a";)\ 817 stringify_in_c(.balign 8;) \ 818 stringify_in_c(.llong (_start);) \ 819 stringify_in_c(.llong (_end);) \ 820 stringify_in_c(.previous) 821 822 #define RESTART_TABLE(_start, _end, _target) \ 823 stringify_in_c(.section __restart_table,"a";)\ 824 stringify_in_c(.balign 8;) \ 825 stringify_in_c(.llong (_start);) \ 826 stringify_in_c(.llong (_end);) \ 827 stringify_in_c(.llong (_target);) \ 828 stringify_in_c(.previous) 829 830 #ifdef CONFIG_PPC_E500 831 #define BTB_FLUSH(reg) \ 832 lis reg,BUCSR_INIT@h; \ 833 ori reg,reg,BUCSR_INIT@l; \ 834 mtspr SPRN_BUCSR,reg; \ 835 isync; 836 #else 837 #define BTB_FLUSH(reg) 838 #endif /* CONFIG_PPC_E500 */ 839 840 #endif /* _ASM_POWERPC_PPC_ASM_H */ 841