1 /* 2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. 3 */ 4 #ifndef _ASM_POWERPC_PPC_ASM_H 5 #define _ASM_POWERPC_PPC_ASM_H 6 7 #include <linux/init.h> 8 #include <linux/stringify.h> 9 #include <asm/asm-compat.h> 10 #include <asm/processor.h> 11 #include <asm/ppc-opcode.h> 12 #include <asm/firmware.h> 13 14 #ifndef __ASSEMBLY__ 15 #error __FILE__ should only be used in assembler files 16 #else 17 18 #define SZL (BITS_PER_LONG/8) 19 20 /* 21 * Stuff for accurate CPU time accounting. 22 * These macros handle transitions between user and system state 23 * in exception entry and exit and accumulate time to the 24 * user_time and system_time fields in the paca. 25 */ 26 27 #ifndef CONFIG_VIRT_CPU_ACCOUNTING 28 #define ACCOUNT_CPU_USER_ENTRY(ra, rb) 29 #define ACCOUNT_CPU_USER_EXIT(ra, rb) 30 #define ACCOUNT_STOLEN_TIME 31 #else 32 #define ACCOUNT_CPU_USER_ENTRY(ra, rb) \ 33 beq 2f; /* if from kernel mode */ \ 34 MFTB(ra); /* get timebase */ \ 35 ld rb,PACA_STARTTIME_USER(r13); \ 36 std ra,PACA_STARTTIME(r13); \ 37 subf rb,rb,ra; /* subtract start value */ \ 38 ld ra,PACA_USER_TIME(r13); \ 39 add ra,ra,rb; /* add on to user time */ \ 40 std ra,PACA_USER_TIME(r13); \ 41 2: 42 43 #define ACCOUNT_CPU_USER_EXIT(ra, rb) \ 44 MFTB(ra); /* get timebase */ \ 45 ld rb,PACA_STARTTIME(r13); \ 46 std ra,PACA_STARTTIME_USER(r13); \ 47 subf rb,rb,ra; /* subtract start value */ \ 48 ld ra,PACA_SYSTEM_TIME(r13); \ 49 add ra,ra,rb; /* add on to system time */ \ 50 std ra,PACA_SYSTEM_TIME(r13) 51 52 #ifdef CONFIG_PPC_SPLPAR 53 #define ACCOUNT_STOLEN_TIME \ 54 BEGIN_FW_FTR_SECTION; \ 55 beq 33f; \ 56 /* from user - see if there are any DTL entries to process */ \ 57 ld r10,PACALPPACAPTR(r13); /* get ptr to VPA */ \ 58 ld r11,PACA_DTL_RIDX(r13); /* get log read index */ \ 59 ld r10,LPPACA_DTLIDX(r10); /* get log write index */ \ 60 cmpd cr1,r11,r10; \ 61 beq+ cr1,33f; \ 62 bl .accumulate_stolen_time; \ 63 ld r12,_MSR(r1); \ 64 andi. r10,r12,MSR_PR; /* Restore cr0 (coming from user) */ \ 65 33: \ 66 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR) 67 68 #else /* CONFIG_PPC_SPLPAR */ 69 #define ACCOUNT_STOLEN_TIME 70 71 #endif /* CONFIG_PPC_SPLPAR */ 72 73 #endif /* CONFIG_VIRT_CPU_ACCOUNTING */ 74 75 /* 76 * Macros for storing registers into and loading registers from 77 * exception frames. 78 */ 79 #ifdef __powerpc64__ 80 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base) 81 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base) 82 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) 83 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) 84 #else 85 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) 86 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) 87 #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \ 88 SAVE_10GPRS(22, base) 89 #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \ 90 REST_10GPRS(22, base) 91 #endif 92 93 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) 94 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) 95 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) 96 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) 97 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) 98 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) 99 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) 100 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) 101 102 #define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) 103 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) 104 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) 105 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) 106 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) 107 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) 108 #define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) 109 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) 110 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) 111 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) 112 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) 113 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) 114 115 #define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,base,b 116 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) 117 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) 118 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) 119 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) 120 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) 121 #define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,base,b 122 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) 123 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) 124 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) 125 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) 126 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) 127 128 /* Save the lower 32 VSRs in the thread VSR region */ 129 #define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,R##base,R##b) 130 #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) 131 #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base) 132 #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base) 133 #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base) 134 #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) 135 #define REST_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,R##base,R##b) 136 #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base) 137 #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base) 138 #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base) 139 #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base) 140 #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base) 141 /* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */ 142 #define SAVE_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,R##base,R##b) 143 #define SAVE_2VSRSU(n,b,base) SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base) 144 #define SAVE_4VSRSU(n,b,base) SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base) 145 #define SAVE_8VSRSU(n,b,base) SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base) 146 #define SAVE_16VSRSU(n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base) 147 #define SAVE_32VSRSU(n,b,base) SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base) 148 #define REST_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,R##base,R##b) 149 #define REST_2VSRSU(n,b,base) REST_VSRU(n,b,base); REST_VSRU(n+1,b,base) 150 #define REST_4VSRSU(n,b,base) REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base) 151 #define REST_8VSRSU(n,b,base) REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base) 152 #define REST_16VSRSU(n,b,base) REST_8VSRSU(n,b,base); REST_8VSRSU(n+8,b,base) 153 #define REST_32VSRSU(n,b,base) REST_16VSRSU(n,b,base); REST_16VSRSU(n+16,b,base) 154 155 /* 156 * b = base register for addressing, o = base offset from register of 1st EVR 157 * n = first EVR, s = scratch 158 */ 159 #define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b) 160 #define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o) 161 #define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o) 162 #define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o) 163 #define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o) 164 #define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o) 165 #define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n 166 #define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o) 167 #define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o) 168 #define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o) 169 #define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o) 170 #define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o) 171 172 /* Macros to adjust thread priority for hardware multithreading */ 173 #define HMT_VERY_LOW or 31,31,31 # very low priority 174 #define HMT_LOW or 1,1,1 175 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority 176 #define HMT_MEDIUM or 2,2,2 177 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority 178 #define HMT_HIGH or 3,3,3 179 #define HMT_EXTRA_HIGH or 7,7,7 # power7 only 180 181 #ifdef CONFIG_PPC64 182 #define ULONG_SIZE 8 183 #else 184 #define ULONG_SIZE 4 185 #endif 186 #define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE)) 187 #define VCPU_GPR(n) __VCPU_GPR(__REG_##n) 188 189 #ifdef __KERNEL__ 190 #ifdef CONFIG_PPC64 191 192 #define STACKFRAMESIZE 256 193 #define __STK_REG(i) (112 + ((i)-14)*8) 194 #define STK_REG(i) __STK_REG(__REG_##i) 195 196 #define __STK_PARAM(i) (48 + ((i)-3)*8) 197 #define STK_PARAM(i) __STK_PARAM(__REG_##i) 198 199 #define XGLUE(a,b) a##b 200 #define GLUE(a,b) XGLUE(a,b) 201 202 #define _GLOBAL(name) \ 203 .section ".text"; \ 204 .align 2 ; \ 205 .globl name; \ 206 .globl GLUE(.,name); \ 207 .section ".opd","aw"; \ 208 name: \ 209 .quad GLUE(.,name); \ 210 .quad .TOC.@tocbase; \ 211 .quad 0; \ 212 .previous; \ 213 .type GLUE(.,name),@function; \ 214 GLUE(.,name): 215 216 #define _INIT_GLOBAL(name) \ 217 __REF; \ 218 .align 2 ; \ 219 .globl name; \ 220 .globl GLUE(.,name); \ 221 .section ".opd","aw"; \ 222 name: \ 223 .quad GLUE(.,name); \ 224 .quad .TOC.@tocbase; \ 225 .quad 0; \ 226 .previous; \ 227 .type GLUE(.,name),@function; \ 228 GLUE(.,name): 229 230 #define _KPROBE(name) \ 231 .section ".kprobes.text","a"; \ 232 .align 2 ; \ 233 .globl name; \ 234 .globl GLUE(.,name); \ 235 .section ".opd","aw"; \ 236 name: \ 237 .quad GLUE(.,name); \ 238 .quad .TOC.@tocbase; \ 239 .quad 0; \ 240 .previous; \ 241 .type GLUE(.,name),@function; \ 242 GLUE(.,name): 243 244 #define _STATIC(name) \ 245 .section ".text"; \ 246 .align 2 ; \ 247 .section ".opd","aw"; \ 248 name: \ 249 .quad GLUE(.,name); \ 250 .quad .TOC.@tocbase; \ 251 .quad 0; \ 252 .previous; \ 253 .type GLUE(.,name),@function; \ 254 GLUE(.,name): 255 256 #define _INIT_STATIC(name) \ 257 __REF; \ 258 .align 2 ; \ 259 .section ".opd","aw"; \ 260 name: \ 261 .quad GLUE(.,name); \ 262 .quad .TOC.@tocbase; \ 263 .quad 0; \ 264 .previous; \ 265 .type GLUE(.,name),@function; \ 266 GLUE(.,name): 267 268 #else /* 32-bit */ 269 270 #define _ENTRY(n) \ 271 .globl n; \ 272 n: 273 274 #define _GLOBAL(n) \ 275 .text; \ 276 .stabs __stringify(n:F-1),N_FUN,0,0,n;\ 277 .globl n; \ 278 n: 279 280 #define _KPROBE(n) \ 281 .section ".kprobes.text","a"; \ 282 .globl n; \ 283 n: 284 285 #endif 286 287 /* 288 * LOAD_REG_IMMEDIATE(rn, expr) 289 * Loads the value of the constant expression 'expr' into register 'rn' 290 * using immediate instructions only. Use this when it's important not 291 * to reference other data (i.e. on ppc64 when the TOC pointer is not 292 * valid) and when 'expr' is a constant or absolute address. 293 * 294 * LOAD_REG_ADDR(rn, name) 295 * Loads the address of label 'name' into register 'rn'. Use this when 296 * you don't particularly need immediate instructions only, but you need 297 * the whole address in one register (e.g. it's a structure address and 298 * you want to access various offsets within it). On ppc32 this is 299 * identical to LOAD_REG_IMMEDIATE. 300 * 301 * LOAD_REG_ADDRBASE(rn, name) 302 * ADDROFF(name) 303 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into 304 * register 'rn'. ADDROFF(name) returns the remainder of the address as 305 * a constant expression. ADDROFF(name) is a signed expression < 16 bits 306 * in size, so is suitable for use directly as an offset in load and store 307 * instructions. Use this when loading/storing a single word or less as: 308 * LOAD_REG_ADDRBASE(rX, name) 309 * ld rY,ADDROFF(name)(rX) 310 */ 311 #ifdef __powerpc64__ 312 #define LOAD_REG_IMMEDIATE(reg,expr) \ 313 lis reg,(expr)@highest; \ 314 ori reg,reg,(expr)@higher; \ 315 rldicr reg,reg,32,31; \ 316 oris reg,reg,(expr)@h; \ 317 ori reg,reg,(expr)@l; 318 319 #define LOAD_REG_ADDR(reg,name) \ 320 ld reg,name@got(r2) 321 322 #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name) 323 #define ADDROFF(name) 0 324 325 /* offsets for stack frame layout */ 326 #define LRSAVE 16 327 328 #else /* 32-bit */ 329 330 #define LOAD_REG_IMMEDIATE(reg,expr) \ 331 lis reg,(expr)@ha; \ 332 addi reg,reg,(expr)@l; 333 334 #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name) 335 336 #define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha 337 #define ADDROFF(name) name@l 338 339 /* offsets for stack frame layout */ 340 #define LRSAVE 4 341 342 #endif 343 344 /* various errata or part fixups */ 345 #ifdef CONFIG_PPC601_SYNC_FIX 346 #define SYNC \ 347 BEGIN_FTR_SECTION \ 348 sync; \ 349 isync; \ 350 END_FTR_SECTION_IFSET(CPU_FTR_601) 351 #define SYNC_601 \ 352 BEGIN_FTR_SECTION \ 353 sync; \ 354 END_FTR_SECTION_IFSET(CPU_FTR_601) 355 #define ISYNC_601 \ 356 BEGIN_FTR_SECTION \ 357 isync; \ 358 END_FTR_SECTION_IFSET(CPU_FTR_601) 359 #else 360 #define SYNC 361 #define SYNC_601 362 #define ISYNC_601 363 #endif 364 365 #ifdef CONFIG_PPC_CELL 366 #define MFTB(dest) \ 367 90: mftb dest; \ 368 BEGIN_FTR_SECTION_NESTED(96); \ 369 cmpwi dest,0; \ 370 beq- 90b; \ 371 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) 372 #else 373 #define MFTB(dest) mftb dest 374 #endif 375 376 #ifndef CONFIG_SMP 377 #define TLBSYNC 378 #else /* CONFIG_SMP */ 379 /* tlbsync is not implemented on 601 */ 380 #define TLBSYNC \ 381 BEGIN_FTR_SECTION \ 382 tlbsync; \ 383 sync; \ 384 END_FTR_SECTION_IFCLR(CPU_FTR_601) 385 #endif 386 387 #ifdef CONFIG_PPC64 388 #define MTOCRF(FXM, RS) \ 389 BEGIN_FTR_SECTION_NESTED(848); \ 390 mtcrf (FXM), RS; \ 391 FTR_SECTION_ELSE_NESTED(848); \ 392 mtocrf (FXM), RS; \ 393 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848) 394 #endif 395 396 /* 397 * This instruction is not implemented on the PPC 603 or 601; however, on 398 * the 403GCX and 405GP tlbia IS defined and tlbie is not. 399 * All of these instructions exist in the 8xx, they have magical powers, 400 * and they must be used. 401 */ 402 403 #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx) 404 #define tlbia \ 405 li r4,1024; \ 406 mtctr r4; \ 407 lis r4,KERNELBASE@h; \ 408 0: tlbie r4; \ 409 addi r4,r4,0x1000; \ 410 bdnz 0b 411 #endif 412 413 414 #ifdef CONFIG_IBM440EP_ERR42 415 #define PPC440EP_ERR42 isync 416 #else 417 #define PPC440EP_ERR42 418 #endif 419 420 /* 421 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them 422 * keep the address intact to be compatible with code shared with 423 * 32-bit classic. 424 * 425 * On the other hand, I find it useful to have them behave as expected 426 * by their name (ie always do the addition) on 64-bit BookE 427 */ 428 #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64) 429 #define toreal(rd) 430 #define fromreal(rd) 431 432 /* 433 * We use addis to ensure compatibility with the "classic" ppc versions of 434 * these macros, which use rs = 0 to get the tophys offset in rd, rather than 435 * converting the address in r0, and so this version has to do that too 436 * (i.e. set register rd to 0 when rs == 0). 437 */ 438 #define tophys(rd,rs) \ 439 addis rd,rs,0 440 441 #define tovirt(rd,rs) \ 442 addis rd,rs,0 443 444 #elif defined(CONFIG_PPC64) 445 #define toreal(rd) /* we can access c000... in real mode */ 446 #define fromreal(rd) 447 448 #define tophys(rd,rs) \ 449 clrldi rd,rs,2 450 451 #define tovirt(rd,rs) \ 452 rotldi rd,rs,16; \ 453 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\ 454 rotldi rd,rd,48 455 #else 456 /* 457 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the 458 * physical base address of RAM at compile time. 459 */ 460 #define toreal(rd) tophys(rd,rd) 461 #define fromreal(rd) tovirt(rd,rd) 462 463 #define tophys(rd,rs) \ 464 0: addis rd,rs,-PAGE_OFFSET@h; \ 465 .section ".vtop_fixup","aw"; \ 466 .align 1; \ 467 .long 0b; \ 468 .previous 469 470 #define tovirt(rd,rs) \ 471 0: addis rd,rs,PAGE_OFFSET@h; \ 472 .section ".ptov_fixup","aw"; \ 473 .align 1; \ 474 .long 0b; \ 475 .previous 476 #endif 477 478 #ifdef CONFIG_PPC_BOOK3S_64 479 #define RFI rfid 480 #define MTMSRD(r) mtmsrd r 481 #define MTMSR_EERI(reg) mtmsrd reg,1 482 #else 483 #define FIX_SRR1(ra, rb) 484 #ifndef CONFIG_40x 485 #define RFI rfi 486 #else 487 #define RFI rfi; b . /* Prevent prefetch past rfi */ 488 #endif 489 #define MTMSRD(r) mtmsr r 490 #define MTMSR_EERI(reg) mtmsr reg 491 #define CLR_TOP32(r) 492 #endif 493 494 #endif /* __KERNEL__ */ 495 496 /* The boring bits... */ 497 498 /* Condition Register Bit Fields */ 499 500 #define cr0 0 501 #define cr1 1 502 #define cr2 2 503 #define cr3 3 504 #define cr4 4 505 #define cr5 5 506 #define cr6 6 507 #define cr7 7 508 509 510 /* 511 * General Purpose Registers (GPRs) 512 * 513 * The lower case r0-r31 should be used in preference to the upper 514 * case R0-R31 as they provide more error checking in the assembler. 515 * Use R0-31 only when really nessesary. 516 */ 517 518 #define r0 %r0 519 #define r1 %r1 520 #define r2 %r2 521 #define r3 %r3 522 #define r4 %r4 523 #define r5 %r5 524 #define r6 %r6 525 #define r7 %r7 526 #define r8 %r8 527 #define r9 %r9 528 #define r10 %r10 529 #define r11 %r11 530 #define r12 %r12 531 #define r13 %r13 532 #define r14 %r14 533 #define r15 %r15 534 #define r16 %r16 535 #define r17 %r17 536 #define r18 %r18 537 #define r19 %r19 538 #define r20 %r20 539 #define r21 %r21 540 #define r22 %r22 541 #define r23 %r23 542 #define r24 %r24 543 #define r25 %r25 544 #define r26 %r26 545 #define r27 %r27 546 #define r28 %r28 547 #define r29 %r29 548 #define r30 %r30 549 #define r31 %r31 550 551 552 /* Floating Point Registers (FPRs) */ 553 554 #define fr0 0 555 #define fr1 1 556 #define fr2 2 557 #define fr3 3 558 #define fr4 4 559 #define fr5 5 560 #define fr6 6 561 #define fr7 7 562 #define fr8 8 563 #define fr9 9 564 #define fr10 10 565 #define fr11 11 566 #define fr12 12 567 #define fr13 13 568 #define fr14 14 569 #define fr15 15 570 #define fr16 16 571 #define fr17 17 572 #define fr18 18 573 #define fr19 19 574 #define fr20 20 575 #define fr21 21 576 #define fr22 22 577 #define fr23 23 578 #define fr24 24 579 #define fr25 25 580 #define fr26 26 581 #define fr27 27 582 #define fr28 28 583 #define fr29 29 584 #define fr30 30 585 #define fr31 31 586 587 /* AltiVec Registers (VPRs) */ 588 589 #define vr0 0 590 #define vr1 1 591 #define vr2 2 592 #define vr3 3 593 #define vr4 4 594 #define vr5 5 595 #define vr6 6 596 #define vr7 7 597 #define vr8 8 598 #define vr9 9 599 #define vr10 10 600 #define vr11 11 601 #define vr12 12 602 #define vr13 13 603 #define vr14 14 604 #define vr15 15 605 #define vr16 16 606 #define vr17 17 607 #define vr18 18 608 #define vr19 19 609 #define vr20 20 610 #define vr21 21 611 #define vr22 22 612 #define vr23 23 613 #define vr24 24 614 #define vr25 25 615 #define vr26 26 616 #define vr27 27 617 #define vr28 28 618 #define vr29 29 619 #define vr30 30 620 #define vr31 31 621 622 /* VSX Registers (VSRs) */ 623 624 #define vsr0 0 625 #define vsr1 1 626 #define vsr2 2 627 #define vsr3 3 628 #define vsr4 4 629 #define vsr5 5 630 #define vsr6 6 631 #define vsr7 7 632 #define vsr8 8 633 #define vsr9 9 634 #define vsr10 10 635 #define vsr11 11 636 #define vsr12 12 637 #define vsr13 13 638 #define vsr14 14 639 #define vsr15 15 640 #define vsr16 16 641 #define vsr17 17 642 #define vsr18 18 643 #define vsr19 19 644 #define vsr20 20 645 #define vsr21 21 646 #define vsr22 22 647 #define vsr23 23 648 #define vsr24 24 649 #define vsr25 25 650 #define vsr26 26 651 #define vsr27 27 652 #define vsr28 28 653 #define vsr29 29 654 #define vsr30 30 655 #define vsr31 31 656 #define vsr32 32 657 #define vsr33 33 658 #define vsr34 34 659 #define vsr35 35 660 #define vsr36 36 661 #define vsr37 37 662 #define vsr38 38 663 #define vsr39 39 664 #define vsr40 40 665 #define vsr41 41 666 #define vsr42 42 667 #define vsr43 43 668 #define vsr44 44 669 #define vsr45 45 670 #define vsr46 46 671 #define vsr47 47 672 #define vsr48 48 673 #define vsr49 49 674 #define vsr50 50 675 #define vsr51 51 676 #define vsr52 52 677 #define vsr53 53 678 #define vsr54 54 679 #define vsr55 55 680 #define vsr56 56 681 #define vsr57 57 682 #define vsr58 58 683 #define vsr59 59 684 #define vsr60 60 685 #define vsr61 61 686 #define vsr62 62 687 #define vsr63 63 688 689 /* SPE Registers (EVPRs) */ 690 691 #define evr0 0 692 #define evr1 1 693 #define evr2 2 694 #define evr3 3 695 #define evr4 4 696 #define evr5 5 697 #define evr6 6 698 #define evr7 7 699 #define evr8 8 700 #define evr9 9 701 #define evr10 10 702 #define evr11 11 703 #define evr12 12 704 #define evr13 13 705 #define evr14 14 706 #define evr15 15 707 #define evr16 16 708 #define evr17 17 709 #define evr18 18 710 #define evr19 19 711 #define evr20 20 712 #define evr21 21 713 #define evr22 22 714 #define evr23 23 715 #define evr24 24 716 #define evr25 25 717 #define evr26 26 718 #define evr27 27 719 #define evr28 28 720 #define evr29 29 721 #define evr30 30 722 #define evr31 31 723 724 /* some stab codes */ 725 #define N_FUN 36 726 #define N_RSYM 64 727 #define N_SLINE 68 728 #define N_SO 100 729 730 #endif /* __ASSEMBLY__ */ 731 732 #endif /* _ASM_POWERPC_PPC_ASM_H */ 733